2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 #include <linux/slab.h>
19 #include <linux/delay.h>
20 #include <linux/err.h>
21 #include <linux/clk.h>
22 #include <linux/clk-provider.h>
26 #define PLL_BASE_BYPASS BIT(31)
27 #define PLL_BASE_ENABLE BIT(30)
28 #define PLL_BASE_REF_ENABLE BIT(29)
29 #define PLL_BASE_OVERRIDE BIT(28)
31 #define PLL_BASE_DIVP_SHIFT 20
32 #define PLL_BASE_DIVP_WIDTH 3
33 #define PLL_BASE_DIVN_SHIFT 8
34 #define PLL_BASE_DIVN_WIDTH 10
35 #define PLL_BASE_DIVM_SHIFT 0
36 #define PLL_BASE_DIVM_WIDTH 5
37 #define PLLU_POST_DIVP_MASK 0x1
39 #define PLL_MISC_DCCON_SHIFT 20
40 #define PLL_MISC_CPCON_SHIFT 8
41 #define PLL_MISC_CPCON_WIDTH 4
42 #define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1)
43 #define PLL_MISC_LFCON_SHIFT 4
44 #define PLL_MISC_LFCON_WIDTH 4
45 #define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1)
46 #define PLL_MISC_VCOCON_SHIFT 0
47 #define PLL_MISC_VCOCON_WIDTH 4
48 #define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1)
50 #define OUT_OF_TABLE_CPCON 8
52 #define PMC_PLLP_WB0_OVERRIDE 0xf8
53 #define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE BIT(12)
54 #define PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE BIT(11)
56 #define PLL_POST_LOCK_DELAY 50
58 #define PLLDU_LFCON_SET_DIVN 600
60 #define PLLE_BASE_DIVCML_SHIFT 24
61 #define PLLE_BASE_DIVCML_MASK 0xf
62 #define PLLE_BASE_DIVP_SHIFT 16
63 #define PLLE_BASE_DIVP_WIDTH 6
64 #define PLLE_BASE_DIVN_SHIFT 8
65 #define PLLE_BASE_DIVN_WIDTH 8
66 #define PLLE_BASE_DIVM_SHIFT 0
67 #define PLLE_BASE_DIVM_WIDTH 8
68 #define PLLE_BASE_ENABLE BIT(31)
70 #define PLLE_MISC_SETUP_BASE_SHIFT 16
71 #define PLLE_MISC_SETUP_BASE_MASK (0xffff << PLLE_MISC_SETUP_BASE_SHIFT)
72 #define PLLE_MISC_LOCK_ENABLE BIT(9)
73 #define PLLE_MISC_READY BIT(15)
74 #define PLLE_MISC_SETUP_EX_SHIFT 2
75 #define PLLE_MISC_SETUP_EX_MASK (3 << PLLE_MISC_SETUP_EX_SHIFT)
76 #define PLLE_MISC_SETUP_MASK (PLLE_MISC_SETUP_BASE_MASK | \
77 PLLE_MISC_SETUP_EX_MASK)
78 #define PLLE_MISC_SETUP_VALUE (7 << PLLE_MISC_SETUP_BASE_SHIFT)
80 #define PLLE_SS_CTRL 0x68
81 #define PLLE_SS_CNTL_BYPASS_SS BIT(10)
82 #define PLLE_SS_CNTL_INTERP_RESET BIT(11)
83 #define PLLE_SS_CNTL_SSC_BYP BIT(12)
84 #define PLLE_SS_CNTL_CENTER BIT(14)
85 #define PLLE_SS_CNTL_INVERT BIT(15)
86 #define PLLE_SS_DISABLE (PLLE_SS_CNTL_BYPASS_SS | PLLE_SS_CNTL_INTERP_RESET |\
88 #define PLLE_SS_MAX_MASK 0x1ff
89 #define PLLE_SS_MAX_VAL_TEGRA114 0x25
90 #define PLLE_SS_MAX_VAL_TEGRA210 0x21
91 #define PLLE_SS_INC_MASK (0xff << 16)
92 #define PLLE_SS_INC_VAL (0x1 << 16)
93 #define PLLE_SS_INCINTRV_MASK (0x3f << 24)
94 #define PLLE_SS_INCINTRV_VAL_TEGRA114 (0x20 << 24)
95 #define PLLE_SS_INCINTRV_VAL_TEGRA210 (0x23 << 24)
96 #define PLLE_SS_COEFFICIENTS_MASK \
97 (PLLE_SS_MAX_MASK | PLLE_SS_INC_MASK | PLLE_SS_INCINTRV_MASK)
98 #define PLLE_SS_COEFFICIENTS_VAL_TEGRA114 \
99 (PLLE_SS_MAX_VAL_TEGRA114 | PLLE_SS_INC_VAL |\
100 PLLE_SS_INCINTRV_VAL_TEGRA114)
101 #define PLLE_SS_COEFFICIENTS_VAL_TEGRA210 \
102 (PLLE_SS_MAX_VAL_TEGRA210 | PLLE_SS_INC_VAL |\
103 PLLE_SS_INCINTRV_VAL_TEGRA210)
105 #define PLLE_AUX_PLLP_SEL BIT(2)
106 #define PLLE_AUX_USE_LOCKDET BIT(3)
107 #define PLLE_AUX_ENABLE_SWCTL BIT(4)
108 #define PLLE_AUX_SS_SWCTL BIT(6)
109 #define PLLE_AUX_SEQ_ENABLE BIT(24)
110 #define PLLE_AUX_SEQ_START_STATE BIT(25)
111 #define PLLE_AUX_PLLRE_SEL BIT(28)
112 #define PLLE_AUX_SS_SEQ_INCLUDE BIT(31)
114 #define XUSBIO_PLL_CFG0 0x51c
115 #define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0)
116 #define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL BIT(2)
117 #define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET BIT(6)
118 #define XUSBIO_PLL_CFG0_SEQ_ENABLE BIT(24)
119 #define XUSBIO_PLL_CFG0_SEQ_START_STATE BIT(25)
121 #define SATA_PLL_CFG0 0x490
122 #define SATA_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0)
123 #define SATA_PLL_CFG0_PADPLL_USE_LOCKDET BIT(2)
124 #define SATA_PLL_CFG0_SEQ_ENABLE BIT(24)
125 #define SATA_PLL_CFG0_SEQ_START_STATE BIT(25)
127 #define PLLE_MISC_PLLE_PTS BIT(8)
128 #define PLLE_MISC_IDDQ_SW_VALUE BIT(13)
129 #define PLLE_MISC_IDDQ_SW_CTRL BIT(14)
130 #define PLLE_MISC_VREG_BG_CTRL_SHIFT 4
131 #define PLLE_MISC_VREG_BG_CTRL_MASK (3 << PLLE_MISC_VREG_BG_CTRL_SHIFT)
132 #define PLLE_MISC_VREG_CTRL_SHIFT 2
133 #define PLLE_MISC_VREG_CTRL_MASK (2 << PLLE_MISC_VREG_CTRL_SHIFT)
135 #define PLLCX_MISC_STROBE BIT(31)
136 #define PLLCX_MISC_RESET BIT(30)
137 #define PLLCX_MISC_SDM_DIV_SHIFT 28
138 #define PLLCX_MISC_SDM_DIV_MASK (0x3 << PLLCX_MISC_SDM_DIV_SHIFT)
139 #define PLLCX_MISC_FILT_DIV_SHIFT 26
140 #define PLLCX_MISC_FILT_DIV_MASK (0x3 << PLLCX_MISC_FILT_DIV_SHIFT)
141 #define PLLCX_MISC_ALPHA_SHIFT 18
142 #define PLLCX_MISC_DIV_LOW_RANGE \
143 ((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | \
144 (0x1 << PLLCX_MISC_FILT_DIV_SHIFT))
145 #define PLLCX_MISC_DIV_HIGH_RANGE \
146 ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | \
147 (0x2 << PLLCX_MISC_FILT_DIV_SHIFT))
148 #define PLLCX_MISC_COEF_LOW_RANGE \
149 ((0x14 << PLLCX_MISC_KA_SHIFT) | (0x38 << PLLCX_MISC_KB_SHIFT))
150 #define PLLCX_MISC_KA_SHIFT 2
151 #define PLLCX_MISC_KB_SHIFT 9
152 #define PLLCX_MISC_DEFAULT (PLLCX_MISC_COEF_LOW_RANGE | \
153 (0x19 << PLLCX_MISC_ALPHA_SHIFT) | \
154 PLLCX_MISC_DIV_LOW_RANGE | \
156 #define PLLCX_MISC1_DEFAULT 0x000d2308
157 #define PLLCX_MISC2_DEFAULT 0x30211200
158 #define PLLCX_MISC3_DEFAULT 0x200
160 #define PMC_SATA_PWRGT 0x1ac
161 #define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5)
162 #define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4)
164 #define PLLSS_MISC_KCP 0
165 #define PLLSS_MISC_KVCO 0
166 #define PLLSS_MISC_SETUP 0
167 #define PLLSS_EN_SDM 0
168 #define PLLSS_EN_SSC 0
169 #define PLLSS_EN_DITHER2 0
170 #define PLLSS_EN_DITHER 1
171 #define PLLSS_SDM_RESET 0
172 #define PLLSS_CLAMP 0
173 #define PLLSS_SDM_SSC_MAX 0
174 #define PLLSS_SDM_SSC_MIN 0
175 #define PLLSS_SDM_SSC_STEP 0
176 #define PLLSS_SDM_DIN 0
177 #define PLLSS_MISC_DEFAULT ((PLLSS_MISC_KCP << 25) | \
178 (PLLSS_MISC_KVCO << 24) | \
180 #define PLLSS_CFG_DEFAULT ((PLLSS_EN_SDM << 31) | \
181 (PLLSS_EN_SSC << 30) | \
182 (PLLSS_EN_DITHER2 << 29) | \
183 (PLLSS_EN_DITHER << 28) | \
184 (PLLSS_SDM_RESET) << 27 | \
186 #define PLLSS_CTRL1_DEFAULT \
187 ((PLLSS_SDM_SSC_MAX << 16) | PLLSS_SDM_SSC_MIN)
188 #define PLLSS_CTRL2_DEFAULT \
189 ((PLLSS_SDM_SSC_STEP << 16) | PLLSS_SDM_DIN)
190 #define PLLSS_LOCK_OVERRIDE BIT(24)
191 #define PLLSS_REF_SRC_SEL_SHIFT 25
192 #define PLLSS_REF_SRC_SEL_MASK (3 << PLLSS_REF_SRC_SEL_SHIFT)
194 #define UTMIP_PLL_CFG1 0x484
195 #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
196 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
197 #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
198 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
199 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15)
200 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
201 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17)
203 #define UTMIP_PLL_CFG2 0x488
204 #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6)
205 #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
206 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
207 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP BIT(1)
208 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
209 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP BIT(3)
210 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
211 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP BIT(5)
212 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN BIT(24)
213 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP BIT(25)
214 #define UTMIP_PLL_CFG2_PHY_XTAL_CLOCKEN BIT(30)
216 #define UTMIPLL_HW_PWRDN_CFG0 0x52c
217 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0)
218 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1)
219 #define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
220 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4)
221 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5)
222 #define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
223 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
224 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25)
226 #define PLLU_HW_PWRDN_CFG0 0x530
227 #define PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL BIT(0)
228 #define PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
229 #define PLLU_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
230 #define PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT BIT(7)
231 #define PLLU_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
232 #define PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE BIT(28)
234 #define XUSB_PLL_CFG0 0x534
235 #define XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY 0x3ff
236 #define XUSB_PLL_CFG0_PLLU_LOCK_DLY (0x3ff << 14)
238 #define PLLU_BASE_CLKENABLE_USB BIT(21)
239 #define PLLU_BASE_OVERRIDE BIT(24)
241 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
242 #define pll_readl_base(p) pll_readl(p->params->base_reg, p)
243 #define pll_readl_misc(p) pll_readl(p->params->misc_reg, p)
244 #define pll_override_readl(offset, p) readl_relaxed(p->pmc + offset)
245 #define pll_readl_sdm_din(p) pll_readl(p->params->sdm_din_reg, p)
246 #define pll_readl_sdm_ctrl(p) pll_readl(p->params->sdm_ctrl_reg, p)
248 #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset)
249 #define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p)
250 #define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p)
251 #define pll_override_writel(val, offset, p) writel(val, p->pmc + offset)
252 #define pll_writel_sdm_din(val, p) pll_writel(val, p->params->sdm_din_reg, p)
253 #define pll_writel_sdm_ctrl(val, p) pll_writel(val, p->params->sdm_ctrl_reg, p)
255 #define mask(w) ((1 << (w)) - 1)
256 #define divm_mask(p) mask(p->params->div_nmp->divm_width)
257 #define divn_mask(p) mask(p->params->div_nmp->divn_width)
258 #define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\
259 mask(p->params->div_nmp->divp_width))
260 #define sdm_din_mask(p) p->params->sdm_din_mask
261 #define sdm_en_mask(p) p->params->sdm_ctrl_en_mask
263 #define divm_shift(p) (p)->params->div_nmp->divm_shift
264 #define divn_shift(p) (p)->params->div_nmp->divn_shift
265 #define divp_shift(p) (p)->params->div_nmp->divp_shift
267 #define divm_mask_shifted(p) (divm_mask(p) << divm_shift(p))
268 #define divn_mask_shifted(p) (divn_mask(p) << divn_shift(p))
269 #define divp_mask_shifted(p) (divp_mask(p) << divp_shift(p))
271 #define divm_max(p) (divm_mask(p))
272 #define divn_max(p) (divn_mask(p))
273 #define divp_max(p) (1 << (divp_mask(p)))
275 #define sdin_din_to_data(din) ((u16)((din) ? : 0xFFFFU))
276 #define sdin_data_to_din(dat) (((dat) == 0xFFFFU) ? 0 : (s16)dat)
278 static struct div_nmp default_nmp = {
279 .divn_shift = PLL_BASE_DIVN_SHIFT,
280 .divn_width = PLL_BASE_DIVN_WIDTH,
281 .divm_shift = PLL_BASE_DIVM_SHIFT,
282 .divm_width = PLL_BASE_DIVM_WIDTH,
283 .divp_shift = PLL_BASE_DIVP_SHIFT,
284 .divp_width = PLL_BASE_DIVP_WIDTH,
287 static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
291 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK))
294 if (!(pll->params->flags & TEGRA_PLL_HAS_LOCK_ENABLE))
297 val = pll_readl_misc(pll);
298 val |= BIT(pll->params->lock_enable_bit_idx);
299 pll_writel_misc(val, pll);
302 static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll)
306 void __iomem *lock_addr;
308 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) {
309 udelay(pll->params->lock_delay);
313 lock_addr = pll->clk_base;
314 if (pll->params->flags & TEGRA_PLL_LOCK_MISC)
315 lock_addr += pll->params->misc_reg;
317 lock_addr += pll->params->base_reg;
319 lock_mask = pll->params->lock_mask;
321 for (i = 0; i < pll->params->lock_delay; i++) {
322 val = readl_relaxed(lock_addr);
323 if ((val & lock_mask) == lock_mask) {
324 udelay(PLL_POST_LOCK_DELAY);
327 udelay(2); /* timeout = 2 * lock time */
330 pr_err("%s: Timed out waiting for pll %s lock\n", __func__,
331 clk_hw_get_name(&pll->hw));
336 int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll)
338 return clk_pll_wait_for_lock(pll);
341 static int clk_pll_is_enabled(struct clk_hw *hw)
343 struct tegra_clk_pll *pll = to_clk_pll(hw);
346 if (pll->params->flags & TEGRA_PLLM) {
347 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
348 if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)
349 return val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE ? 1 : 0;
352 val = pll_readl_base(pll);
354 return val & PLL_BASE_ENABLE ? 1 : 0;
357 static void _clk_pll_enable(struct clk_hw *hw)
359 struct tegra_clk_pll *pll = to_clk_pll(hw);
362 if (pll->params->iddq_reg) {
363 val = pll_readl(pll->params->iddq_reg, pll);
364 val &= ~BIT(pll->params->iddq_bit_idx);
365 pll_writel(val, pll->params->iddq_reg, pll);
369 if (pll->params->reset_reg) {
370 val = pll_readl(pll->params->reset_reg, pll);
371 val &= ~BIT(pll->params->reset_bit_idx);
372 pll_writel(val, pll->params->reset_reg, pll);
375 clk_pll_enable_lock(pll);
377 val = pll_readl_base(pll);
378 if (pll->params->flags & TEGRA_PLL_BYPASS)
379 val &= ~PLL_BASE_BYPASS;
380 val |= PLL_BASE_ENABLE;
381 pll_writel_base(val, pll);
383 if (pll->params->flags & TEGRA_PLLM) {
384 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
385 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
386 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
390 static void _clk_pll_disable(struct clk_hw *hw)
392 struct tegra_clk_pll *pll = to_clk_pll(hw);
395 val = pll_readl_base(pll);
396 if (pll->params->flags & TEGRA_PLL_BYPASS)
397 val &= ~PLL_BASE_BYPASS;
398 val &= ~PLL_BASE_ENABLE;
399 pll_writel_base(val, pll);
401 if (pll->params->flags & TEGRA_PLLM) {
402 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
403 val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
404 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
407 if (pll->params->reset_reg) {
408 val = pll_readl(pll->params->reset_reg, pll);
409 val |= BIT(pll->params->reset_bit_idx);
410 pll_writel(val, pll->params->reset_reg, pll);
413 if (pll->params->iddq_reg) {
414 val = pll_readl(pll->params->iddq_reg, pll);
415 val |= BIT(pll->params->iddq_bit_idx);
416 pll_writel(val, pll->params->iddq_reg, pll);
421 static void pll_clk_start_ss(struct tegra_clk_pll *pll)
423 if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
424 u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
426 val |= pll->params->ssc_ctrl_en_mask;
427 pll_writel(val, pll->params->ssc_ctrl_reg, pll);
431 static void pll_clk_stop_ss(struct tegra_clk_pll *pll)
433 if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
434 u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
436 val &= ~pll->params->ssc_ctrl_en_mask;
437 pll_writel(val, pll->params->ssc_ctrl_reg, pll);
441 static int clk_pll_enable(struct clk_hw *hw)
443 struct tegra_clk_pll *pll = to_clk_pll(hw);
444 unsigned long flags = 0;
448 spin_lock_irqsave(pll->lock, flags);
452 ret = clk_pll_wait_for_lock(pll);
454 pll_clk_start_ss(pll);
457 spin_unlock_irqrestore(pll->lock, flags);
462 static void clk_pll_disable(struct clk_hw *hw)
464 struct tegra_clk_pll *pll = to_clk_pll(hw);
465 unsigned long flags = 0;
468 spin_lock_irqsave(pll->lock, flags);
470 pll_clk_stop_ss(pll);
472 _clk_pll_disable(hw);
475 spin_unlock_irqrestore(pll->lock, flags);
478 static int _p_div_to_hw(struct clk_hw *hw, u8 p_div)
480 struct tegra_clk_pll *pll = to_clk_pll(hw);
481 const struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
484 while (p_tohw->pdiv) {
485 if (p_div <= p_tohw->pdiv)
486 return p_tohw->hw_val;
494 int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div)
496 return _p_div_to_hw(&pll->hw, p_div);
499 static int _hw_to_p_div(struct clk_hw *hw, u8 p_div_hw)
501 struct tegra_clk_pll *pll = to_clk_pll(hw);
502 const struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
505 while (p_tohw->pdiv) {
506 if (p_div_hw == p_tohw->hw_val)
513 return 1 << p_div_hw;
516 static int _get_table_rate(struct clk_hw *hw,
517 struct tegra_clk_pll_freq_table *cfg,
518 unsigned long rate, unsigned long parent_rate)
520 struct tegra_clk_pll *pll = to_clk_pll(hw);
521 struct tegra_clk_pll_freq_table *sel;
524 for (sel = pll->params->freq_table; sel->input_rate != 0; sel++)
525 if (sel->input_rate == parent_rate &&
526 sel->output_rate == rate)
529 if (sel->input_rate == 0)
532 if (pll->params->pdiv_tohw) {
533 p = _p_div_to_hw(hw, sel->p);
540 cfg->input_rate = sel->input_rate;
541 cfg->output_rate = sel->output_rate;
545 cfg->cpcon = sel->cpcon;
546 cfg->sdm_data = sel->sdm_data;
551 static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
552 unsigned long rate, unsigned long parent_rate)
554 struct tegra_clk_pll *pll = to_clk_pll(hw);
559 switch (parent_rate) {
562 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
565 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
569 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
574 * PLL_P_OUT1 rate is not listed in PLLA table
576 cfreq = parent_rate / (parent_rate / 1000000);
579 pr_err("%s Unexpected reference rate %lu\n",
580 __func__, parent_rate);
584 /* Raise VCO to guarantee 0.5% accuracy */
585 for (cfg->output_rate = rate; cfg->output_rate < 200 * cfreq;
586 cfg->output_rate <<= 1)
589 cfg->m = parent_rate / cfreq;
590 cfg->n = cfg->output_rate / cfreq;
591 cfg->cpcon = OUT_OF_TABLE_CPCON;
593 if (cfg->m > divm_max(pll) || cfg->n > divn_max(pll) ||
594 (1 << p_div) > divp_max(pll)
595 || cfg->output_rate > pll->params->vco_max) {
599 cfg->output_rate >>= p_div;
601 if (pll->params->pdiv_tohw) {
602 ret = _p_div_to_hw(hw, 1 << p_div);
614 * SDM (Sigma Delta Modulator) divisor is 16-bit 2's complement signed number
615 * within (-2^12 ... 2^12-1) range. Represented in PLL data structure as
616 * unsigned 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used
617 * to indicate that SDM is disabled.
619 * Effective ndiv value when SDM is enabled: ndiv + 1/2 + sdm_din/2^13
621 static void clk_pll_set_sdm_data(struct clk_hw *hw,
622 struct tegra_clk_pll_freq_table *cfg)
624 struct tegra_clk_pll *pll = to_clk_pll(hw);
628 if (!pll->params->sdm_din_reg)
632 val = pll_readl_sdm_din(pll) & (~sdm_din_mask(pll));
633 val |= sdin_data_to_din(cfg->sdm_data) & sdm_din_mask(pll);
634 pll_writel_sdm_din(val, pll);
637 val = pll_readl_sdm_ctrl(pll);
638 enabled = (val & sdm_en_mask(pll));
640 if (cfg->sdm_data == 0 && enabled)
641 val &= ~pll->params->sdm_ctrl_en_mask;
643 if (cfg->sdm_data != 0 && !enabled)
644 val |= pll->params->sdm_ctrl_en_mask;
646 pll_writel_sdm_ctrl(val, pll);
649 static void _update_pll_mnp(struct tegra_clk_pll *pll,
650 struct tegra_clk_pll_freq_table *cfg)
653 struct tegra_clk_pll_params *params = pll->params;
654 struct div_nmp *div_nmp = params->div_nmp;
656 if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
657 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
658 PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
659 val = pll_override_readl(params->pmc_divp_reg, pll);
660 val &= ~(divp_mask(pll) << div_nmp->override_divp_shift);
661 val |= cfg->p << div_nmp->override_divp_shift;
662 pll_override_writel(val, params->pmc_divp_reg, pll);
664 val = pll_override_readl(params->pmc_divnm_reg, pll);
665 val &= ~((divm_mask(pll) << div_nmp->override_divm_shift) |
666 (divn_mask(pll) << div_nmp->override_divn_shift));
667 val |= (cfg->m << div_nmp->override_divm_shift) |
668 (cfg->n << div_nmp->override_divn_shift);
669 pll_override_writel(val, params->pmc_divnm_reg, pll);
671 val = pll_readl_base(pll);
673 val &= ~(divm_mask_shifted(pll) | divn_mask_shifted(pll) |
674 divp_mask_shifted(pll));
676 val |= (cfg->m << divm_shift(pll)) |
677 (cfg->n << divn_shift(pll)) |
678 (cfg->p << divp_shift(pll));
680 pll_writel_base(val, pll);
682 clk_pll_set_sdm_data(&pll->hw, cfg);
686 static void _get_pll_mnp(struct tegra_clk_pll *pll,
687 struct tegra_clk_pll_freq_table *cfg)
690 struct tegra_clk_pll_params *params = pll->params;
691 struct div_nmp *div_nmp = params->div_nmp;
693 *cfg = (struct tegra_clk_pll_freq_table) { };
695 if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
696 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
697 PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
698 val = pll_override_readl(params->pmc_divp_reg, pll);
699 cfg->p = (val >> div_nmp->override_divp_shift) & divp_mask(pll);
701 val = pll_override_readl(params->pmc_divnm_reg, pll);
702 cfg->m = (val >> div_nmp->override_divm_shift) & divm_mask(pll);
703 cfg->n = (val >> div_nmp->override_divn_shift) & divn_mask(pll);
705 val = pll_readl_base(pll);
707 cfg->m = (val >> div_nmp->divm_shift) & divm_mask(pll);
708 cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll);
709 cfg->p = (val >> div_nmp->divp_shift) & divp_mask(pll);
711 if (pll->params->sdm_din_reg) {
712 if (sdm_en_mask(pll) & pll_readl_sdm_ctrl(pll)) {
713 val = pll_readl_sdm_din(pll);
714 val &= sdm_din_mask(pll);
715 cfg->sdm_data = sdin_din_to_data(val);
721 static void _update_pll_cpcon(struct tegra_clk_pll *pll,
722 struct tegra_clk_pll_freq_table *cfg,
727 val = pll_readl_misc(pll);
729 val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT);
730 val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT;
732 if (pll->params->flags & TEGRA_PLL_SET_LFCON) {
733 val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT);
734 if (cfg->n >= PLLDU_LFCON_SET_DIVN)
735 val |= 1 << PLL_MISC_LFCON_SHIFT;
736 } else if (pll->params->flags & TEGRA_PLL_SET_DCCON) {
737 val &= ~(1 << PLL_MISC_DCCON_SHIFT);
738 if (rate >= (pll->params->vco_max >> 1))
739 val |= 1 << PLL_MISC_DCCON_SHIFT;
742 pll_writel_misc(val, pll);
745 static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
748 struct tegra_clk_pll *pll = to_clk_pll(hw);
749 struct tegra_clk_pll_freq_table old_cfg;
752 state = clk_pll_is_enabled(hw);
754 _get_pll_mnp(pll, &old_cfg);
756 if (state && pll->params->defaults_set && pll->params->dyn_ramp &&
757 (cfg->m == old_cfg.m) && (cfg->p == old_cfg.p)) {
758 ret = pll->params->dyn_ramp(pll, cfg);
764 pll_clk_stop_ss(pll);
765 _clk_pll_disable(hw);
768 if (!pll->params->defaults_set && pll->params->set_defaults)
769 pll->params->set_defaults(pll);
771 _update_pll_mnp(pll, cfg);
773 if (pll->params->flags & TEGRA_PLL_HAS_CPCON)
774 _update_pll_cpcon(pll, cfg, rate);
778 ret = clk_pll_wait_for_lock(pll);
779 pll_clk_start_ss(pll);
785 static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
786 unsigned long parent_rate)
788 struct tegra_clk_pll *pll = to_clk_pll(hw);
789 struct tegra_clk_pll_freq_table cfg, old_cfg;
790 unsigned long flags = 0;
793 if (pll->params->flags & TEGRA_PLL_FIXED) {
794 if (rate != pll->params->fixed_rate) {
795 pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
796 __func__, clk_hw_get_name(hw),
797 pll->params->fixed_rate, rate);
803 if (_get_table_rate(hw, &cfg, rate, parent_rate) &&
804 pll->params->calc_rate(hw, &cfg, rate, parent_rate)) {
805 pr_err("%s: Failed to set %s rate %lu\n", __func__,
806 clk_hw_get_name(hw), rate);
811 spin_lock_irqsave(pll->lock, flags);
813 _get_pll_mnp(pll, &old_cfg);
814 if (pll->params->flags & TEGRA_PLL_VCO_OUT)
817 if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p ||
818 old_cfg.sdm_data != cfg.sdm_data)
819 ret = _program_pll(hw, &cfg, rate);
822 spin_unlock_irqrestore(pll->lock, flags);
827 static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
828 unsigned long *prate)
830 struct tegra_clk_pll *pll = to_clk_pll(hw);
831 struct tegra_clk_pll_freq_table cfg;
833 if (pll->params->flags & TEGRA_PLL_FIXED) {
834 /* PLLM/MB are used for memory; we do not change rate */
835 if (pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB))
836 return clk_hw_get_rate(hw);
837 return pll->params->fixed_rate;
840 if (_get_table_rate(hw, &cfg, rate, *prate) &&
841 pll->params->calc_rate(hw, &cfg, rate, *prate))
844 return cfg.output_rate;
847 static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
848 unsigned long parent_rate)
850 struct tegra_clk_pll *pll = to_clk_pll(hw);
851 struct tegra_clk_pll_freq_table cfg;
853 u64 rate = parent_rate;
856 val = pll_readl_base(pll);
858 if ((pll->params->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS))
861 if ((pll->params->flags & TEGRA_PLL_FIXED) &&
862 !(pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
863 !(val & PLL_BASE_OVERRIDE)) {
864 struct tegra_clk_pll_freq_table sel;
865 if (_get_table_rate(hw, &sel, pll->params->fixed_rate,
867 pr_err("Clock %s has unknown fixed frequency\n",
868 clk_hw_get_name(hw));
871 return pll->params->fixed_rate;
874 _get_pll_mnp(pll, &cfg);
876 if (pll->params->flags & TEGRA_PLL_VCO_OUT) {
879 pdiv = _hw_to_p_div(hw, cfg.p);
881 WARN(1, "Clock %s has invalid pdiv value : 0x%x\n",
882 clk_hw_get_name(hw), cfg.p);
887 if (pll->params->set_gain)
888 pll->params->set_gain(&cfg);
898 static int clk_plle_training(struct tegra_clk_pll *pll)
901 unsigned long timeout;
907 * PLLE is already disabled, and setup cleared;
908 * create falling edge on PLLE IDDQ input.
910 val = readl(pll->pmc + PMC_SATA_PWRGT);
911 val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
912 writel(val, pll->pmc + PMC_SATA_PWRGT);
914 val = readl(pll->pmc + PMC_SATA_PWRGT);
915 val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
916 writel(val, pll->pmc + PMC_SATA_PWRGT);
918 val = readl(pll->pmc + PMC_SATA_PWRGT);
919 val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
920 writel(val, pll->pmc + PMC_SATA_PWRGT);
922 val = pll_readl_misc(pll);
924 timeout = jiffies + msecs_to_jiffies(100);
926 val = pll_readl_misc(pll);
927 if (val & PLLE_MISC_READY)
929 if (time_after(jiffies, timeout)) {
930 pr_err("%s: timeout waiting for PLLE\n", __func__);
939 static int clk_plle_enable(struct clk_hw *hw)
941 struct tegra_clk_pll *pll = to_clk_pll(hw);
942 unsigned long input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
943 struct tegra_clk_pll_freq_table sel;
947 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
952 val = pll_readl_misc(pll);
953 val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK);
954 pll_writel_misc(val, pll);
956 val = pll_readl_misc(pll);
957 if (!(val & PLLE_MISC_READY)) {
958 err = clk_plle_training(pll);
963 if (pll->params->flags & TEGRA_PLLE_CONFIGURE) {
964 /* configure dividers */
965 val = pll_readl_base(pll);
966 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
967 divm_mask_shifted(pll));
968 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
969 val |= sel.m << divm_shift(pll);
970 val |= sel.n << divn_shift(pll);
971 val |= sel.p << divp_shift(pll);
972 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
973 pll_writel_base(val, pll);
976 val = pll_readl_misc(pll);
977 val |= PLLE_MISC_SETUP_VALUE;
978 val |= PLLE_MISC_LOCK_ENABLE;
979 pll_writel_misc(val, pll);
981 val = readl(pll->clk_base + PLLE_SS_CTRL);
982 val &= ~PLLE_SS_COEFFICIENTS_MASK;
983 val |= PLLE_SS_DISABLE;
984 writel(val, pll->clk_base + PLLE_SS_CTRL);
986 val = pll_readl_base(pll);
987 val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE);
988 pll_writel_base(val, pll);
990 clk_pll_wait_for_lock(pll);
995 static unsigned long clk_plle_recalc_rate(struct clk_hw *hw,
996 unsigned long parent_rate)
998 struct tegra_clk_pll *pll = to_clk_pll(hw);
999 u32 val = pll_readl_base(pll);
1000 u32 divn = 0, divm = 0, divp = 0;
1001 u64 rate = parent_rate;
1003 divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll));
1004 divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll));
1005 divm = (val >> pll->params->div_nmp->divm_shift) & (divm_mask(pll));
1013 const struct clk_ops tegra_clk_pll_ops = {
1014 .is_enabled = clk_pll_is_enabled,
1015 .enable = clk_pll_enable,
1016 .disable = clk_pll_disable,
1017 .recalc_rate = clk_pll_recalc_rate,
1018 .round_rate = clk_pll_round_rate,
1019 .set_rate = clk_pll_set_rate,
1022 const struct clk_ops tegra_clk_plle_ops = {
1023 .recalc_rate = clk_plle_recalc_rate,
1024 .is_enabled = clk_pll_is_enabled,
1025 .disable = clk_pll_disable,
1026 .enable = clk_plle_enable,
1030 * Structure defining the fields for USB UTMI clocks Parameters.
1032 struct utmi_clk_param {
1033 /* Oscillator Frequency in Hz */
1035 /* UTMIP PLL Enable Delay Count */
1036 u8 enable_delay_count;
1037 /* UTMIP PLL Stable count */
1039 /* UTMIP PLL Active delay count */
1040 u8 active_delay_count;
1041 /* UTMIP PLL Xtal frequency count */
1045 static const struct utmi_clk_param utmi_parameters[] = {
1047 .osc_frequency = 13000000, .enable_delay_count = 0x02,
1048 .stable_count = 0x33, .active_delay_count = 0x05,
1049 .xtal_freq_count = 0x7f
1051 .osc_frequency = 19200000, .enable_delay_count = 0x03,
1052 .stable_count = 0x4b, .active_delay_count = 0x06,
1053 .xtal_freq_count = 0xbb
1055 .osc_frequency = 12000000, .enable_delay_count = 0x02,
1056 .stable_count = 0x2f, .active_delay_count = 0x04,
1057 .xtal_freq_count = 0x76
1059 .osc_frequency = 26000000, .enable_delay_count = 0x04,
1060 .stable_count = 0x66, .active_delay_count = 0x09,
1061 .xtal_freq_count = 0xfe
1063 .osc_frequency = 16800000, .enable_delay_count = 0x03,
1064 .stable_count = 0x41, .active_delay_count = 0x0a,
1065 .xtal_freq_count = 0xa4
1067 .osc_frequency = 38400000, .enable_delay_count = 0x0,
1068 .stable_count = 0x0, .active_delay_count = 0x6,
1069 .xtal_freq_count = 0x80
1073 static int clk_pllu_enable(struct clk_hw *hw)
1075 struct tegra_clk_pll *pll = to_clk_pll(hw);
1076 struct clk_hw *pll_ref = clk_hw_get_parent(hw);
1077 struct clk_hw *osc = clk_hw_get_parent(pll_ref);
1078 const struct utmi_clk_param *params = NULL;
1079 unsigned long flags = 0, input_rate;
1085 pr_err("%s: failed to get OSC clock\n", __func__);
1089 input_rate = clk_hw_get_rate(osc);
1092 spin_lock_irqsave(pll->lock, flags);
1094 if (!clk_pll_is_enabled(hw))
1095 _clk_pll_enable(hw);
1097 ret = clk_pll_wait_for_lock(pll);
1101 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
1102 if (input_rate == utmi_parameters[i].osc_frequency) {
1103 params = &utmi_parameters[i];
1109 pr_err("%s: unexpected input rate %lu Hz\n", __func__,
1115 value = pll_readl_base(pll);
1116 value &= ~PLLU_BASE_OVERRIDE;
1117 pll_writel_base(value, pll);
1119 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2);
1120 /* Program UTMIP PLL stable and active counts */
1121 value &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1122 value |= UTMIP_PLL_CFG2_STABLE_COUNT(params->stable_count);
1123 value &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1124 value |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(params->active_delay_count);
1125 /* Remove power downs from UTMIP PLL control bits */
1126 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
1127 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
1128 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
1129 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2);
1131 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
1132 /* Program UTMIP PLL delay and oscillator frequency counts */
1133 value &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1134 value |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(params->enable_delay_count);
1135 value &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1136 value |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(params->xtal_freq_count);
1137 /* Remove power downs from UTMIP PLL control bits */
1138 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1139 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
1140 value &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
1141 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
1145 spin_unlock_irqrestore(pll->lock, flags);
1150 static const struct clk_ops tegra_clk_pllu_ops = {
1151 .is_enabled = clk_pll_is_enabled,
1152 .enable = clk_pllu_enable,
1153 .disable = clk_pll_disable,
1154 .recalc_rate = clk_pll_recalc_rate,
1155 .round_rate = clk_pll_round_rate,
1156 .set_rate = clk_pll_set_rate,
1159 static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params,
1160 unsigned long parent_rate)
1162 u16 mdiv = parent_rate / pll_params->cf_min;
1164 if (pll_params->flags & TEGRA_MDIV_NEW)
1165 return (!pll_params->mdiv_default ? mdiv :
1166 min(mdiv, pll_params->mdiv_default));
1168 if (pll_params->mdiv_default)
1169 return pll_params->mdiv_default;
1171 if (parent_rate > pll_params->cf_max)
1177 static int _calc_dynamic_ramp_rate(struct clk_hw *hw,
1178 struct tegra_clk_pll_freq_table *cfg,
1179 unsigned long rate, unsigned long parent_rate)
1181 struct tegra_clk_pll *pll = to_clk_pll(hw);
1188 p = DIV_ROUND_UP(pll->params->vco_min, rate);
1189 cfg->m = _pll_fixed_mdiv(pll->params, parent_rate);
1190 cfg->output_rate = rate * p;
1191 cfg->n = cfg->output_rate * cfg->m / parent_rate;
1192 cfg->input_rate = parent_rate;
1194 p_div = _p_div_to_hw(hw, p);
1200 if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max)
1206 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
1207 defined(CONFIG_ARCH_TEGRA_124_SOC) || \
1208 defined(CONFIG_ARCH_TEGRA_132_SOC) || \
1209 defined(CONFIG_ARCH_TEGRA_210_SOC)
1211 u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate)
1213 struct tegra_clk_pll *pll = to_clk_pll(hw);
1215 return (u16)_pll_fixed_mdiv(pll->params, input_rate);
1218 static unsigned long _clip_vco_min(unsigned long vco_min,
1219 unsigned long parent_rate)
1221 return DIV_ROUND_UP(vco_min, parent_rate) * parent_rate;
1224 static int _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params,
1225 void __iomem *clk_base,
1226 unsigned long parent_rate)
1231 switch (parent_rate) {
1247 pr_err("%s: Unexpected reference rate %lu\n",
1248 __func__, parent_rate);
1253 val = step_a << pll_params->stepa_shift;
1254 val |= step_b << pll_params->stepb_shift;
1255 writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg);
1260 static int _pll_ramp_calc_pll(struct clk_hw *hw,
1261 struct tegra_clk_pll_freq_table *cfg,
1262 unsigned long rate, unsigned long parent_rate)
1264 struct tegra_clk_pll *pll = to_clk_pll(hw);
1267 err = _get_table_rate(hw, cfg, rate, parent_rate);
1269 err = _calc_dynamic_ramp_rate(hw, cfg, rate, parent_rate);
1271 if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) {
1278 if (cfg->p > pll->params->max_p)
1285 static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate,
1286 unsigned long parent_rate)
1288 struct tegra_clk_pll *pll = to_clk_pll(hw);
1289 struct tegra_clk_pll_freq_table cfg, old_cfg;
1290 unsigned long flags = 0;
1293 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
1298 spin_lock_irqsave(pll->lock, flags);
1300 _get_pll_mnp(pll, &old_cfg);
1301 if (pll->params->flags & TEGRA_PLL_VCO_OUT)
1304 if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p)
1305 ret = _program_pll(hw, &cfg, rate);
1308 spin_unlock_irqrestore(pll->lock, flags);
1313 static long clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate,
1314 unsigned long *prate)
1316 struct tegra_clk_pll *pll = to_clk_pll(hw);
1317 struct tegra_clk_pll_freq_table cfg;
1319 u64 output_rate = *prate;
1321 ret = _pll_ramp_calc_pll(hw, &cfg, rate, *prate);
1325 p_div = _hw_to_p_div(hw, cfg.p);
1329 if (pll->params->set_gain)
1330 pll->params->set_gain(&cfg);
1332 output_rate *= cfg.n;
1333 do_div(output_rate, cfg.m * p_div);
1338 static void _pllcx_strobe(struct tegra_clk_pll *pll)
1342 val = pll_readl_misc(pll);
1343 val |= PLLCX_MISC_STROBE;
1344 pll_writel_misc(val, pll);
1347 val &= ~PLLCX_MISC_STROBE;
1348 pll_writel_misc(val, pll);
1351 static int clk_pllc_enable(struct clk_hw *hw)
1353 struct tegra_clk_pll *pll = to_clk_pll(hw);
1356 unsigned long flags = 0;
1359 spin_lock_irqsave(pll->lock, flags);
1361 _clk_pll_enable(hw);
1364 val = pll_readl_misc(pll);
1365 val &= ~PLLCX_MISC_RESET;
1366 pll_writel_misc(val, pll);
1371 ret = clk_pll_wait_for_lock(pll);
1374 spin_unlock_irqrestore(pll->lock, flags);
1379 static void _clk_pllc_disable(struct clk_hw *hw)
1381 struct tegra_clk_pll *pll = to_clk_pll(hw);
1384 _clk_pll_disable(hw);
1386 val = pll_readl_misc(pll);
1387 val |= PLLCX_MISC_RESET;
1388 pll_writel_misc(val, pll);
1392 static void clk_pllc_disable(struct clk_hw *hw)
1394 struct tegra_clk_pll *pll = to_clk_pll(hw);
1395 unsigned long flags = 0;
1398 spin_lock_irqsave(pll->lock, flags);
1400 _clk_pllc_disable(hw);
1403 spin_unlock_irqrestore(pll->lock, flags);
1406 static int _pllcx_update_dynamic_coef(struct tegra_clk_pll *pll,
1407 unsigned long input_rate, u32 n)
1409 u32 val, n_threshold;
1411 switch (input_rate) {
1426 pr_err("%s: Unexpected reference rate %lu\n",
1427 __func__, input_rate);
1431 val = pll_readl_misc(pll);
1432 val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK);
1433 val |= n <= n_threshold ?
1434 PLLCX_MISC_DIV_LOW_RANGE : PLLCX_MISC_DIV_HIGH_RANGE;
1435 pll_writel_misc(val, pll);
1440 static int clk_pllc_set_rate(struct clk_hw *hw, unsigned long rate,
1441 unsigned long parent_rate)
1443 struct tegra_clk_pll_freq_table cfg, old_cfg;
1444 struct tegra_clk_pll *pll = to_clk_pll(hw);
1445 unsigned long flags = 0;
1449 spin_lock_irqsave(pll->lock, flags);
1451 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
1455 _get_pll_mnp(pll, &old_cfg);
1457 if (cfg.m != old_cfg.m) {
1462 if (old_cfg.n == cfg.n && old_cfg.p == cfg.p)
1465 state = clk_pll_is_enabled(hw);
1467 _clk_pllc_disable(hw);
1469 ret = _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
1473 _update_pll_mnp(pll, &cfg);
1476 ret = clk_pllc_enable(hw);
1480 spin_unlock_irqrestore(pll->lock, flags);
1485 static long _pllre_calc_rate(struct tegra_clk_pll *pll,
1486 struct tegra_clk_pll_freq_table *cfg,
1487 unsigned long rate, unsigned long parent_rate)
1490 u64 output_rate = parent_rate;
1492 m = _pll_fixed_mdiv(pll->params, parent_rate);
1493 n = rate * m / parent_rate;
1496 do_div(output_rate, m);
1506 static int clk_pllre_set_rate(struct clk_hw *hw, unsigned long rate,
1507 unsigned long parent_rate)
1509 struct tegra_clk_pll_freq_table cfg, old_cfg;
1510 struct tegra_clk_pll *pll = to_clk_pll(hw);
1511 unsigned long flags = 0;
1515 spin_lock_irqsave(pll->lock, flags);
1517 _pllre_calc_rate(pll, &cfg, rate, parent_rate);
1518 _get_pll_mnp(pll, &old_cfg);
1521 if (cfg.m != old_cfg.m || cfg.n != old_cfg.n) {
1522 state = clk_pll_is_enabled(hw);
1524 _clk_pll_disable(hw);
1526 _update_pll_mnp(pll, &cfg);
1529 _clk_pll_enable(hw);
1530 ret = clk_pll_wait_for_lock(pll);
1535 spin_unlock_irqrestore(pll->lock, flags);
1540 static unsigned long clk_pllre_recalc_rate(struct clk_hw *hw,
1541 unsigned long parent_rate)
1543 struct tegra_clk_pll_freq_table cfg;
1544 struct tegra_clk_pll *pll = to_clk_pll(hw);
1545 u64 rate = parent_rate;
1547 _get_pll_mnp(pll, &cfg);
1550 do_div(rate, cfg.m);
1555 static long clk_pllre_round_rate(struct clk_hw *hw, unsigned long rate,
1556 unsigned long *prate)
1558 struct tegra_clk_pll *pll = to_clk_pll(hw);
1560 return _pllre_calc_rate(pll, NULL, rate, *prate);
1563 static int clk_plle_tegra114_enable(struct clk_hw *hw)
1565 struct tegra_clk_pll *pll = to_clk_pll(hw);
1566 struct tegra_clk_pll_freq_table sel;
1569 unsigned long flags = 0;
1570 unsigned long input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
1572 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
1576 spin_lock_irqsave(pll->lock, flags);
1578 val = pll_readl_base(pll);
1579 val &= ~BIT(29); /* Disable lock override */
1580 pll_writel_base(val, pll);
1582 val = pll_readl(pll->params->aux_reg, pll);
1583 val |= PLLE_AUX_ENABLE_SWCTL;
1584 val &= ~PLLE_AUX_SEQ_ENABLE;
1585 pll_writel(val, pll->params->aux_reg, pll);
1588 val = pll_readl_misc(pll);
1589 val |= PLLE_MISC_LOCK_ENABLE;
1590 val |= PLLE_MISC_IDDQ_SW_CTRL;
1591 val &= ~PLLE_MISC_IDDQ_SW_VALUE;
1592 val |= PLLE_MISC_PLLE_PTS;
1593 val &= ~(PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK);
1594 pll_writel_misc(val, pll);
1597 val = pll_readl(PLLE_SS_CTRL, pll);
1598 val |= PLLE_SS_DISABLE;
1599 pll_writel(val, PLLE_SS_CTRL, pll);
1601 val = pll_readl_base(pll);
1602 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
1603 divm_mask_shifted(pll));
1604 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
1605 val |= sel.m << divm_shift(pll);
1606 val |= sel.n << divn_shift(pll);
1607 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
1608 pll_writel_base(val, pll);
1611 _clk_pll_enable(hw);
1612 ret = clk_pll_wait_for_lock(pll);
1617 val = pll_readl(PLLE_SS_CTRL, pll);
1618 val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
1619 val &= ~PLLE_SS_COEFFICIENTS_MASK;
1620 val |= PLLE_SS_COEFFICIENTS_VAL_TEGRA114;
1621 pll_writel(val, PLLE_SS_CTRL, pll);
1622 val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
1623 pll_writel(val, PLLE_SS_CTRL, pll);
1625 val &= ~PLLE_SS_CNTL_INTERP_RESET;
1626 pll_writel(val, PLLE_SS_CTRL, pll);
1629 /* Enable hw control of xusb brick pll */
1630 val = pll_readl_misc(pll);
1631 val &= ~PLLE_MISC_IDDQ_SW_CTRL;
1632 pll_writel_misc(val, pll);
1634 val = pll_readl(pll->params->aux_reg, pll);
1635 val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SEQ_START_STATE);
1636 val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
1637 pll_writel(val, pll->params->aux_reg, pll);
1639 val |= PLLE_AUX_SEQ_ENABLE;
1640 pll_writel(val, pll->params->aux_reg, pll);
1642 val = pll_readl(XUSBIO_PLL_CFG0, pll);
1643 val |= (XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET |
1644 XUSBIO_PLL_CFG0_SEQ_START_STATE);
1645 val &= ~(XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL |
1646 XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL);
1647 pll_writel(val, XUSBIO_PLL_CFG0, pll);
1649 val |= XUSBIO_PLL_CFG0_SEQ_ENABLE;
1650 pll_writel(val, XUSBIO_PLL_CFG0, pll);
1652 /* Enable hw control of SATA pll */
1653 val = pll_readl(SATA_PLL_CFG0, pll);
1654 val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL;
1655 val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET;
1656 val |= SATA_PLL_CFG0_SEQ_START_STATE;
1657 pll_writel(val, SATA_PLL_CFG0, pll);
1661 val = pll_readl(SATA_PLL_CFG0, pll);
1662 val |= SATA_PLL_CFG0_SEQ_ENABLE;
1663 pll_writel(val, SATA_PLL_CFG0, pll);
1667 spin_unlock_irqrestore(pll->lock, flags);
1672 static void clk_plle_tegra114_disable(struct clk_hw *hw)
1674 struct tegra_clk_pll *pll = to_clk_pll(hw);
1675 unsigned long flags = 0;
1679 spin_lock_irqsave(pll->lock, flags);
1681 _clk_pll_disable(hw);
1683 val = pll_readl_misc(pll);
1684 val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
1685 pll_writel_misc(val, pll);
1689 spin_unlock_irqrestore(pll->lock, flags);
1692 static int clk_pllu_tegra114_enable(struct clk_hw *hw)
1694 struct tegra_clk_pll *pll = to_clk_pll(hw);
1695 const struct utmi_clk_param *params = NULL;
1696 struct clk *osc = __clk_lookup("osc");
1697 unsigned long flags = 0, input_rate;
1703 pr_err("%s: failed to get OSC clock\n", __func__);
1707 input_rate = clk_hw_get_rate(__clk_get_hw(osc));
1710 spin_lock_irqsave(pll->lock, flags);
1712 if (!clk_pll_is_enabled(hw))
1713 _clk_pll_enable(hw);
1715 ret = clk_pll_wait_for_lock(pll);
1719 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
1720 if (input_rate == utmi_parameters[i].osc_frequency) {
1721 params = &utmi_parameters[i];
1727 pr_err("%s: unexpected input rate %lu Hz\n", __func__,
1733 value = pll_readl_base(pll);
1734 value &= ~PLLU_BASE_OVERRIDE;
1735 pll_writel_base(value, pll);
1737 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2);
1738 /* Program UTMIP PLL stable and active counts */
1739 value &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1740 value |= UTMIP_PLL_CFG2_STABLE_COUNT(params->stable_count);
1741 value &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1742 value |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(params->active_delay_count);
1743 /* Remove power downs from UTMIP PLL control bits */
1744 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
1745 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
1746 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
1747 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2);
1749 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
1750 /* Program UTMIP PLL delay and oscillator frequency counts */
1751 value &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1752 value |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(params->enable_delay_count);
1753 value &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1754 value |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(params->xtal_freq_count);
1755 /* Remove power downs from UTMIP PLL control bits */
1756 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1757 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
1758 value &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP;
1759 value &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
1760 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
1762 /* Setup HW control of UTMIPLL */
1763 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1764 value |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
1765 value &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
1766 value |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE;
1767 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1769 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
1770 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
1771 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1772 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
1777 * Setup SW override of UTMIPLL assuming USB2.0 ports are assigned
1780 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1781 value |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;
1782 value &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
1783 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1787 /* Enable HW control of UTMIPLL */
1788 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1789 value |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
1790 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1794 spin_unlock_irqrestore(pll->lock, flags);
1800 static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base,
1801 void __iomem *pmc, struct tegra_clk_pll_params *pll_params,
1804 struct tegra_clk_pll *pll;
1806 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
1808 return ERR_PTR(-ENOMEM);
1810 pll->clk_base = clk_base;
1813 pll->params = pll_params;
1816 if (!pll_params->div_nmp)
1817 pll_params->div_nmp = &default_nmp;
1822 static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll,
1823 const char *name, const char *parent_name, unsigned long flags,
1824 const struct clk_ops *ops)
1826 struct clk_init_data init;
1831 init.parent_names = (parent_name ? &parent_name : NULL);
1832 init.num_parents = (parent_name ? 1 : 0);
1834 /* Default to _calc_rate if unspecified */
1835 if (!pll->params->calc_rate) {
1836 if (pll->params->flags & TEGRA_PLLM)
1837 pll->params->calc_rate = _calc_dynamic_ramp_rate;
1839 pll->params->calc_rate = _calc_rate;
1842 if (pll->params->set_defaults)
1843 pll->params->set_defaults(pll);
1845 /* Data in .init is copied by clk_register(), so stack variable OK */
1846 pll->hw.init = &init;
1848 return clk_register(NULL, &pll->hw);
1851 struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
1852 void __iomem *clk_base, void __iomem *pmc,
1853 unsigned long flags, struct tegra_clk_pll_params *pll_params,
1856 struct tegra_clk_pll *pll;
1859 pll_params->flags |= TEGRA_PLL_BYPASS;
1861 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1863 return ERR_CAST(pll);
1865 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1866 &tegra_clk_pll_ops);
1873 static struct div_nmp pll_e_nmp = {
1874 .divn_shift = PLLE_BASE_DIVN_SHIFT,
1875 .divn_width = PLLE_BASE_DIVN_WIDTH,
1876 .divm_shift = PLLE_BASE_DIVM_SHIFT,
1877 .divm_width = PLLE_BASE_DIVM_WIDTH,
1878 .divp_shift = PLLE_BASE_DIVP_SHIFT,
1879 .divp_width = PLLE_BASE_DIVP_WIDTH,
1882 struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
1883 void __iomem *clk_base, void __iomem *pmc,
1884 unsigned long flags, struct tegra_clk_pll_params *pll_params,
1887 struct tegra_clk_pll *pll;
1890 pll_params->flags |= TEGRA_PLL_BYPASS;
1892 if (!pll_params->div_nmp)
1893 pll_params->div_nmp = &pll_e_nmp;
1895 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1897 return ERR_CAST(pll);
1899 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1900 &tegra_clk_plle_ops);
1907 struct clk *tegra_clk_register_pllu(const char *name, const char *parent_name,
1908 void __iomem *clk_base, unsigned long flags,
1909 struct tegra_clk_pll_params *pll_params, spinlock_t *lock)
1911 struct tegra_clk_pll *pll;
1914 pll_params->flags |= TEGRA_PLLU;
1916 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
1918 return ERR_CAST(pll);
1920 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1921 &tegra_clk_pllu_ops);
1928 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
1929 defined(CONFIG_ARCH_TEGRA_124_SOC) || \
1930 defined(CONFIG_ARCH_TEGRA_132_SOC) || \
1931 defined(CONFIG_ARCH_TEGRA_210_SOC)
1932 static const struct clk_ops tegra_clk_pllxc_ops = {
1933 .is_enabled = clk_pll_is_enabled,
1934 .enable = clk_pll_enable,
1935 .disable = clk_pll_disable,
1936 .recalc_rate = clk_pll_recalc_rate,
1937 .round_rate = clk_pll_ramp_round_rate,
1938 .set_rate = clk_pllxc_set_rate,
1941 static const struct clk_ops tegra_clk_pllc_ops = {
1942 .is_enabled = clk_pll_is_enabled,
1943 .enable = clk_pllc_enable,
1944 .disable = clk_pllc_disable,
1945 .recalc_rate = clk_pll_recalc_rate,
1946 .round_rate = clk_pll_ramp_round_rate,
1947 .set_rate = clk_pllc_set_rate,
1950 static const struct clk_ops tegra_clk_pllre_ops = {
1951 .is_enabled = clk_pll_is_enabled,
1952 .enable = clk_pll_enable,
1953 .disable = clk_pll_disable,
1954 .recalc_rate = clk_pllre_recalc_rate,
1955 .round_rate = clk_pllre_round_rate,
1956 .set_rate = clk_pllre_set_rate,
1959 static const struct clk_ops tegra_clk_plle_tegra114_ops = {
1960 .is_enabled = clk_pll_is_enabled,
1961 .enable = clk_plle_tegra114_enable,
1962 .disable = clk_plle_tegra114_disable,
1963 .recalc_rate = clk_pll_recalc_rate,
1966 static const struct clk_ops tegra_clk_pllu_tegra114_ops = {
1967 .is_enabled = clk_pll_is_enabled,
1968 .enable = clk_pllu_tegra114_enable,
1969 .disable = clk_pll_disable,
1970 .recalc_rate = clk_pll_recalc_rate,
1973 struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
1974 void __iomem *clk_base, void __iomem *pmc,
1975 unsigned long flags,
1976 struct tegra_clk_pll_params *pll_params,
1979 struct tegra_clk_pll *pll;
1980 struct clk *clk, *parent;
1981 unsigned long parent_rate;
1984 parent = __clk_lookup(parent_name);
1986 WARN(1, "parent clk %s of %s must be registered first\n",
1988 return ERR_PTR(-EINVAL);
1991 if (!pll_params->pdiv_tohw)
1992 return ERR_PTR(-EINVAL);
1994 parent_rate = clk_get_rate(parent);
1996 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1998 if (pll_params->adjust_vco)
1999 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2003 * If the pll has a set_defaults callback, it will take care of
2004 * configuring dynamic ramping and setting IDDQ in that path.
2006 if (!pll_params->set_defaults) {
2009 err = _setup_dynamic_ramp(pll_params, clk_base, parent_rate);
2011 return ERR_PTR(err);
2013 val = readl_relaxed(clk_base + pll_params->base_reg);
2014 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
2016 if (val & PLL_BASE_ENABLE)
2017 WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx));
2019 val_iddq |= BIT(pll_params->iddq_bit_idx);
2020 writel_relaxed(val_iddq,
2021 clk_base + pll_params->iddq_reg);
2025 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2027 return ERR_CAST(pll);
2029 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2030 &tegra_clk_pllxc_ops);
2037 struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
2038 void __iomem *clk_base, void __iomem *pmc,
2039 unsigned long flags,
2040 struct tegra_clk_pll_params *pll_params,
2041 spinlock_t *lock, unsigned long parent_rate)
2044 struct tegra_clk_pll *pll;
2047 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2049 if (pll_params->adjust_vco)
2050 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2053 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2055 return ERR_CAST(pll);
2057 /* program minimum rate by default */
2059 val = pll_readl_base(pll);
2060 if (val & PLL_BASE_ENABLE)
2061 WARN_ON(readl_relaxed(clk_base + pll_params->iddq_reg) &
2062 BIT(pll_params->iddq_bit_idx));
2066 m = _pll_fixed_mdiv(pll_params, parent_rate);
2067 val = m << divm_shift(pll);
2068 val |= (pll_params->vco_min / parent_rate) << divn_shift(pll);
2069 pll_writel_base(val, pll);
2072 /* disable lock override */
2074 val = pll_readl_misc(pll);
2076 pll_writel_misc(val, pll);
2078 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2079 &tegra_clk_pllre_ops);
2086 struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
2087 void __iomem *clk_base, void __iomem *pmc,
2088 unsigned long flags,
2089 struct tegra_clk_pll_params *pll_params,
2092 struct tegra_clk_pll *pll;
2093 struct clk *clk, *parent;
2094 unsigned long parent_rate;
2096 if (!pll_params->pdiv_tohw)
2097 return ERR_PTR(-EINVAL);
2099 parent = __clk_lookup(parent_name);
2101 WARN(1, "parent clk %s of %s must be registered first\n",
2103 return ERR_PTR(-EINVAL);
2106 parent_rate = clk_get_rate(parent);
2108 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2110 if (pll_params->adjust_vco)
2111 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2114 pll_params->flags |= TEGRA_PLL_BYPASS;
2115 pll_params->flags |= TEGRA_PLLM;
2116 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2118 return ERR_CAST(pll);
2120 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2121 &tegra_clk_pll_ops);
2128 struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
2129 void __iomem *clk_base, void __iomem *pmc,
2130 unsigned long flags,
2131 struct tegra_clk_pll_params *pll_params,
2134 struct clk *parent, *clk;
2135 const struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
2136 struct tegra_clk_pll *pll;
2137 struct tegra_clk_pll_freq_table cfg;
2138 unsigned long parent_rate;
2141 return ERR_PTR(-EINVAL);
2143 parent = __clk_lookup(parent_name);
2145 WARN(1, "parent clk %s of %s must be registered first\n",
2147 return ERR_PTR(-EINVAL);
2150 parent_rate = clk_get_rate(parent);
2152 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2154 pll_params->flags |= TEGRA_PLL_BYPASS;
2155 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2157 return ERR_CAST(pll);
2160 * Most of PLLC register fields are shadowed, and can not be read
2161 * directly from PLL h/w. Hence, actual PLLC boot state is unknown.
2162 * Initialize PLL to default state: disabled, reset; shadow registers
2163 * loaded with default parameters; dividers are preset for half of
2164 * minimum VCO rate (the latter assured that shadowed divider settings
2165 * are within supported range).
2168 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
2169 cfg.n = cfg.m * pll_params->vco_min / parent_rate;
2171 while (p_tohw->pdiv) {
2172 if (p_tohw->pdiv == 2) {
2173 cfg.p = p_tohw->hw_val;
2179 if (!p_tohw->pdiv) {
2181 return ERR_PTR(-EINVAL);
2184 pll_writel_base(0, pll);
2185 _update_pll_mnp(pll, &cfg);
2187 pll_writel_misc(PLLCX_MISC_DEFAULT, pll);
2188 pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll);
2189 pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll);
2190 pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll);
2192 _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
2194 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2195 &tegra_clk_pllc_ops);
2202 struct clk *tegra_clk_register_plle_tegra114(const char *name,
2203 const char *parent_name,
2204 void __iomem *clk_base, unsigned long flags,
2205 struct tegra_clk_pll_params *pll_params,
2208 struct tegra_clk_pll *pll;
2212 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2214 return ERR_CAST(pll);
2216 /* ensure parent is set to pll_re_vco */
2218 val = pll_readl_base(pll);
2219 val_aux = pll_readl(pll_params->aux_reg, pll);
2221 if (val & PLL_BASE_ENABLE) {
2222 if ((val_aux & PLLE_AUX_PLLRE_SEL) ||
2223 (val_aux & PLLE_AUX_PLLP_SEL))
2224 WARN(1, "pll_e enabled with unsupported parent %s\n",
2225 (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" :
2228 val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
2229 pll_writel(val_aux, pll_params->aux_reg, pll);
2232 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2233 &tegra_clk_plle_tegra114_ops);
2241 tegra_clk_register_pllu_tegra114(const char *name, const char *parent_name,
2242 void __iomem *clk_base, unsigned long flags,
2243 struct tegra_clk_pll_params *pll_params,
2246 struct tegra_clk_pll *pll;
2249 pll_params->flags |= TEGRA_PLLU;
2251 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2253 return ERR_CAST(pll);
2255 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2256 &tegra_clk_pllu_tegra114_ops);
2264 #if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC) || defined(CONFIG_ARCH_TEGRA_210_SOC)
2265 static const struct clk_ops tegra_clk_pllss_ops = {
2266 .is_enabled = clk_pll_is_enabled,
2267 .enable = clk_pll_enable,
2268 .disable = clk_pll_disable,
2269 .recalc_rate = clk_pll_recalc_rate,
2270 .round_rate = clk_pll_ramp_round_rate,
2271 .set_rate = clk_pllxc_set_rate,
2274 struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
2275 void __iomem *clk_base, unsigned long flags,
2276 struct tegra_clk_pll_params *pll_params,
2279 struct tegra_clk_pll *pll;
2280 struct clk *clk, *parent;
2281 struct tegra_clk_pll_freq_table cfg;
2282 unsigned long parent_rate;
2286 if (!pll_params->div_nmp)
2287 return ERR_PTR(-EINVAL);
2289 parent = __clk_lookup(parent_name);
2291 WARN(1, "parent clk %s of %s must be registered first\n",
2293 return ERR_PTR(-EINVAL);
2296 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2298 return ERR_CAST(pll);
2300 val = pll_readl_base(pll);
2301 val &= ~PLLSS_REF_SRC_SEL_MASK;
2302 pll_writel_base(val, pll);
2304 parent_rate = clk_get_rate(parent);
2306 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2308 /* initialize PLL to minimum rate */
2310 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
2311 cfg.n = cfg.m * pll_params->vco_min / parent_rate;
2313 for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++)
2317 return ERR_PTR(-EINVAL);
2320 cfg.p = pll_params->pdiv_tohw[i-1].hw_val;
2322 _update_pll_mnp(pll, &cfg);
2324 pll_writel_misc(PLLSS_MISC_DEFAULT, pll);
2325 pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll);
2326 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll);
2327 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll);
2329 val = pll_readl_base(pll);
2330 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
2331 if (val & PLL_BASE_ENABLE) {
2332 if (val_iddq & BIT(pll_params->iddq_bit_idx)) {
2333 WARN(1, "%s is on but IDDQ set\n", name);
2335 return ERR_PTR(-EINVAL);
2338 val_iddq |= BIT(pll_params->iddq_bit_idx);
2339 writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg);
2342 val &= ~PLLSS_LOCK_OVERRIDE;
2343 pll_writel_base(val, pll);
2345 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2346 &tegra_clk_pllss_ops);
2355 #if defined(CONFIG_ARCH_TEGRA_210_SOC)
2356 struct clk *tegra_clk_register_pllre_tegra210(const char *name,
2357 const char *parent_name, void __iomem *clk_base,
2358 void __iomem *pmc, unsigned long flags,
2359 struct tegra_clk_pll_params *pll_params,
2360 spinlock_t *lock, unsigned long parent_rate)
2362 struct tegra_clk_pll *pll;
2365 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2367 if (pll_params->adjust_vco)
2368 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2371 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2373 return ERR_CAST(pll);
2375 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2376 &tegra_clk_pll_ops);
2383 static int clk_plle_tegra210_enable(struct clk_hw *hw)
2385 struct tegra_clk_pll *pll = to_clk_pll(hw);
2386 struct tegra_clk_pll_freq_table sel;
2389 unsigned long flags = 0;
2390 unsigned long input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
2392 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
2396 spin_lock_irqsave(pll->lock, flags);
2398 val = pll_readl(pll->params->aux_reg, pll);
2399 if (val & PLLE_AUX_SEQ_ENABLE)
2402 val = pll_readl_base(pll);
2403 val &= ~BIT(30); /* Disable lock override */
2404 pll_writel_base(val, pll);
2406 val = pll_readl_misc(pll);
2407 val |= PLLE_MISC_LOCK_ENABLE;
2408 val |= PLLE_MISC_IDDQ_SW_CTRL;
2409 val &= ~PLLE_MISC_IDDQ_SW_VALUE;
2410 val |= PLLE_MISC_PLLE_PTS;
2411 val &= ~(PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK);
2412 pll_writel_misc(val, pll);
2415 val = pll_readl(PLLE_SS_CTRL, pll);
2416 val |= PLLE_SS_DISABLE;
2417 pll_writel(val, PLLE_SS_CTRL, pll);
2419 val = pll_readl_base(pll);
2420 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
2421 divm_mask_shifted(pll));
2422 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
2423 val |= sel.m << divm_shift(pll);
2424 val |= sel.n << divn_shift(pll);
2425 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
2426 pll_writel_base(val, pll);
2429 val = pll_readl_base(pll);
2430 val |= PLLE_BASE_ENABLE;
2431 pll_writel_base(val, pll);
2433 ret = clk_pll_wait_for_lock(pll);
2438 val = pll_readl(PLLE_SS_CTRL, pll);
2439 val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
2440 val &= ~PLLE_SS_COEFFICIENTS_MASK;
2441 val |= PLLE_SS_COEFFICIENTS_VAL_TEGRA210;
2442 pll_writel(val, PLLE_SS_CTRL, pll);
2443 val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
2444 pll_writel(val, PLLE_SS_CTRL, pll);
2446 val &= ~PLLE_SS_CNTL_INTERP_RESET;
2447 pll_writel(val, PLLE_SS_CTRL, pll);
2450 val = pll_readl_misc(pll);
2451 val &= ~PLLE_MISC_IDDQ_SW_CTRL;
2452 pll_writel_misc(val, pll);
2454 val = pll_readl(pll->params->aux_reg, pll);
2455 val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SS_SEQ_INCLUDE);
2456 val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
2457 pll_writel(val, pll->params->aux_reg, pll);
2459 val |= PLLE_AUX_SEQ_ENABLE;
2460 pll_writel(val, pll->params->aux_reg, pll);
2464 spin_unlock_irqrestore(pll->lock, flags);
2469 static void clk_plle_tegra210_disable(struct clk_hw *hw)
2471 struct tegra_clk_pll *pll = to_clk_pll(hw);
2472 unsigned long flags = 0;
2476 spin_lock_irqsave(pll->lock, flags);
2478 /* If PLLE HW sequencer is enabled, SW should not disable PLLE */
2479 val = pll_readl(pll->params->aux_reg, pll);
2480 if (val & PLLE_AUX_SEQ_ENABLE)
2483 val = pll_readl_base(pll);
2484 val &= ~PLLE_BASE_ENABLE;
2485 pll_writel_base(val, pll);
2487 val = pll_readl(pll->params->aux_reg, pll);
2488 val |= PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL;
2489 pll_writel(val, pll->params->aux_reg, pll);
2491 val = pll_readl_misc(pll);
2492 val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
2493 pll_writel_misc(val, pll);
2498 spin_unlock_irqrestore(pll->lock, flags);
2501 static int clk_plle_tegra210_is_enabled(struct clk_hw *hw)
2503 struct tegra_clk_pll *pll = to_clk_pll(hw);
2506 val = pll_readl_base(pll);
2508 return val & PLLE_BASE_ENABLE ? 1 : 0;
2511 static const struct clk_ops tegra_clk_plle_tegra210_ops = {
2512 .is_enabled = clk_plle_tegra210_is_enabled,
2513 .enable = clk_plle_tegra210_enable,
2514 .disable = clk_plle_tegra210_disable,
2515 .recalc_rate = clk_pll_recalc_rate,
2518 struct clk *tegra_clk_register_plle_tegra210(const char *name,
2519 const char *parent_name,
2520 void __iomem *clk_base, unsigned long flags,
2521 struct tegra_clk_pll_params *pll_params,
2524 struct tegra_clk_pll *pll;
2528 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2530 return ERR_CAST(pll);
2532 /* ensure parent is set to pll_re_vco */
2534 val = pll_readl_base(pll);
2535 val_aux = pll_readl(pll_params->aux_reg, pll);
2537 if (val & PLLE_BASE_ENABLE) {
2538 if ((val_aux & PLLE_AUX_PLLRE_SEL) ||
2539 (val_aux & PLLE_AUX_PLLP_SEL))
2540 WARN(1, "pll_e enabled with unsupported parent %s\n",
2541 (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" :
2544 val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
2545 pll_writel(val_aux, pll_params->aux_reg, pll);
2548 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2549 &tegra_clk_plle_tegra210_ops);
2556 struct clk *tegra_clk_register_pllc_tegra210(const char *name,
2557 const char *parent_name, void __iomem *clk_base,
2558 void __iomem *pmc, unsigned long flags,
2559 struct tegra_clk_pll_params *pll_params,
2562 struct clk *parent, *clk;
2563 const struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
2564 struct tegra_clk_pll *pll;
2565 unsigned long parent_rate;
2568 return ERR_PTR(-EINVAL);
2570 parent = __clk_lookup(parent_name);
2572 WARN(1, "parent clk %s of %s must be registered first\n",
2574 return ERR_PTR(-EINVAL);
2577 parent_rate = clk_get_rate(parent);
2579 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2581 if (pll_params->adjust_vco)
2582 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2585 pll_params->flags |= TEGRA_PLL_BYPASS;
2586 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2588 return ERR_CAST(pll);
2590 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2591 &tegra_clk_pll_ops);
2598 struct clk *tegra_clk_register_pllss_tegra210(const char *name,
2599 const char *parent_name, void __iomem *clk_base,
2600 unsigned long flags,
2601 struct tegra_clk_pll_params *pll_params,
2604 struct tegra_clk_pll *pll;
2605 struct clk *clk, *parent;
2606 unsigned long parent_rate;
2609 if (!pll_params->div_nmp)
2610 return ERR_PTR(-EINVAL);
2612 parent = __clk_lookup(parent_name);
2614 WARN(1, "parent clk %s of %s must be registered first\n",
2616 return ERR_PTR(-EINVAL);
2619 val = readl_relaxed(clk_base + pll_params->base_reg);
2620 if (val & PLLSS_REF_SRC_SEL_MASK) {
2621 WARN(1, "not supported reference clock for %s\n", name);
2622 return ERR_PTR(-EINVAL);
2625 parent_rate = clk_get_rate(parent);
2627 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2629 if (pll_params->adjust_vco)
2630 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2633 pll_params->flags |= TEGRA_PLL_BYPASS;
2634 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2636 return ERR_CAST(pll);
2638 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2639 &tegra_clk_pll_ops);
2647 struct clk *tegra_clk_register_pllmb(const char *name, const char *parent_name,
2648 void __iomem *clk_base, void __iomem *pmc,
2649 unsigned long flags,
2650 struct tegra_clk_pll_params *pll_params,
2653 struct tegra_clk_pll *pll;
2654 struct clk *clk, *parent;
2655 unsigned long parent_rate;
2657 if (!pll_params->pdiv_tohw)
2658 return ERR_PTR(-EINVAL);
2660 parent = __clk_lookup(parent_name);
2662 WARN(1, "parent clk %s of %s must be registered first\n",
2664 return ERR_PTR(-EINVAL);
2667 parent_rate = clk_get_rate(parent);
2669 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2671 if (pll_params->adjust_vco)
2672 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2675 pll_params->flags |= TEGRA_PLL_BYPASS;
2676 pll_params->flags |= TEGRA_PLLMB;
2677 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2679 return ERR_CAST(pll);
2681 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2682 &tegra_clk_pll_ops);