2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 #include <linux/slab.h>
19 #include <linux/delay.h>
20 #include <linux/err.h>
21 #include <linux/clk.h>
22 #include <linux/clk-provider.h>
26 #define PLL_BASE_BYPASS BIT(31)
27 #define PLL_BASE_ENABLE BIT(30)
28 #define PLL_BASE_REF_ENABLE BIT(29)
29 #define PLL_BASE_OVERRIDE BIT(28)
31 #define PLL_BASE_DIVP_SHIFT 20
32 #define PLL_BASE_DIVP_WIDTH 3
33 #define PLL_BASE_DIVN_SHIFT 8
34 #define PLL_BASE_DIVN_WIDTH 10
35 #define PLL_BASE_DIVM_SHIFT 0
36 #define PLL_BASE_DIVM_WIDTH 5
37 #define PLLU_POST_DIVP_MASK 0x1
39 #define PLL_MISC_DCCON_SHIFT 20
40 #define PLL_MISC_CPCON_SHIFT 8
41 #define PLL_MISC_CPCON_WIDTH 4
42 #define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1)
43 #define PLL_MISC_LFCON_SHIFT 4
44 #define PLL_MISC_LFCON_WIDTH 4
45 #define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1)
46 #define PLL_MISC_VCOCON_SHIFT 0
47 #define PLL_MISC_VCOCON_WIDTH 4
48 #define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1)
50 #define OUT_OF_TABLE_CPCON 8
52 #define PMC_PLLP_WB0_OVERRIDE 0xf8
53 #define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE BIT(12)
54 #define PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE BIT(11)
56 #define PLL_POST_LOCK_DELAY 50
58 #define PLLDU_LFCON_SET_DIVN 600
60 #define PLLE_BASE_DIVCML_SHIFT 24
61 #define PLLE_BASE_DIVCML_MASK 0xf
62 #define PLLE_BASE_DIVP_SHIFT 16
63 #define PLLE_BASE_DIVP_WIDTH 6
64 #define PLLE_BASE_DIVN_SHIFT 8
65 #define PLLE_BASE_DIVN_WIDTH 8
66 #define PLLE_BASE_DIVM_SHIFT 0
67 #define PLLE_BASE_DIVM_WIDTH 8
68 #define PLLE_BASE_ENABLE BIT(31)
70 #define PLLE_MISC_SETUP_BASE_SHIFT 16
71 #define PLLE_MISC_SETUP_BASE_MASK (0xffff << PLLE_MISC_SETUP_BASE_SHIFT)
72 #define PLLE_MISC_LOCK_ENABLE BIT(9)
73 #define PLLE_MISC_READY BIT(15)
74 #define PLLE_MISC_SETUP_EX_SHIFT 2
75 #define PLLE_MISC_SETUP_EX_MASK (3 << PLLE_MISC_SETUP_EX_SHIFT)
76 #define PLLE_MISC_SETUP_MASK (PLLE_MISC_SETUP_BASE_MASK | \
77 PLLE_MISC_SETUP_EX_MASK)
78 #define PLLE_MISC_SETUP_VALUE (7 << PLLE_MISC_SETUP_BASE_SHIFT)
80 #define PLLE_SS_CTRL 0x68
81 #define PLLE_SS_CNTL_BYPASS_SS BIT(10)
82 #define PLLE_SS_CNTL_INTERP_RESET BIT(11)
83 #define PLLE_SS_CNTL_SSC_BYP BIT(12)
84 #define PLLE_SS_CNTL_CENTER BIT(14)
85 #define PLLE_SS_CNTL_INVERT BIT(15)
86 #define PLLE_SS_DISABLE (PLLE_SS_CNTL_BYPASS_SS | PLLE_SS_CNTL_INTERP_RESET |\
88 #define PLLE_SS_MAX_MASK 0x1ff
89 #define PLLE_SS_MAX_VAL_TEGRA114 0x25
90 #define PLLE_SS_MAX_VAL_TEGRA210 0x21
91 #define PLLE_SS_INC_MASK (0xff << 16)
92 #define PLLE_SS_INC_VAL (0x1 << 16)
93 #define PLLE_SS_INCINTRV_MASK (0x3f << 24)
94 #define PLLE_SS_INCINTRV_VAL_TEGRA114 (0x20 << 24)
95 #define PLLE_SS_INCINTRV_VAL_TEGRA210 (0x23 << 24)
96 #define PLLE_SS_COEFFICIENTS_MASK \
97 (PLLE_SS_MAX_MASK | PLLE_SS_INC_MASK | PLLE_SS_INCINTRV_MASK)
98 #define PLLE_SS_COEFFICIENTS_VAL_TEGRA114 \
99 (PLLE_SS_MAX_VAL_TEGRA114 | PLLE_SS_INC_VAL |\
100 PLLE_SS_INCINTRV_VAL_TEGRA114)
101 #define PLLE_SS_COEFFICIENTS_VAL_TEGRA210 \
102 (PLLE_SS_MAX_VAL_TEGRA210 | PLLE_SS_INC_VAL |\
103 PLLE_SS_INCINTRV_VAL_TEGRA210)
105 #define PLLE_AUX_PLLP_SEL BIT(2)
106 #define PLLE_AUX_USE_LOCKDET BIT(3)
107 #define PLLE_AUX_ENABLE_SWCTL BIT(4)
108 #define PLLE_AUX_SS_SWCTL BIT(6)
109 #define PLLE_AUX_SEQ_ENABLE BIT(24)
110 #define PLLE_AUX_SEQ_START_STATE BIT(25)
111 #define PLLE_AUX_PLLRE_SEL BIT(28)
112 #define PLLE_AUX_SS_SEQ_INCLUDE BIT(31)
114 #define XUSBIO_PLL_CFG0 0x51c
115 #define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0)
116 #define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL BIT(2)
117 #define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET BIT(6)
118 #define XUSBIO_PLL_CFG0_SEQ_ENABLE BIT(24)
119 #define XUSBIO_PLL_CFG0_SEQ_START_STATE BIT(25)
121 #define SATA_PLL_CFG0 0x490
122 #define SATA_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0)
123 #define SATA_PLL_CFG0_PADPLL_USE_LOCKDET BIT(2)
124 #define SATA_PLL_CFG0_SEQ_ENABLE BIT(24)
125 #define SATA_PLL_CFG0_SEQ_START_STATE BIT(25)
127 #define PLLE_MISC_PLLE_PTS BIT(8)
128 #define PLLE_MISC_IDDQ_SW_VALUE BIT(13)
129 #define PLLE_MISC_IDDQ_SW_CTRL BIT(14)
130 #define PLLE_MISC_VREG_BG_CTRL_SHIFT 4
131 #define PLLE_MISC_VREG_BG_CTRL_MASK (3 << PLLE_MISC_VREG_BG_CTRL_SHIFT)
132 #define PLLE_MISC_VREG_CTRL_SHIFT 2
133 #define PLLE_MISC_VREG_CTRL_MASK (2 << PLLE_MISC_VREG_CTRL_SHIFT)
135 #define PLLCX_MISC_STROBE BIT(31)
136 #define PLLCX_MISC_RESET BIT(30)
137 #define PLLCX_MISC_SDM_DIV_SHIFT 28
138 #define PLLCX_MISC_SDM_DIV_MASK (0x3 << PLLCX_MISC_SDM_DIV_SHIFT)
139 #define PLLCX_MISC_FILT_DIV_SHIFT 26
140 #define PLLCX_MISC_FILT_DIV_MASK (0x3 << PLLCX_MISC_FILT_DIV_SHIFT)
141 #define PLLCX_MISC_ALPHA_SHIFT 18
142 #define PLLCX_MISC_DIV_LOW_RANGE \
143 ((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | \
144 (0x1 << PLLCX_MISC_FILT_DIV_SHIFT))
145 #define PLLCX_MISC_DIV_HIGH_RANGE \
146 ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | \
147 (0x2 << PLLCX_MISC_FILT_DIV_SHIFT))
148 #define PLLCX_MISC_COEF_LOW_RANGE \
149 ((0x14 << PLLCX_MISC_KA_SHIFT) | (0x38 << PLLCX_MISC_KB_SHIFT))
150 #define PLLCX_MISC_KA_SHIFT 2
151 #define PLLCX_MISC_KB_SHIFT 9
152 #define PLLCX_MISC_DEFAULT (PLLCX_MISC_COEF_LOW_RANGE | \
153 (0x19 << PLLCX_MISC_ALPHA_SHIFT) | \
154 PLLCX_MISC_DIV_LOW_RANGE | \
156 #define PLLCX_MISC1_DEFAULT 0x000d2308
157 #define PLLCX_MISC2_DEFAULT 0x30211200
158 #define PLLCX_MISC3_DEFAULT 0x200
160 #define PMC_SATA_PWRGT 0x1ac
161 #define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5)
162 #define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4)
164 #define PLLSS_MISC_KCP 0
165 #define PLLSS_MISC_KVCO 0
166 #define PLLSS_MISC_SETUP 0
167 #define PLLSS_EN_SDM 0
168 #define PLLSS_EN_SSC 0
169 #define PLLSS_EN_DITHER2 0
170 #define PLLSS_EN_DITHER 1
171 #define PLLSS_SDM_RESET 0
172 #define PLLSS_CLAMP 0
173 #define PLLSS_SDM_SSC_MAX 0
174 #define PLLSS_SDM_SSC_MIN 0
175 #define PLLSS_SDM_SSC_STEP 0
176 #define PLLSS_SDM_DIN 0
177 #define PLLSS_MISC_DEFAULT ((PLLSS_MISC_KCP << 25) | \
178 (PLLSS_MISC_KVCO << 24) | \
180 #define PLLSS_CFG_DEFAULT ((PLLSS_EN_SDM << 31) | \
181 (PLLSS_EN_SSC << 30) | \
182 (PLLSS_EN_DITHER2 << 29) | \
183 (PLLSS_EN_DITHER << 28) | \
184 (PLLSS_SDM_RESET) << 27 | \
186 #define PLLSS_CTRL1_DEFAULT \
187 ((PLLSS_SDM_SSC_MAX << 16) | PLLSS_SDM_SSC_MIN)
188 #define PLLSS_CTRL2_DEFAULT \
189 ((PLLSS_SDM_SSC_STEP << 16) | PLLSS_SDM_DIN)
190 #define PLLSS_LOCK_OVERRIDE BIT(24)
191 #define PLLSS_REF_SRC_SEL_SHIFT 25
192 #define PLLSS_REF_SRC_SEL_MASK (3 << PLLSS_REF_SRC_SEL_SHIFT)
194 #define UTMIP_PLL_CFG1 0x484
195 #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
196 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
197 #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
198 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
199 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15)
200 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
201 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17)
203 #define UTMIP_PLL_CFG2 0x488
204 #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6)
205 #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
206 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
207 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP BIT(1)
208 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
209 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP BIT(3)
210 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
211 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP BIT(5)
212 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN BIT(24)
213 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP BIT(25)
214 #define UTMIP_PLL_CFG2_PHY_XTAL_CLOCKEN BIT(30)
216 #define UTMIPLL_HW_PWRDN_CFG0 0x52c
217 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0)
218 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1)
219 #define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
220 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4)
221 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5)
222 #define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
223 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
224 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25)
226 #define PLLU_HW_PWRDN_CFG0 0x530
227 #define PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL BIT(0)
228 #define PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
229 #define PLLU_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
230 #define PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT BIT(7)
231 #define PLLU_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
232 #define PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE BIT(28)
234 #define XUSB_PLL_CFG0 0x534
235 #define XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY 0x3ff
236 #define XUSB_PLL_CFG0_PLLU_LOCK_DLY (0x3ff << 14)
238 #define PLLU_BASE_CLKENABLE_USB BIT(21)
239 #define PLLU_BASE_OVERRIDE BIT(24)
241 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
242 #define pll_readl_base(p) pll_readl(p->params->base_reg, p)
243 #define pll_readl_misc(p) pll_readl(p->params->misc_reg, p)
244 #define pll_override_readl(offset, p) readl_relaxed(p->pmc + offset)
245 #define pll_readl_sdm_din(p) pll_readl(p->params->sdm_din_reg, p)
246 #define pll_readl_sdm_ctrl(p) pll_readl(p->params->sdm_ctrl_reg, p)
248 #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset)
249 #define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p)
250 #define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p)
251 #define pll_override_writel(val, offset, p) writel(val, p->pmc + offset)
252 #define pll_writel_sdm_din(val, p) pll_writel(val, p->params->sdm_din_reg, p)
253 #define pll_writel_sdm_ctrl(val, p) pll_writel(val, p->params->sdm_ctrl_reg, p)
255 #define mask(w) ((1 << (w)) - 1)
256 #define divm_mask(p) mask(p->params->div_nmp->divm_width)
257 #define divn_mask(p) mask(p->params->div_nmp->divn_width)
258 #define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\
259 mask(p->params->div_nmp->divp_width))
260 #define sdm_din_mask(p) p->params->sdm_din_mask
261 #define sdm_en_mask(p) p->params->sdm_ctrl_en_mask
263 #define divm_shift(p) (p)->params->div_nmp->divm_shift
264 #define divn_shift(p) (p)->params->div_nmp->divn_shift
265 #define divp_shift(p) (p)->params->div_nmp->divp_shift
267 #define divm_mask_shifted(p) (divm_mask(p) << divm_shift(p))
268 #define divn_mask_shifted(p) (divn_mask(p) << divn_shift(p))
269 #define divp_mask_shifted(p) (divp_mask(p) << divp_shift(p))
271 #define divm_max(p) (divm_mask(p))
272 #define divn_max(p) (divn_mask(p))
273 #define divp_max(p) (1 << (divp_mask(p)))
275 #define sdin_din_to_data(din) ((u16)((din) ? : 0xFFFFU))
276 #define sdin_data_to_din(dat) (((dat) == 0xFFFFU) ? 0 : (s16)dat)
278 static struct div_nmp default_nmp = {
279 .divn_shift = PLL_BASE_DIVN_SHIFT,
280 .divn_width = PLL_BASE_DIVN_WIDTH,
281 .divm_shift = PLL_BASE_DIVM_SHIFT,
282 .divm_width = PLL_BASE_DIVM_WIDTH,
283 .divp_shift = PLL_BASE_DIVP_SHIFT,
284 .divp_width = PLL_BASE_DIVP_WIDTH,
287 static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
291 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK))
294 if (!(pll->params->flags & TEGRA_PLL_HAS_LOCK_ENABLE))
297 val = pll_readl_misc(pll);
298 val |= BIT(pll->params->lock_enable_bit_idx);
299 pll_writel_misc(val, pll);
302 static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll)
306 void __iomem *lock_addr;
308 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) {
309 udelay(pll->params->lock_delay);
313 lock_addr = pll->clk_base;
314 if (pll->params->flags & TEGRA_PLL_LOCK_MISC)
315 lock_addr += pll->params->misc_reg;
317 lock_addr += pll->params->base_reg;
319 lock_mask = pll->params->lock_mask;
321 for (i = 0; i < pll->params->lock_delay; i++) {
322 val = readl_relaxed(lock_addr);
323 if ((val & lock_mask) == lock_mask) {
324 udelay(PLL_POST_LOCK_DELAY);
327 udelay(2); /* timeout = 2 * lock time */
330 pr_err("%s: Timed out waiting for pll %s lock\n", __func__,
331 clk_hw_get_name(&pll->hw));
336 int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll)
338 return clk_pll_wait_for_lock(pll);
341 static int clk_pll_is_enabled(struct clk_hw *hw)
343 struct tegra_clk_pll *pll = to_clk_pll(hw);
346 if (pll->params->flags & TEGRA_PLLM) {
347 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
348 if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)
349 return val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE ? 1 : 0;
352 val = pll_readl_base(pll);
354 return val & PLL_BASE_ENABLE ? 1 : 0;
357 static void _clk_pll_enable(struct clk_hw *hw)
359 struct tegra_clk_pll *pll = to_clk_pll(hw);
362 if (pll->params->iddq_reg) {
363 val = pll_readl(pll->params->iddq_reg, pll);
364 val &= ~BIT(pll->params->iddq_bit_idx);
365 pll_writel(val, pll->params->iddq_reg, pll);
369 if (pll->params->reset_reg) {
370 val = pll_readl(pll->params->reset_reg, pll);
371 val &= ~BIT(pll->params->reset_bit_idx);
372 pll_writel(val, pll->params->reset_reg, pll);
375 clk_pll_enable_lock(pll);
377 val = pll_readl_base(pll);
378 if (pll->params->flags & TEGRA_PLL_BYPASS)
379 val &= ~PLL_BASE_BYPASS;
380 val |= PLL_BASE_ENABLE;
381 pll_writel_base(val, pll);
383 if (pll->params->flags & TEGRA_PLLM) {
384 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
385 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
386 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
390 static void _clk_pll_disable(struct clk_hw *hw)
392 struct tegra_clk_pll *pll = to_clk_pll(hw);
395 val = pll_readl_base(pll);
396 if (pll->params->flags & TEGRA_PLL_BYPASS)
397 val &= ~PLL_BASE_BYPASS;
398 val &= ~PLL_BASE_ENABLE;
399 pll_writel_base(val, pll);
401 if (pll->params->flags & TEGRA_PLLM) {
402 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
403 val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
404 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
407 if (pll->params->reset_reg) {
408 val = pll_readl(pll->params->reset_reg, pll);
409 val |= BIT(pll->params->reset_bit_idx);
410 pll_writel(val, pll->params->reset_reg, pll);
413 if (pll->params->iddq_reg) {
414 val = pll_readl(pll->params->iddq_reg, pll);
415 val |= BIT(pll->params->iddq_bit_idx);
416 pll_writel(val, pll->params->iddq_reg, pll);
421 static int clk_pll_enable(struct clk_hw *hw)
423 struct tegra_clk_pll *pll = to_clk_pll(hw);
424 unsigned long flags = 0;
428 spin_lock_irqsave(pll->lock, flags);
432 ret = clk_pll_wait_for_lock(pll);
435 spin_unlock_irqrestore(pll->lock, flags);
440 static void clk_pll_disable(struct clk_hw *hw)
442 struct tegra_clk_pll *pll = to_clk_pll(hw);
443 unsigned long flags = 0;
446 spin_lock_irqsave(pll->lock, flags);
448 _clk_pll_disable(hw);
451 spin_unlock_irqrestore(pll->lock, flags);
454 static int _p_div_to_hw(struct clk_hw *hw, u8 p_div)
456 struct tegra_clk_pll *pll = to_clk_pll(hw);
457 const struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
460 while (p_tohw->pdiv) {
461 if (p_div <= p_tohw->pdiv)
462 return p_tohw->hw_val;
470 int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div)
472 return _p_div_to_hw(&pll->hw, p_div);
475 static int _hw_to_p_div(struct clk_hw *hw, u8 p_div_hw)
477 struct tegra_clk_pll *pll = to_clk_pll(hw);
478 const struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
481 while (p_tohw->pdiv) {
482 if (p_div_hw == p_tohw->hw_val)
489 return 1 << p_div_hw;
492 static int _get_table_rate(struct clk_hw *hw,
493 struct tegra_clk_pll_freq_table *cfg,
494 unsigned long rate, unsigned long parent_rate)
496 struct tegra_clk_pll *pll = to_clk_pll(hw);
497 struct tegra_clk_pll_freq_table *sel;
500 for (sel = pll->params->freq_table; sel->input_rate != 0; sel++)
501 if (sel->input_rate == parent_rate &&
502 sel->output_rate == rate)
505 if (sel->input_rate == 0)
508 if (pll->params->pdiv_tohw) {
509 p = _p_div_to_hw(hw, sel->p);
516 cfg->input_rate = sel->input_rate;
517 cfg->output_rate = sel->output_rate;
521 cfg->cpcon = sel->cpcon;
522 cfg->sdm_data = sel->sdm_data;
527 static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
528 unsigned long rate, unsigned long parent_rate)
530 struct tegra_clk_pll *pll = to_clk_pll(hw);
535 switch (parent_rate) {
538 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
541 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
545 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
550 * PLL_P_OUT1 rate is not listed in PLLA table
552 cfreq = parent_rate / (parent_rate / 1000000);
555 pr_err("%s Unexpected reference rate %lu\n",
556 __func__, parent_rate);
560 /* Raise VCO to guarantee 0.5% accuracy */
561 for (cfg->output_rate = rate; cfg->output_rate < 200 * cfreq;
562 cfg->output_rate <<= 1)
565 cfg->m = parent_rate / cfreq;
566 cfg->n = cfg->output_rate / cfreq;
567 cfg->cpcon = OUT_OF_TABLE_CPCON;
569 if (cfg->m > divm_max(pll) || cfg->n > divn_max(pll) ||
570 (1 << p_div) > divp_max(pll)
571 || cfg->output_rate > pll->params->vco_max) {
575 cfg->output_rate >>= p_div;
577 if (pll->params->pdiv_tohw) {
578 ret = _p_div_to_hw(hw, 1 << p_div);
590 * SDM (Sigma Delta Modulator) divisor is 16-bit 2's complement signed number
591 * within (-2^12 ... 2^12-1) range. Represented in PLL data structure as
592 * unsigned 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used
593 * to indicate that SDM is disabled.
595 * Effective ndiv value when SDM is enabled: ndiv + 1/2 + sdm_din/2^13
597 static void clk_pll_set_sdm_data(struct clk_hw *hw,
598 struct tegra_clk_pll_freq_table *cfg)
600 struct tegra_clk_pll *pll = to_clk_pll(hw);
604 if (!pll->params->sdm_din_reg)
608 val = pll_readl_sdm_din(pll) & (~sdm_din_mask(pll));
609 val |= sdin_data_to_din(cfg->sdm_data) & sdm_din_mask(pll);
610 pll_writel_sdm_din(val, pll);
613 val = pll_readl_sdm_ctrl(pll);
614 enabled = (val & sdm_en_mask(pll));
616 if (cfg->sdm_data == 0 && enabled)
617 val &= ~pll->params->sdm_ctrl_en_mask;
619 if (cfg->sdm_data != 0 && !enabled)
620 val |= pll->params->sdm_ctrl_en_mask;
622 pll_writel_sdm_ctrl(val, pll);
625 static void _update_pll_mnp(struct tegra_clk_pll *pll,
626 struct tegra_clk_pll_freq_table *cfg)
629 struct tegra_clk_pll_params *params = pll->params;
630 struct div_nmp *div_nmp = params->div_nmp;
632 if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
633 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
634 PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
635 val = pll_override_readl(params->pmc_divp_reg, pll);
636 val &= ~(divp_mask(pll) << div_nmp->override_divp_shift);
637 val |= cfg->p << div_nmp->override_divp_shift;
638 pll_override_writel(val, params->pmc_divp_reg, pll);
640 val = pll_override_readl(params->pmc_divnm_reg, pll);
641 val &= ~((divm_mask(pll) << div_nmp->override_divm_shift) |
642 (divn_mask(pll) << div_nmp->override_divn_shift));
643 val |= (cfg->m << div_nmp->override_divm_shift) |
644 (cfg->n << div_nmp->override_divn_shift);
645 pll_override_writel(val, params->pmc_divnm_reg, pll);
647 val = pll_readl_base(pll);
649 val &= ~(divm_mask_shifted(pll) | divn_mask_shifted(pll) |
650 divp_mask_shifted(pll));
652 val |= (cfg->m << divm_shift(pll)) |
653 (cfg->n << divn_shift(pll)) |
654 (cfg->p << divp_shift(pll));
656 pll_writel_base(val, pll);
658 clk_pll_set_sdm_data(&pll->hw, cfg);
662 static void _get_pll_mnp(struct tegra_clk_pll *pll,
663 struct tegra_clk_pll_freq_table *cfg)
666 struct tegra_clk_pll_params *params = pll->params;
667 struct div_nmp *div_nmp = params->div_nmp;
669 if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
670 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
671 PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
672 val = pll_override_readl(params->pmc_divp_reg, pll);
673 cfg->p = (val >> div_nmp->override_divp_shift) & divp_mask(pll);
675 val = pll_override_readl(params->pmc_divnm_reg, pll);
676 cfg->m = (val >> div_nmp->override_divm_shift) & divm_mask(pll);
677 cfg->n = (val >> div_nmp->override_divn_shift) & divn_mask(pll);
679 val = pll_readl_base(pll);
681 cfg->m = (val >> div_nmp->divm_shift) & divm_mask(pll);
682 cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll);
683 cfg->p = (val >> div_nmp->divp_shift) & divp_mask(pll);
685 if (pll->params->sdm_din_reg) {
686 if (sdm_en_mask(pll) & pll_readl_sdm_ctrl(pll)) {
687 val = pll_readl_sdm_din(pll);
688 val &= sdm_din_mask(pll);
689 cfg->sdm_data = sdin_din_to_data(val);
695 static void _update_pll_cpcon(struct tegra_clk_pll *pll,
696 struct tegra_clk_pll_freq_table *cfg,
701 val = pll_readl_misc(pll);
703 val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT);
704 val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT;
706 if (pll->params->flags & TEGRA_PLL_SET_LFCON) {
707 val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT);
708 if (cfg->n >= PLLDU_LFCON_SET_DIVN)
709 val |= 1 << PLL_MISC_LFCON_SHIFT;
710 } else if (pll->params->flags & TEGRA_PLL_SET_DCCON) {
711 val &= ~(1 << PLL_MISC_DCCON_SHIFT);
712 if (rate >= (pll->params->vco_max >> 1))
713 val |= 1 << PLL_MISC_DCCON_SHIFT;
716 pll_writel_misc(val, pll);
719 static void pll_clk_start_ss(struct tegra_clk_pll *pll)
721 if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
722 u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
724 val |= pll->params->ssc_ctrl_en_mask;
725 pll_writel(val, pll->params->ssc_ctrl_reg, pll);
729 static void pll_clk_stop_ss(struct tegra_clk_pll *pll)
731 if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
732 u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
734 val &= ~pll->params->ssc_ctrl_en_mask;
735 pll_writel(val, pll->params->ssc_ctrl_reg, pll);
739 static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
742 struct tegra_clk_pll *pll = to_clk_pll(hw);
743 struct tegra_clk_pll_freq_table old_cfg;
746 state = clk_pll_is_enabled(hw);
748 _get_pll_mnp(pll, &old_cfg);
750 if (state && pll->params->defaults_set && pll->params->dyn_ramp &&
751 (cfg->m == old_cfg.m) && (cfg->p == old_cfg.p)) {
752 ret = pll->params->dyn_ramp(pll, cfg);
758 pll_clk_stop_ss(pll);
759 _clk_pll_disable(hw);
762 if (!pll->params->defaults_set && pll->params->set_defaults)
763 pll->params->set_defaults(pll);
765 _update_pll_mnp(pll, cfg);
767 if (pll->params->flags & TEGRA_PLL_HAS_CPCON)
768 _update_pll_cpcon(pll, cfg, rate);
772 ret = clk_pll_wait_for_lock(pll);
773 pll_clk_start_ss(pll);
779 static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
780 unsigned long parent_rate)
782 struct tegra_clk_pll *pll = to_clk_pll(hw);
783 struct tegra_clk_pll_freq_table cfg, old_cfg;
784 unsigned long flags = 0;
787 if (pll->params->flags & TEGRA_PLL_FIXED) {
788 if (rate != pll->params->fixed_rate) {
789 pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
790 __func__, clk_hw_get_name(hw),
791 pll->params->fixed_rate, rate);
797 if (_get_table_rate(hw, &cfg, rate, parent_rate) &&
798 pll->params->calc_rate(hw, &cfg, rate, parent_rate)) {
799 pr_err("%s: Failed to set %s rate %lu\n", __func__,
800 clk_hw_get_name(hw), rate);
805 spin_lock_irqsave(pll->lock, flags);
807 _get_pll_mnp(pll, &old_cfg);
808 if (pll->params->flags & TEGRA_PLL_VCO_OUT)
811 if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p ||
812 old_cfg.sdm_data != cfg.sdm_data)
813 ret = _program_pll(hw, &cfg, rate);
816 spin_unlock_irqrestore(pll->lock, flags);
821 static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
822 unsigned long *prate)
824 struct tegra_clk_pll *pll = to_clk_pll(hw);
825 struct tegra_clk_pll_freq_table cfg;
827 if (pll->params->flags & TEGRA_PLL_FIXED) {
828 /* PLLM/MB are used for memory; we do not change rate */
829 if (pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB))
830 return clk_hw_get_rate(hw);
831 return pll->params->fixed_rate;
834 if (_get_table_rate(hw, &cfg, rate, *prate) &&
835 pll->params->calc_rate(hw, &cfg, rate, *prate))
838 return cfg.output_rate;
841 static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
842 unsigned long parent_rate)
844 struct tegra_clk_pll *pll = to_clk_pll(hw);
845 struct tegra_clk_pll_freq_table cfg;
847 u64 rate = parent_rate;
850 val = pll_readl_base(pll);
852 if ((pll->params->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS))
855 if ((pll->params->flags & TEGRA_PLL_FIXED) &&
856 !(pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
857 !(val & PLL_BASE_OVERRIDE)) {
858 struct tegra_clk_pll_freq_table sel;
859 if (_get_table_rate(hw, &sel, pll->params->fixed_rate,
861 pr_err("Clock %s has unknown fixed frequency\n",
862 clk_hw_get_name(hw));
865 return pll->params->fixed_rate;
868 _get_pll_mnp(pll, &cfg);
870 if (pll->params->flags & TEGRA_PLL_VCO_OUT) {
873 pdiv = _hw_to_p_div(hw, cfg.p);
875 WARN(1, "Clock %s has invalid pdiv value : 0x%x\n",
876 clk_hw_get_name(hw), cfg.p);
881 if (pll->params->set_gain)
882 pll->params->set_gain(&cfg);
892 static int clk_plle_training(struct tegra_clk_pll *pll)
895 unsigned long timeout;
901 * PLLE is already disabled, and setup cleared;
902 * create falling edge on PLLE IDDQ input.
904 val = readl(pll->pmc + PMC_SATA_PWRGT);
905 val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
906 writel(val, pll->pmc + PMC_SATA_PWRGT);
908 val = readl(pll->pmc + PMC_SATA_PWRGT);
909 val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
910 writel(val, pll->pmc + PMC_SATA_PWRGT);
912 val = readl(pll->pmc + PMC_SATA_PWRGT);
913 val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
914 writel(val, pll->pmc + PMC_SATA_PWRGT);
916 val = pll_readl_misc(pll);
918 timeout = jiffies + msecs_to_jiffies(100);
920 val = pll_readl_misc(pll);
921 if (val & PLLE_MISC_READY)
923 if (time_after(jiffies, timeout)) {
924 pr_err("%s: timeout waiting for PLLE\n", __func__);
933 static int clk_plle_enable(struct clk_hw *hw)
935 struct tegra_clk_pll *pll = to_clk_pll(hw);
936 unsigned long input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
937 struct tegra_clk_pll_freq_table sel;
941 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
946 val = pll_readl_misc(pll);
947 val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK);
948 pll_writel_misc(val, pll);
950 val = pll_readl_misc(pll);
951 if (!(val & PLLE_MISC_READY)) {
952 err = clk_plle_training(pll);
957 if (pll->params->flags & TEGRA_PLLE_CONFIGURE) {
958 /* configure dividers */
959 val = pll_readl_base(pll);
960 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
961 divm_mask_shifted(pll));
962 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
963 val |= sel.m << divm_shift(pll);
964 val |= sel.n << divn_shift(pll);
965 val |= sel.p << divp_shift(pll);
966 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
967 pll_writel_base(val, pll);
970 val = pll_readl_misc(pll);
971 val |= PLLE_MISC_SETUP_VALUE;
972 val |= PLLE_MISC_LOCK_ENABLE;
973 pll_writel_misc(val, pll);
975 val = readl(pll->clk_base + PLLE_SS_CTRL);
976 val &= ~PLLE_SS_COEFFICIENTS_MASK;
977 val |= PLLE_SS_DISABLE;
978 writel(val, pll->clk_base + PLLE_SS_CTRL);
980 val = pll_readl_base(pll);
981 val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE);
982 pll_writel_base(val, pll);
984 clk_pll_wait_for_lock(pll);
989 static unsigned long clk_plle_recalc_rate(struct clk_hw *hw,
990 unsigned long parent_rate)
992 struct tegra_clk_pll *pll = to_clk_pll(hw);
993 u32 val = pll_readl_base(pll);
994 u32 divn = 0, divm = 0, divp = 0;
995 u64 rate = parent_rate;
997 divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll));
998 divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll));
999 divm = (val >> pll->params->div_nmp->divm_shift) & (divm_mask(pll));
1007 const struct clk_ops tegra_clk_pll_ops = {
1008 .is_enabled = clk_pll_is_enabled,
1009 .enable = clk_pll_enable,
1010 .disable = clk_pll_disable,
1011 .recalc_rate = clk_pll_recalc_rate,
1012 .round_rate = clk_pll_round_rate,
1013 .set_rate = clk_pll_set_rate,
1016 const struct clk_ops tegra_clk_plle_ops = {
1017 .recalc_rate = clk_plle_recalc_rate,
1018 .is_enabled = clk_pll_is_enabled,
1019 .disable = clk_pll_disable,
1020 .enable = clk_plle_enable,
1024 * Structure defining the fields for USB UTMI clocks Parameters.
1026 struct utmi_clk_param {
1027 /* Oscillator Frequency in Hz */
1029 /* UTMIP PLL Enable Delay Count */
1030 u8 enable_delay_count;
1031 /* UTMIP PLL Stable count */
1033 /* UTMIP PLL Active delay count */
1034 u8 active_delay_count;
1035 /* UTMIP PLL Xtal frequency count */
1039 static const struct utmi_clk_param utmi_parameters[] = {
1041 .osc_frequency = 13000000, .enable_delay_count = 0x02,
1042 .stable_count = 0x33, .active_delay_count = 0x05,
1043 .xtal_freq_count = 0x7f
1045 .osc_frequency = 19200000, .enable_delay_count = 0x03,
1046 .stable_count = 0x4b, .active_delay_count = 0x06,
1047 .xtal_freq_count = 0xbb
1049 .osc_frequency = 12000000, .enable_delay_count = 0x02,
1050 .stable_count = 0x2f, .active_delay_count = 0x04,
1051 .xtal_freq_count = 0x76
1053 .osc_frequency = 26000000, .enable_delay_count = 0x04,
1054 .stable_count = 0x66, .active_delay_count = 0x09,
1055 .xtal_freq_count = 0xfe
1057 .osc_frequency = 16800000, .enable_delay_count = 0x03,
1058 .stable_count = 0x41, .active_delay_count = 0x0a,
1059 .xtal_freq_count = 0xa4
1061 .osc_frequency = 38400000, .enable_delay_count = 0x0,
1062 .stable_count = 0x0, .active_delay_count = 0x6,
1063 .xtal_freq_count = 0x80
1067 static int clk_pllu_enable(struct clk_hw *hw)
1069 struct tegra_clk_pll *pll = to_clk_pll(hw);
1070 struct clk_hw *pll_ref = clk_hw_get_parent(hw);
1071 struct clk_hw *osc = clk_hw_get_parent(pll_ref);
1072 const struct utmi_clk_param *params = NULL;
1073 unsigned long flags = 0, input_rate;
1079 pr_err("%s: failed to get OSC clock\n", __func__);
1083 input_rate = clk_hw_get_rate(osc);
1086 spin_lock_irqsave(pll->lock, flags);
1088 if (!clk_pll_is_enabled(hw))
1089 _clk_pll_enable(hw);
1091 ret = clk_pll_wait_for_lock(pll);
1095 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
1096 if (input_rate == utmi_parameters[i].osc_frequency) {
1097 params = &utmi_parameters[i];
1103 pr_err("%s: unexpected input rate %lu Hz\n", __func__,
1109 value = pll_readl_base(pll);
1110 value &= ~PLLU_BASE_OVERRIDE;
1111 pll_writel_base(value, pll);
1113 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2);
1114 /* Program UTMIP PLL stable and active counts */
1115 value &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1116 value |= UTMIP_PLL_CFG2_STABLE_COUNT(params->stable_count);
1117 value &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1118 value |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(params->active_delay_count);
1119 /* Remove power downs from UTMIP PLL control bits */
1120 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
1121 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
1122 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
1123 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2);
1125 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
1126 /* Program UTMIP PLL delay and oscillator frequency counts */
1127 value &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1128 value |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(params->enable_delay_count);
1129 value &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1130 value |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(params->xtal_freq_count);
1131 /* Remove power downs from UTMIP PLL control bits */
1132 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1133 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
1134 value &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
1135 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
1139 spin_unlock_irqrestore(pll->lock, flags);
1144 static const struct clk_ops tegra_clk_pllu_ops = {
1145 .is_enabled = clk_pll_is_enabled,
1146 .enable = clk_pllu_enable,
1147 .disable = clk_pll_disable,
1148 .recalc_rate = clk_pll_recalc_rate,
1149 .round_rate = clk_pll_round_rate,
1150 .set_rate = clk_pll_set_rate,
1153 static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params,
1154 unsigned long parent_rate)
1156 u16 mdiv = parent_rate / pll_params->cf_min;
1158 if (pll_params->flags & TEGRA_MDIV_NEW)
1159 return (!pll_params->mdiv_default ? mdiv :
1160 min(mdiv, pll_params->mdiv_default));
1162 if (pll_params->mdiv_default)
1163 return pll_params->mdiv_default;
1165 if (parent_rate > pll_params->cf_max)
1171 static int _calc_dynamic_ramp_rate(struct clk_hw *hw,
1172 struct tegra_clk_pll_freq_table *cfg,
1173 unsigned long rate, unsigned long parent_rate)
1175 struct tegra_clk_pll *pll = to_clk_pll(hw);
1182 p = DIV_ROUND_UP(pll->params->vco_min, rate);
1183 cfg->m = _pll_fixed_mdiv(pll->params, parent_rate);
1184 cfg->output_rate = rate * p;
1185 cfg->n = cfg->output_rate * cfg->m / parent_rate;
1186 cfg->input_rate = parent_rate;
1188 p_div = _p_div_to_hw(hw, p);
1194 if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max)
1200 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
1201 defined(CONFIG_ARCH_TEGRA_124_SOC) || \
1202 defined(CONFIG_ARCH_TEGRA_132_SOC) || \
1203 defined(CONFIG_ARCH_TEGRA_210_SOC)
1205 u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate)
1207 struct tegra_clk_pll *pll = to_clk_pll(hw);
1209 return (u16)_pll_fixed_mdiv(pll->params, input_rate);
1212 static unsigned long _clip_vco_min(unsigned long vco_min,
1213 unsigned long parent_rate)
1215 return DIV_ROUND_UP(vco_min, parent_rate) * parent_rate;
1218 static int _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params,
1219 void __iomem *clk_base,
1220 unsigned long parent_rate)
1225 switch (parent_rate) {
1241 pr_err("%s: Unexpected reference rate %lu\n",
1242 __func__, parent_rate);
1247 val = step_a << pll_params->stepa_shift;
1248 val |= step_b << pll_params->stepb_shift;
1249 writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg);
1254 static int _pll_ramp_calc_pll(struct clk_hw *hw,
1255 struct tegra_clk_pll_freq_table *cfg,
1256 unsigned long rate, unsigned long parent_rate)
1258 struct tegra_clk_pll *pll = to_clk_pll(hw);
1261 err = _get_table_rate(hw, cfg, rate, parent_rate);
1263 err = _calc_dynamic_ramp_rate(hw, cfg, rate, parent_rate);
1265 if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) {
1272 if (cfg->p > pll->params->max_p)
1279 static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate,
1280 unsigned long parent_rate)
1282 struct tegra_clk_pll *pll = to_clk_pll(hw);
1283 struct tegra_clk_pll_freq_table cfg, old_cfg;
1284 unsigned long flags = 0;
1287 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
1292 spin_lock_irqsave(pll->lock, flags);
1294 _get_pll_mnp(pll, &old_cfg);
1295 if (pll->params->flags & TEGRA_PLL_VCO_OUT)
1298 if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p)
1299 ret = _program_pll(hw, &cfg, rate);
1302 spin_unlock_irqrestore(pll->lock, flags);
1307 static long clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate,
1308 unsigned long *prate)
1310 struct tegra_clk_pll *pll = to_clk_pll(hw);
1311 struct tegra_clk_pll_freq_table cfg;
1313 u64 output_rate = *prate;
1315 ret = _pll_ramp_calc_pll(hw, &cfg, rate, *prate);
1319 p_div = _hw_to_p_div(hw, cfg.p);
1323 if (pll->params->set_gain)
1324 pll->params->set_gain(&cfg);
1326 output_rate *= cfg.n;
1327 do_div(output_rate, cfg.m * p_div);
1332 static void _pllcx_strobe(struct tegra_clk_pll *pll)
1336 val = pll_readl_misc(pll);
1337 val |= PLLCX_MISC_STROBE;
1338 pll_writel_misc(val, pll);
1341 val &= ~PLLCX_MISC_STROBE;
1342 pll_writel_misc(val, pll);
1345 static int clk_pllc_enable(struct clk_hw *hw)
1347 struct tegra_clk_pll *pll = to_clk_pll(hw);
1350 unsigned long flags = 0;
1353 spin_lock_irqsave(pll->lock, flags);
1355 _clk_pll_enable(hw);
1358 val = pll_readl_misc(pll);
1359 val &= ~PLLCX_MISC_RESET;
1360 pll_writel_misc(val, pll);
1365 ret = clk_pll_wait_for_lock(pll);
1368 spin_unlock_irqrestore(pll->lock, flags);
1373 static void _clk_pllc_disable(struct clk_hw *hw)
1375 struct tegra_clk_pll *pll = to_clk_pll(hw);
1378 _clk_pll_disable(hw);
1380 val = pll_readl_misc(pll);
1381 val |= PLLCX_MISC_RESET;
1382 pll_writel_misc(val, pll);
1386 static void clk_pllc_disable(struct clk_hw *hw)
1388 struct tegra_clk_pll *pll = to_clk_pll(hw);
1389 unsigned long flags = 0;
1392 spin_lock_irqsave(pll->lock, flags);
1394 _clk_pllc_disable(hw);
1397 spin_unlock_irqrestore(pll->lock, flags);
1400 static int _pllcx_update_dynamic_coef(struct tegra_clk_pll *pll,
1401 unsigned long input_rate, u32 n)
1403 u32 val, n_threshold;
1405 switch (input_rate) {
1420 pr_err("%s: Unexpected reference rate %lu\n",
1421 __func__, input_rate);
1425 val = pll_readl_misc(pll);
1426 val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK);
1427 val |= n <= n_threshold ?
1428 PLLCX_MISC_DIV_LOW_RANGE : PLLCX_MISC_DIV_HIGH_RANGE;
1429 pll_writel_misc(val, pll);
1434 static int clk_pllc_set_rate(struct clk_hw *hw, unsigned long rate,
1435 unsigned long parent_rate)
1437 struct tegra_clk_pll_freq_table cfg, old_cfg;
1438 struct tegra_clk_pll *pll = to_clk_pll(hw);
1439 unsigned long flags = 0;
1443 spin_lock_irqsave(pll->lock, flags);
1445 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
1449 _get_pll_mnp(pll, &old_cfg);
1451 if (cfg.m != old_cfg.m) {
1456 if (old_cfg.n == cfg.n && old_cfg.p == cfg.p)
1459 state = clk_pll_is_enabled(hw);
1461 _clk_pllc_disable(hw);
1463 ret = _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
1467 _update_pll_mnp(pll, &cfg);
1470 ret = clk_pllc_enable(hw);
1474 spin_unlock_irqrestore(pll->lock, flags);
1479 static long _pllre_calc_rate(struct tegra_clk_pll *pll,
1480 struct tegra_clk_pll_freq_table *cfg,
1481 unsigned long rate, unsigned long parent_rate)
1484 u64 output_rate = parent_rate;
1486 m = _pll_fixed_mdiv(pll->params, parent_rate);
1487 n = rate * m / parent_rate;
1490 do_div(output_rate, m);
1500 static int clk_pllre_set_rate(struct clk_hw *hw, unsigned long rate,
1501 unsigned long parent_rate)
1503 struct tegra_clk_pll_freq_table cfg, old_cfg;
1504 struct tegra_clk_pll *pll = to_clk_pll(hw);
1505 unsigned long flags = 0;
1509 spin_lock_irqsave(pll->lock, flags);
1511 _pllre_calc_rate(pll, &cfg, rate, parent_rate);
1512 _get_pll_mnp(pll, &old_cfg);
1515 if (cfg.m != old_cfg.m || cfg.n != old_cfg.n) {
1516 state = clk_pll_is_enabled(hw);
1518 _clk_pll_disable(hw);
1520 _update_pll_mnp(pll, &cfg);
1523 _clk_pll_enable(hw);
1524 ret = clk_pll_wait_for_lock(pll);
1529 spin_unlock_irqrestore(pll->lock, flags);
1534 static unsigned long clk_pllre_recalc_rate(struct clk_hw *hw,
1535 unsigned long parent_rate)
1537 struct tegra_clk_pll_freq_table cfg;
1538 struct tegra_clk_pll *pll = to_clk_pll(hw);
1539 u64 rate = parent_rate;
1541 _get_pll_mnp(pll, &cfg);
1544 do_div(rate, cfg.m);
1549 static long clk_pllre_round_rate(struct clk_hw *hw, unsigned long rate,
1550 unsigned long *prate)
1552 struct tegra_clk_pll *pll = to_clk_pll(hw);
1554 return _pllre_calc_rate(pll, NULL, rate, *prate);
1557 static int clk_plle_tegra114_enable(struct clk_hw *hw)
1559 struct tegra_clk_pll *pll = to_clk_pll(hw);
1560 struct tegra_clk_pll_freq_table sel;
1563 unsigned long flags = 0;
1564 unsigned long input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
1566 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
1570 spin_lock_irqsave(pll->lock, flags);
1572 val = pll_readl_base(pll);
1573 val &= ~BIT(29); /* Disable lock override */
1574 pll_writel_base(val, pll);
1576 val = pll_readl(pll->params->aux_reg, pll);
1577 val |= PLLE_AUX_ENABLE_SWCTL;
1578 val &= ~PLLE_AUX_SEQ_ENABLE;
1579 pll_writel(val, pll->params->aux_reg, pll);
1582 val = pll_readl_misc(pll);
1583 val |= PLLE_MISC_LOCK_ENABLE;
1584 val |= PLLE_MISC_IDDQ_SW_CTRL;
1585 val &= ~PLLE_MISC_IDDQ_SW_VALUE;
1586 val |= PLLE_MISC_PLLE_PTS;
1587 val &= ~(PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK);
1588 pll_writel_misc(val, pll);
1591 val = pll_readl(PLLE_SS_CTRL, pll);
1592 val |= PLLE_SS_DISABLE;
1593 pll_writel(val, PLLE_SS_CTRL, pll);
1595 val = pll_readl_base(pll);
1596 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
1597 divm_mask_shifted(pll));
1598 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
1599 val |= sel.m << divm_shift(pll);
1600 val |= sel.n << divn_shift(pll);
1601 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
1602 pll_writel_base(val, pll);
1605 _clk_pll_enable(hw);
1606 ret = clk_pll_wait_for_lock(pll);
1611 val = pll_readl(PLLE_SS_CTRL, pll);
1612 val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
1613 val &= ~PLLE_SS_COEFFICIENTS_MASK;
1614 val |= PLLE_SS_COEFFICIENTS_VAL_TEGRA114;
1615 pll_writel(val, PLLE_SS_CTRL, pll);
1616 val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
1617 pll_writel(val, PLLE_SS_CTRL, pll);
1619 val &= ~PLLE_SS_CNTL_INTERP_RESET;
1620 pll_writel(val, PLLE_SS_CTRL, pll);
1623 /* Enable hw control of xusb brick pll */
1624 val = pll_readl_misc(pll);
1625 val &= ~PLLE_MISC_IDDQ_SW_CTRL;
1626 pll_writel_misc(val, pll);
1628 val = pll_readl(pll->params->aux_reg, pll);
1629 val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SEQ_START_STATE);
1630 val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
1631 pll_writel(val, pll->params->aux_reg, pll);
1633 val |= PLLE_AUX_SEQ_ENABLE;
1634 pll_writel(val, pll->params->aux_reg, pll);
1636 val = pll_readl(XUSBIO_PLL_CFG0, pll);
1637 val |= (XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET |
1638 XUSBIO_PLL_CFG0_SEQ_START_STATE);
1639 val &= ~(XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL |
1640 XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL);
1641 pll_writel(val, XUSBIO_PLL_CFG0, pll);
1643 val |= XUSBIO_PLL_CFG0_SEQ_ENABLE;
1644 pll_writel(val, XUSBIO_PLL_CFG0, pll);
1646 /* Enable hw control of SATA pll */
1647 val = pll_readl(SATA_PLL_CFG0, pll);
1648 val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL;
1649 val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET;
1650 val |= SATA_PLL_CFG0_SEQ_START_STATE;
1651 pll_writel(val, SATA_PLL_CFG0, pll);
1655 val = pll_readl(SATA_PLL_CFG0, pll);
1656 val |= SATA_PLL_CFG0_SEQ_ENABLE;
1657 pll_writel(val, SATA_PLL_CFG0, pll);
1661 spin_unlock_irqrestore(pll->lock, flags);
1666 static void clk_plle_tegra114_disable(struct clk_hw *hw)
1668 struct tegra_clk_pll *pll = to_clk_pll(hw);
1669 unsigned long flags = 0;
1673 spin_lock_irqsave(pll->lock, flags);
1675 _clk_pll_disable(hw);
1677 val = pll_readl_misc(pll);
1678 val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
1679 pll_writel_misc(val, pll);
1683 spin_unlock_irqrestore(pll->lock, flags);
1686 static int clk_pllu_tegra114_enable(struct clk_hw *hw)
1688 struct tegra_clk_pll *pll = to_clk_pll(hw);
1689 const struct utmi_clk_param *params = NULL;
1690 struct clk *osc = __clk_lookup("osc");
1691 unsigned long flags = 0, input_rate;
1697 pr_err("%s: failed to get OSC clock\n", __func__);
1701 input_rate = clk_hw_get_rate(__clk_get_hw(osc));
1704 spin_lock_irqsave(pll->lock, flags);
1706 if (!clk_pll_is_enabled(hw))
1707 _clk_pll_enable(hw);
1709 ret = clk_pll_wait_for_lock(pll);
1713 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
1714 if (input_rate == utmi_parameters[i].osc_frequency) {
1715 params = &utmi_parameters[i];
1721 pr_err("%s: unexpected input rate %lu Hz\n", __func__,
1727 value = pll_readl_base(pll);
1728 value &= ~PLLU_BASE_OVERRIDE;
1729 pll_writel_base(value, pll);
1731 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2);
1732 /* Program UTMIP PLL stable and active counts */
1733 value &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1734 value |= UTMIP_PLL_CFG2_STABLE_COUNT(params->stable_count);
1735 value &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1736 value |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(params->active_delay_count);
1737 /* Remove power downs from UTMIP PLL control bits */
1738 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
1739 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
1740 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
1741 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2);
1743 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
1744 /* Program UTMIP PLL delay and oscillator frequency counts */
1745 value &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1746 value |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(params->enable_delay_count);
1747 value &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1748 value |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(params->xtal_freq_count);
1749 /* Remove power downs from UTMIP PLL control bits */
1750 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1751 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
1752 value &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP;
1753 value &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
1754 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
1756 /* Setup HW control of UTMIPLL */
1757 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1758 value |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
1759 value &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
1760 value |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE;
1761 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1763 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
1764 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
1765 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1766 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
1771 * Setup SW override of UTMIPLL assuming USB2.0 ports are assigned
1774 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1775 value |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;
1776 value &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
1777 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1781 /* Enable HW control of UTMIPLL */
1782 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1783 value |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
1784 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1788 spin_unlock_irqrestore(pll->lock, flags);
1794 static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base,
1795 void __iomem *pmc, struct tegra_clk_pll_params *pll_params,
1798 struct tegra_clk_pll *pll;
1800 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
1802 return ERR_PTR(-ENOMEM);
1804 pll->clk_base = clk_base;
1807 pll->params = pll_params;
1810 if (!pll_params->div_nmp)
1811 pll_params->div_nmp = &default_nmp;
1816 static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll,
1817 const char *name, const char *parent_name, unsigned long flags,
1818 const struct clk_ops *ops)
1820 struct clk_init_data init;
1825 init.parent_names = (parent_name ? &parent_name : NULL);
1826 init.num_parents = (parent_name ? 1 : 0);
1828 /* Default to _calc_rate if unspecified */
1829 if (!pll->params->calc_rate) {
1830 if (pll->params->flags & TEGRA_PLLM)
1831 pll->params->calc_rate = _calc_dynamic_ramp_rate;
1833 pll->params->calc_rate = _calc_rate;
1836 if (pll->params->set_defaults)
1837 pll->params->set_defaults(pll);
1839 /* Data in .init is copied by clk_register(), so stack variable OK */
1840 pll->hw.init = &init;
1842 return clk_register(NULL, &pll->hw);
1845 struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
1846 void __iomem *clk_base, void __iomem *pmc,
1847 unsigned long flags, struct tegra_clk_pll_params *pll_params,
1850 struct tegra_clk_pll *pll;
1853 pll_params->flags |= TEGRA_PLL_BYPASS;
1855 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1857 return ERR_CAST(pll);
1859 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1860 &tegra_clk_pll_ops);
1867 static struct div_nmp pll_e_nmp = {
1868 .divn_shift = PLLE_BASE_DIVN_SHIFT,
1869 .divn_width = PLLE_BASE_DIVN_WIDTH,
1870 .divm_shift = PLLE_BASE_DIVM_SHIFT,
1871 .divm_width = PLLE_BASE_DIVM_WIDTH,
1872 .divp_shift = PLLE_BASE_DIVP_SHIFT,
1873 .divp_width = PLLE_BASE_DIVP_WIDTH,
1876 struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
1877 void __iomem *clk_base, void __iomem *pmc,
1878 unsigned long flags, struct tegra_clk_pll_params *pll_params,
1881 struct tegra_clk_pll *pll;
1884 pll_params->flags |= TEGRA_PLL_BYPASS;
1886 if (!pll_params->div_nmp)
1887 pll_params->div_nmp = &pll_e_nmp;
1889 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1891 return ERR_CAST(pll);
1893 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1894 &tegra_clk_plle_ops);
1901 struct clk *tegra_clk_register_pllu(const char *name, const char *parent_name,
1902 void __iomem *clk_base, unsigned long flags,
1903 struct tegra_clk_pll_params *pll_params, spinlock_t *lock)
1905 struct tegra_clk_pll *pll;
1908 pll_params->flags |= TEGRA_PLLU;
1910 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
1912 return ERR_CAST(pll);
1914 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1915 &tegra_clk_pllu_ops);
1922 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
1923 defined(CONFIG_ARCH_TEGRA_124_SOC) || \
1924 defined(CONFIG_ARCH_TEGRA_132_SOC) || \
1925 defined(CONFIG_ARCH_TEGRA_210_SOC)
1926 static const struct clk_ops tegra_clk_pllxc_ops = {
1927 .is_enabled = clk_pll_is_enabled,
1928 .enable = clk_pll_enable,
1929 .disable = clk_pll_disable,
1930 .recalc_rate = clk_pll_recalc_rate,
1931 .round_rate = clk_pll_ramp_round_rate,
1932 .set_rate = clk_pllxc_set_rate,
1935 static const struct clk_ops tegra_clk_pllc_ops = {
1936 .is_enabled = clk_pll_is_enabled,
1937 .enable = clk_pllc_enable,
1938 .disable = clk_pllc_disable,
1939 .recalc_rate = clk_pll_recalc_rate,
1940 .round_rate = clk_pll_ramp_round_rate,
1941 .set_rate = clk_pllc_set_rate,
1944 static const struct clk_ops tegra_clk_pllre_ops = {
1945 .is_enabled = clk_pll_is_enabled,
1946 .enable = clk_pll_enable,
1947 .disable = clk_pll_disable,
1948 .recalc_rate = clk_pllre_recalc_rate,
1949 .round_rate = clk_pllre_round_rate,
1950 .set_rate = clk_pllre_set_rate,
1953 static const struct clk_ops tegra_clk_plle_tegra114_ops = {
1954 .is_enabled = clk_pll_is_enabled,
1955 .enable = clk_plle_tegra114_enable,
1956 .disable = clk_plle_tegra114_disable,
1957 .recalc_rate = clk_pll_recalc_rate,
1960 static const struct clk_ops tegra_clk_pllu_tegra114_ops = {
1961 .is_enabled = clk_pll_is_enabled,
1962 .enable = clk_pllu_tegra114_enable,
1963 .disable = clk_pll_disable,
1964 .recalc_rate = clk_pll_recalc_rate,
1967 struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
1968 void __iomem *clk_base, void __iomem *pmc,
1969 unsigned long flags,
1970 struct tegra_clk_pll_params *pll_params,
1973 struct tegra_clk_pll *pll;
1974 struct clk *clk, *parent;
1975 unsigned long parent_rate;
1978 parent = __clk_lookup(parent_name);
1980 WARN(1, "parent clk %s of %s must be registered first\n",
1982 return ERR_PTR(-EINVAL);
1985 if (!pll_params->pdiv_tohw)
1986 return ERR_PTR(-EINVAL);
1988 parent_rate = clk_get_rate(parent);
1990 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1992 if (pll_params->adjust_vco)
1993 pll_params->vco_min = pll_params->adjust_vco(pll_params,
1997 * If the pll has a set_defaults callback, it will take care of
1998 * configuring dynamic ramping and setting IDDQ in that path.
2000 if (!pll_params->set_defaults) {
2003 err = _setup_dynamic_ramp(pll_params, clk_base, parent_rate);
2005 return ERR_PTR(err);
2007 val = readl_relaxed(clk_base + pll_params->base_reg);
2008 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
2010 if (val & PLL_BASE_ENABLE)
2011 WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx));
2013 val_iddq |= BIT(pll_params->iddq_bit_idx);
2014 writel_relaxed(val_iddq,
2015 clk_base + pll_params->iddq_reg);
2019 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2021 return ERR_CAST(pll);
2023 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2024 &tegra_clk_pllxc_ops);
2031 struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
2032 void __iomem *clk_base, void __iomem *pmc,
2033 unsigned long flags,
2034 struct tegra_clk_pll_params *pll_params,
2035 spinlock_t *lock, unsigned long parent_rate)
2038 struct tegra_clk_pll *pll;
2041 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2043 if (pll_params->adjust_vco)
2044 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2047 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2049 return ERR_CAST(pll);
2051 /* program minimum rate by default */
2053 val = pll_readl_base(pll);
2054 if (val & PLL_BASE_ENABLE)
2055 WARN_ON(readl_relaxed(clk_base + pll_params->iddq_reg) &
2056 BIT(pll_params->iddq_bit_idx));
2060 m = _pll_fixed_mdiv(pll_params, parent_rate);
2061 val = m << divm_shift(pll);
2062 val |= (pll_params->vco_min / parent_rate) << divn_shift(pll);
2063 pll_writel_base(val, pll);
2066 /* disable lock override */
2068 val = pll_readl_misc(pll);
2070 pll_writel_misc(val, pll);
2072 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2073 &tegra_clk_pllre_ops);
2080 struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
2081 void __iomem *clk_base, void __iomem *pmc,
2082 unsigned long flags,
2083 struct tegra_clk_pll_params *pll_params,
2086 struct tegra_clk_pll *pll;
2087 struct clk *clk, *parent;
2088 unsigned long parent_rate;
2090 if (!pll_params->pdiv_tohw)
2091 return ERR_PTR(-EINVAL);
2093 parent = __clk_lookup(parent_name);
2095 WARN(1, "parent clk %s of %s must be registered first\n",
2097 return ERR_PTR(-EINVAL);
2100 parent_rate = clk_get_rate(parent);
2102 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2104 if (pll_params->adjust_vco)
2105 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2108 pll_params->flags |= TEGRA_PLL_BYPASS;
2109 pll_params->flags |= TEGRA_PLLM;
2110 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2112 return ERR_CAST(pll);
2114 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2115 &tegra_clk_pll_ops);
2122 struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
2123 void __iomem *clk_base, void __iomem *pmc,
2124 unsigned long flags,
2125 struct tegra_clk_pll_params *pll_params,
2128 struct clk *parent, *clk;
2129 const struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
2130 struct tegra_clk_pll *pll;
2131 struct tegra_clk_pll_freq_table cfg;
2132 unsigned long parent_rate;
2135 return ERR_PTR(-EINVAL);
2137 parent = __clk_lookup(parent_name);
2139 WARN(1, "parent clk %s of %s must be registered first\n",
2141 return ERR_PTR(-EINVAL);
2144 parent_rate = clk_get_rate(parent);
2146 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2148 pll_params->flags |= TEGRA_PLL_BYPASS;
2149 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2151 return ERR_CAST(pll);
2154 * Most of PLLC register fields are shadowed, and can not be read
2155 * directly from PLL h/w. Hence, actual PLLC boot state is unknown.
2156 * Initialize PLL to default state: disabled, reset; shadow registers
2157 * loaded with default parameters; dividers are preset for half of
2158 * minimum VCO rate (the latter assured that shadowed divider settings
2159 * are within supported range).
2162 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
2163 cfg.n = cfg.m * pll_params->vco_min / parent_rate;
2165 while (p_tohw->pdiv) {
2166 if (p_tohw->pdiv == 2) {
2167 cfg.p = p_tohw->hw_val;
2173 if (!p_tohw->pdiv) {
2175 return ERR_PTR(-EINVAL);
2178 pll_writel_base(0, pll);
2179 _update_pll_mnp(pll, &cfg);
2181 pll_writel_misc(PLLCX_MISC_DEFAULT, pll);
2182 pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll);
2183 pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll);
2184 pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll);
2186 _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
2188 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2189 &tegra_clk_pllc_ops);
2196 struct clk *tegra_clk_register_plle_tegra114(const char *name,
2197 const char *parent_name,
2198 void __iomem *clk_base, unsigned long flags,
2199 struct tegra_clk_pll_params *pll_params,
2202 struct tegra_clk_pll *pll;
2206 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2208 return ERR_CAST(pll);
2210 /* ensure parent is set to pll_re_vco */
2212 val = pll_readl_base(pll);
2213 val_aux = pll_readl(pll_params->aux_reg, pll);
2215 if (val & PLL_BASE_ENABLE) {
2216 if ((val_aux & PLLE_AUX_PLLRE_SEL) ||
2217 (val_aux & PLLE_AUX_PLLP_SEL))
2218 WARN(1, "pll_e enabled with unsupported parent %s\n",
2219 (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" :
2222 val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
2223 pll_writel(val_aux, pll_params->aux_reg, pll);
2226 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2227 &tegra_clk_plle_tegra114_ops);
2235 tegra_clk_register_pllu_tegra114(const char *name, const char *parent_name,
2236 void __iomem *clk_base, unsigned long flags,
2237 struct tegra_clk_pll_params *pll_params,
2240 struct tegra_clk_pll *pll;
2243 pll_params->flags |= TEGRA_PLLU;
2245 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2247 return ERR_CAST(pll);
2249 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2250 &tegra_clk_pllu_tegra114_ops);
2258 #if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC)
2259 static const struct clk_ops tegra_clk_pllss_ops = {
2260 .is_enabled = clk_pll_is_enabled,
2261 .enable = clk_pll_enable,
2262 .disable = clk_pll_disable,
2263 .recalc_rate = clk_pll_recalc_rate,
2264 .round_rate = clk_pll_ramp_round_rate,
2265 .set_rate = clk_pllxc_set_rate,
2268 struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
2269 void __iomem *clk_base, unsigned long flags,
2270 struct tegra_clk_pll_params *pll_params,
2273 struct tegra_clk_pll *pll;
2274 struct clk *clk, *parent;
2275 struct tegra_clk_pll_freq_table cfg;
2276 unsigned long parent_rate;
2280 if (!pll_params->div_nmp)
2281 return ERR_PTR(-EINVAL);
2283 parent = __clk_lookup(parent_name);
2285 WARN(1, "parent clk %s of %s must be registered first\n",
2287 return ERR_PTR(-EINVAL);
2290 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2292 return ERR_CAST(pll);
2294 val = pll_readl_base(pll);
2295 val &= ~PLLSS_REF_SRC_SEL_MASK;
2296 pll_writel_base(val, pll);
2298 parent_rate = clk_get_rate(parent);
2300 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2302 /* initialize PLL to minimum rate */
2304 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
2305 cfg.n = cfg.m * pll_params->vco_min / parent_rate;
2307 for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++)
2311 return ERR_PTR(-EINVAL);
2314 cfg.p = pll_params->pdiv_tohw[i-1].hw_val;
2316 _update_pll_mnp(pll, &cfg);
2318 pll_writel_misc(PLLSS_MISC_DEFAULT, pll);
2319 pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll);
2320 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll);
2321 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll);
2323 val = pll_readl_base(pll);
2324 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
2325 if (val & PLL_BASE_ENABLE) {
2326 if (val_iddq & BIT(pll_params->iddq_bit_idx)) {
2327 WARN(1, "%s is on but IDDQ set\n", name);
2329 return ERR_PTR(-EINVAL);
2332 val_iddq |= BIT(pll_params->iddq_bit_idx);
2333 writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg);
2336 val &= ~PLLSS_LOCK_OVERRIDE;
2337 pll_writel_base(val, pll);
2339 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2340 &tegra_clk_pllss_ops);
2349 #if defined(CONFIG_ARCH_TEGRA_210_SOC)
2350 struct clk *tegra_clk_register_pllre_tegra210(const char *name,
2351 const char *parent_name, void __iomem *clk_base,
2352 void __iomem *pmc, unsigned long flags,
2353 struct tegra_clk_pll_params *pll_params,
2354 spinlock_t *lock, unsigned long parent_rate)
2357 struct tegra_clk_pll *pll;
2360 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2362 if (pll_params->adjust_vco)
2363 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2366 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2368 return ERR_CAST(pll);
2370 /* program minimum rate by default */
2372 val = pll_readl_base(pll);
2373 if (val & PLL_BASE_ENABLE)
2374 WARN_ON(readl_relaxed(clk_base + pll_params->iddq_reg) &
2375 BIT(pll_params->iddq_bit_idx));
2377 val = 0x4 << divm_shift(pll);
2378 val |= 0x41 << divn_shift(pll);
2379 pll_writel_base(val, pll);
2382 /* disable lock override */
2384 val = pll_readl_misc(pll);
2386 pll_writel_misc(val, pll);
2388 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2389 &tegra_clk_pllre_ops);
2396 static int clk_plle_tegra210_enable(struct clk_hw *hw)
2398 struct tegra_clk_pll *pll = to_clk_pll(hw);
2399 struct tegra_clk_pll_freq_table sel;
2402 unsigned long flags = 0;
2403 unsigned long input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
2405 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
2409 spin_lock_irqsave(pll->lock, flags);
2411 val = pll_readl(pll->params->aux_reg, pll);
2412 if (val & PLLE_AUX_SEQ_ENABLE)
2415 val = pll_readl_base(pll);
2416 val &= ~BIT(30); /* Disable lock override */
2417 pll_writel_base(val, pll);
2419 val = pll_readl_misc(pll);
2420 val |= PLLE_MISC_LOCK_ENABLE;
2421 val |= PLLE_MISC_IDDQ_SW_CTRL;
2422 val &= ~PLLE_MISC_IDDQ_SW_VALUE;
2423 val |= PLLE_MISC_PLLE_PTS;
2424 val &= ~(PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK);
2425 pll_writel_misc(val, pll);
2428 val = pll_readl(PLLE_SS_CTRL, pll);
2429 val |= PLLE_SS_DISABLE;
2430 pll_writel(val, PLLE_SS_CTRL, pll);
2432 val = pll_readl_base(pll);
2433 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
2434 divm_mask_shifted(pll));
2435 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
2436 val |= sel.m << divm_shift(pll);
2437 val |= sel.n << divn_shift(pll);
2438 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
2439 pll_writel_base(val, pll);
2442 val = pll_readl_base(pll);
2443 val |= PLLE_BASE_ENABLE;
2444 pll_writel_base(val, pll);
2446 ret = clk_pll_wait_for_lock(pll);
2451 val = pll_readl(PLLE_SS_CTRL, pll);
2452 val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
2453 val &= ~PLLE_SS_COEFFICIENTS_MASK;
2454 val |= PLLE_SS_COEFFICIENTS_VAL_TEGRA210;
2455 pll_writel(val, PLLE_SS_CTRL, pll);
2456 val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
2457 pll_writel(val, PLLE_SS_CTRL, pll);
2459 val &= ~PLLE_SS_CNTL_INTERP_RESET;
2460 pll_writel(val, PLLE_SS_CTRL, pll);
2463 val = pll_readl_misc(pll);
2464 val &= ~PLLE_MISC_IDDQ_SW_CTRL;
2465 pll_writel_misc(val, pll);
2467 val = pll_readl(pll->params->aux_reg, pll);
2468 val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SS_SEQ_INCLUDE);
2469 val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
2470 pll_writel(val, pll->params->aux_reg, pll);
2472 val |= PLLE_AUX_SEQ_ENABLE;
2473 pll_writel(val, pll->params->aux_reg, pll);
2477 spin_unlock_irqrestore(pll->lock, flags);
2482 static void clk_plle_tegra210_disable(struct clk_hw *hw)
2484 struct tegra_clk_pll *pll = to_clk_pll(hw);
2485 unsigned long flags = 0;
2489 spin_lock_irqsave(pll->lock, flags);
2491 /* If PLLE HW sequencer is enabled, SW should not disable PLLE */
2492 val = pll_readl(pll->params->aux_reg, pll);
2493 if (val & PLLE_AUX_SEQ_ENABLE)
2496 val = pll_readl_base(pll);
2497 val &= ~PLLE_BASE_ENABLE;
2498 pll_writel_base(val, pll);
2500 val = pll_readl(pll->params->aux_reg, pll);
2501 val |= PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL;
2502 pll_writel(val, pll->params->aux_reg, pll);
2504 val = pll_readl_misc(pll);
2505 val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
2506 pll_writel_misc(val, pll);
2511 spin_unlock_irqrestore(pll->lock, flags);
2514 static int clk_plle_tegra210_is_enabled(struct clk_hw *hw)
2516 struct tegra_clk_pll *pll = to_clk_pll(hw);
2519 val = pll_readl_base(pll);
2521 return val & PLLE_BASE_ENABLE ? 1 : 0;
2524 static int clk_pllu_tegra210_enable(struct clk_hw *hw)
2526 struct tegra_clk_pll *pll = to_clk_pll(hw);
2527 struct clk_hw *pll_ref = clk_hw_get_parent(hw);
2528 struct clk_hw *osc = clk_hw_get_parent(pll_ref);
2529 const struct utmi_clk_param *params = NULL;
2530 unsigned long flags = 0, input_rate;
2536 pr_err("%s: failed to get OSC clock\n", __func__);
2540 input_rate = clk_hw_get_rate(osc);
2543 spin_lock_irqsave(pll->lock, flags);
2545 _clk_pll_enable(hw);
2547 ret = clk_pll_wait_for_lock(pll);
2551 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
2552 if (input_rate == utmi_parameters[i].osc_frequency) {
2553 params = &utmi_parameters[i];
2559 pr_err("%s: unexpected input rate %lu Hz\n", __func__,
2565 value = pll_readl_base(pll);
2566 value &= ~PLLU_BASE_OVERRIDE;
2567 pll_writel_base(value, pll);
2569 /* Put PLLU under HW control */
2570 value = readl_relaxed(pll->clk_base + PLLU_HW_PWRDN_CFG0);
2571 value |= PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE |
2572 PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT |
2573 PLLU_HW_PWRDN_CFG0_USE_LOCKDET;
2574 value &= ~(PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL |
2575 PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL);
2576 writel_relaxed(value, pll->clk_base + PLLU_HW_PWRDN_CFG0);
2578 value = readl_relaxed(pll->clk_base + XUSB_PLL_CFG0);
2579 value &= ~XUSB_PLL_CFG0_PLLU_LOCK_DLY;
2580 writel_relaxed(value, pll->clk_base + XUSB_PLL_CFG0);
2584 value = readl_relaxed(pll->clk_base + PLLU_HW_PWRDN_CFG0);
2585 value |= PLLU_HW_PWRDN_CFG0_SEQ_ENABLE;
2586 writel_relaxed(value, pll->clk_base + PLLU_HW_PWRDN_CFG0);
2590 /* Disable PLLU clock branch to UTMIPLL since it uses OSC */
2591 value = pll_readl_base(pll);
2592 value &= ~PLLU_BASE_CLKENABLE_USB;
2593 pll_writel_base(value, pll);
2595 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
2596 if (value & UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE) {
2597 pr_debug("UTMIPLL already enabled\n");
2601 value &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
2602 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
2604 /* Program UTMIP PLL stable and active counts */
2605 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2);
2606 value &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
2607 value |= UTMIP_PLL_CFG2_STABLE_COUNT(params->stable_count);
2608 value &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
2609 value |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(params->active_delay_count);
2610 value |= UTMIP_PLL_CFG2_PHY_XTAL_CLOCKEN;
2611 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2);
2613 /* Program UTMIP PLL delay and oscillator frequency counts */
2614 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
2615 value &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
2616 value |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(params->enable_delay_count);
2617 value &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
2618 value |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(params->xtal_freq_count);
2619 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
2621 /* Remove power downs from UTMIP PLL control bits */
2622 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
2623 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
2624 value |= UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
2625 writel(value, pll->clk_base + UTMIP_PLL_CFG1);
2629 /* Enable samplers for SNPS, XUSB_HOST, XUSB_DEV */
2630 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2);
2631 value |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP;
2632 value |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP;
2633 value |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP;
2634 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
2635 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
2636 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN;
2637 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2);
2639 /* Setup HW control of UTMIPLL */
2640 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
2641 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
2642 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
2643 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
2645 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
2646 value |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
2647 value &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
2648 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
2652 value = readl_relaxed(pll->clk_base + XUSB_PLL_CFG0);
2653 value &= ~XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY;
2654 writel_relaxed(value, pll->clk_base + XUSB_PLL_CFG0);
2658 /* Enable HW control of UTMIPLL */
2659 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
2660 value |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
2661 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
2665 spin_unlock_irqrestore(pll->lock, flags);
2670 static const struct clk_ops tegra_clk_plle_tegra210_ops = {
2671 .is_enabled = clk_plle_tegra210_is_enabled,
2672 .enable = clk_plle_tegra210_enable,
2673 .disable = clk_plle_tegra210_disable,
2674 .recalc_rate = clk_pll_recalc_rate,
2677 static const struct clk_ops tegra_clk_pllu_tegra210_ops = {
2678 .is_enabled = clk_pll_is_enabled,
2679 .enable = clk_pllu_tegra210_enable,
2680 .disable = clk_pll_disable,
2681 .recalc_rate = clk_pllre_recalc_rate,
2684 struct clk *tegra_clk_register_plle_tegra210(const char *name,
2685 const char *parent_name,
2686 void __iomem *clk_base, unsigned long flags,
2687 struct tegra_clk_pll_params *pll_params,
2690 struct tegra_clk_pll *pll;
2694 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2696 return ERR_CAST(pll);
2698 /* ensure parent is set to pll_re_vco */
2700 val = pll_readl_base(pll);
2701 val_aux = pll_readl(pll_params->aux_reg, pll);
2703 if (val & PLLE_BASE_ENABLE) {
2704 if ((val_aux & PLLE_AUX_PLLRE_SEL) ||
2705 (val_aux & PLLE_AUX_PLLP_SEL))
2706 WARN(1, "pll_e enabled with unsupported parent %s\n",
2707 (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" :
2710 val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
2711 pll_writel(val_aux, pll_params->aux_reg, pll);
2714 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2715 &tegra_clk_plle_tegra210_ops);
2722 struct clk *tegra_clk_register_pllc_tegra210(const char *name,
2723 const char *parent_name, void __iomem *clk_base,
2724 void __iomem *pmc, unsigned long flags,
2725 struct tegra_clk_pll_params *pll_params,
2728 struct clk *parent, *clk;
2729 const struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
2730 struct tegra_clk_pll *pll;
2731 unsigned long parent_rate;
2734 return ERR_PTR(-EINVAL);
2736 parent = __clk_lookup(parent_name);
2738 WARN(1, "parent clk %s of %s must be registered first\n",
2740 return ERR_PTR(-EINVAL);
2743 parent_rate = clk_get_rate(parent);
2745 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2747 if (pll_params->adjust_vco)
2748 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2751 pll_params->flags |= TEGRA_PLL_BYPASS;
2752 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2754 return ERR_CAST(pll);
2756 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2757 &tegra_clk_pll_ops);
2764 struct clk *tegra_clk_register_pllxc_tegra210(const char *name,
2765 const char *parent_name, void __iomem *clk_base,
2766 void __iomem *pmc, unsigned long flags,
2767 struct tegra_clk_pll_params *pll_params,
2770 struct tegra_clk_pll *pll;
2771 struct clk *clk, *parent;
2772 unsigned long parent_rate;
2774 parent = __clk_lookup(parent_name);
2776 WARN(1, "parent clk %s of %s must be registered first\n",
2778 return ERR_PTR(-EINVAL);
2781 if (!pll_params->pdiv_tohw)
2782 return ERR_PTR(-EINVAL);
2784 parent_rate = clk_get_rate(parent);
2786 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2788 if (pll_params->adjust_vco)
2789 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2792 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2794 return ERR_CAST(pll);
2796 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2797 &tegra_clk_pll_ops);
2804 struct clk *tegra_clk_register_pllss_tegra210(const char *name,
2805 const char *parent_name, void __iomem *clk_base,
2806 unsigned long flags,
2807 struct tegra_clk_pll_params *pll_params,
2810 struct tegra_clk_pll *pll;
2811 struct clk *clk, *parent;
2812 struct tegra_clk_pll_freq_table cfg;
2813 unsigned long parent_rate;
2817 if (!pll_params->div_nmp)
2818 return ERR_PTR(-EINVAL);
2820 parent = __clk_lookup(parent_name);
2822 WARN(1, "parent clk %s of %s must be registered first\n",
2824 return ERR_PTR(-EINVAL);
2827 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2829 return ERR_CAST(pll);
2831 val = pll_readl_base(pll);
2832 val &= ~PLLSS_REF_SRC_SEL_MASK;
2833 pll_writel_base(val, pll);
2835 parent_rate = clk_get_rate(parent);
2837 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2839 if (pll_params->adjust_vco)
2840 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2843 /* initialize PLL to minimum rate */
2845 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
2846 cfg.n = cfg.m * pll_params->vco_min / parent_rate;
2848 for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++)
2852 return ERR_PTR(-EINVAL);
2855 cfg.p = pll_params->pdiv_tohw[i-1].hw_val;
2857 _update_pll_mnp(pll, &cfg);
2859 pll_writel_misc(PLLSS_MISC_DEFAULT, pll);
2861 val = pll_readl_base(pll);
2862 if (val & PLL_BASE_ENABLE) {
2863 if (val & BIT(pll_params->iddq_bit_idx)) {
2864 WARN(1, "%s is on but IDDQ set\n", name);
2866 return ERR_PTR(-EINVAL);
2869 val |= BIT(pll_params->iddq_bit_idx);
2871 val &= ~PLLSS_LOCK_OVERRIDE;
2872 pll_writel_base(val, pll);
2874 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2875 &tegra_clk_pll_ops);
2883 struct clk *tegra_clk_register_pllmb(const char *name, const char *parent_name,
2884 void __iomem *clk_base, void __iomem *pmc,
2885 unsigned long flags,
2886 struct tegra_clk_pll_params *pll_params,
2889 struct tegra_clk_pll *pll;
2890 struct clk *clk, *parent;
2891 unsigned long parent_rate;
2893 if (!pll_params->pdiv_tohw)
2894 return ERR_PTR(-EINVAL);
2896 parent = __clk_lookup(parent_name);
2898 WARN(1, "parent clk %s of %s must be registered first\n",
2900 return ERR_PTR(-EINVAL);
2903 parent_rate = clk_get_rate(parent);
2905 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2907 if (pll_params->adjust_vco)
2908 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2911 pll_params->flags |= TEGRA_PLL_BYPASS;
2912 pll_params->flags |= TEGRA_PLLMB;
2913 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2915 return ERR_CAST(pll);
2917 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2918 &tegra_clk_pll_ops);
2925 struct clk *tegra_clk_register_pllu_tegra210(const char *name,
2926 const char *parent_name, void __iomem *clk_base,
2927 unsigned long flags, struct tegra_clk_pll_params *pll_params,
2930 struct tegra_clk_pll *pll;
2933 pll_params->flags |= TEGRA_PLLU;
2935 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2937 return ERR_CAST(pll);
2939 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2940 &tegra_clk_pllu_tegra210_ops);