1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
6 #include <linux/clk-provider.h>
7 #include <linux/slab.h>
9 #include <linux/delay.h>
10 #include <linux/err.h>
12 #include <soc/tegra/fuse.h>
16 static DEFINE_SPINLOCK(periph_ref_lock);
18 /* Macros to assist peripheral gate clock */
19 #define read_enb(gate) \
20 readl_relaxed(gate->clk_base + (gate->regs->enb_reg))
21 #define write_enb_set(val, gate) \
22 writel_relaxed(val, gate->clk_base + (gate->regs->enb_set_reg))
23 #define write_enb_clr(val, gate) \
24 writel_relaxed(val, gate->clk_base + (gate->regs->enb_clr_reg))
26 #define read_rst(gate) \
27 readl_relaxed(gate->clk_base + (gate->regs->rst_reg))
28 #define write_rst_clr(val, gate) \
29 writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg))
31 #define periph_clk_to_bit(gate) (1 << (gate->clk_num % 32))
33 #define LVL2_CLK_GATE_OVRE 0x554
35 /* Peripheral gate clock ops */
36 static int clk_periph_is_enabled(struct clk_hw *hw)
38 struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
41 if (!(read_enb(gate) & periph_clk_to_bit(gate)))
44 if (!(gate->flags & TEGRA_PERIPH_NO_RESET))
45 if (read_rst(gate) & periph_clk_to_bit(gate))
51 static void clk_periph_enable_locked(struct clk_hw *hw)
53 struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
55 write_enb_set(periph_clk_to_bit(gate), gate);
58 if (!(gate->flags & TEGRA_PERIPH_NO_RESET) &&
59 !(gate->flags & TEGRA_PERIPH_MANUAL_RESET)) {
60 if (read_rst(gate) & periph_clk_to_bit(gate)) {
61 udelay(5); /* reset propogation delay */
62 write_rst_clr(periph_clk_to_bit(gate), gate);
66 if (gate->flags & TEGRA_PERIPH_WAR_1005168) {
67 writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE);
68 writel_relaxed(BIT(22), gate->clk_base + LVL2_CLK_GATE_OVRE);
70 writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE);
74 static void clk_periph_disable_locked(struct clk_hw *hw)
76 struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
79 * If peripheral is in the APB bus then read the APB bus to
80 * flush the write operation in apb bus. This will avoid the
81 * peripheral access after disabling clock
83 if (gate->flags & TEGRA_PERIPH_ON_APB)
86 write_enb_clr(periph_clk_to_bit(gate), gate);
89 static int clk_periph_enable(struct clk_hw *hw)
91 struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
92 unsigned long flags = 0;
94 spin_lock_irqsave(&periph_ref_lock, flags);
96 if (!gate->enable_refcnt[gate->clk_num]++)
97 clk_periph_enable_locked(hw);
99 spin_unlock_irqrestore(&periph_ref_lock, flags);
104 static void clk_periph_disable(struct clk_hw *hw)
106 struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
107 unsigned long flags = 0;
109 spin_lock_irqsave(&periph_ref_lock, flags);
111 WARN_ON(!gate->enable_refcnt[gate->clk_num]);
113 if (--gate->enable_refcnt[gate->clk_num] == 0)
114 clk_periph_disable_locked(hw);
116 spin_unlock_irqrestore(&periph_ref_lock, flags);
119 static void clk_periph_disable_unused(struct clk_hw *hw)
121 struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
122 unsigned long flags = 0;
124 spin_lock_irqsave(&periph_ref_lock, flags);
127 * Some clocks are duplicated and some of them are marked as critical,
128 * like fuse and fuse_burn for example, thus the enable_refcnt will
129 * be non-zero here if the "unused" duplicate is disabled by CCF.
131 if (!gate->enable_refcnt[gate->clk_num])
132 clk_periph_disable_locked(hw);
134 spin_unlock_irqrestore(&periph_ref_lock, flags);
137 const struct clk_ops tegra_clk_periph_gate_ops = {
138 .is_enabled = clk_periph_is_enabled,
139 .enable = clk_periph_enable,
140 .disable = clk_periph_disable,
141 .disable_unused = clk_periph_disable_unused,
144 struct clk *tegra_clk_register_periph_gate(const char *name,
145 const char *parent_name, u8 gate_flags, void __iomem *clk_base,
146 unsigned long flags, int clk_num, int *enable_refcnt)
148 struct tegra_clk_periph_gate *gate;
150 struct clk_init_data init;
151 const struct tegra_clk_periph_regs *pregs;
153 pregs = get_reg_bank(clk_num);
155 return ERR_PTR(-EINVAL);
157 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
159 pr_err("%s: could not allocate periph gate clk\n", __func__);
160 return ERR_PTR(-ENOMEM);
165 init.parent_names = parent_name ? &parent_name : NULL;
166 init.num_parents = parent_name ? 1 : 0;
167 init.ops = &tegra_clk_periph_gate_ops;
169 gate->magic = TEGRA_CLK_PERIPH_GATE_MAGIC;
170 gate->clk_base = clk_base;
171 gate->clk_num = clk_num;
172 gate->flags = gate_flags;
173 gate->enable_refcnt = enable_refcnt;
176 /* Data in .init is copied by clk_register(), so stack variable OK */
177 gate->hw.init = &init;
179 clk = clk_register(NULL, &gate->hw);