1 /* SPDX-License-Identifier: GPL-2.0 */
3 * This header provides IDs for clocks common between several Tegra SoCs
5 #ifndef _TEGRA_CLK_ID_H
6 #define _TEGRA_CLK_ID_H
49 tegra_clk_clk_out_1_mux,
51 tegra_clk_clk_out_2_mux,
53 tegra_clk_clk_out_3_mux,
99 tegra_clk_hda2codec_2x,
100 tegra_clk_hda2codec_2x_8,
103 tegra_clk_hdmi_audio,
152 tegra_clk_pll_a_out0,
158 tegra_clk_pll_c4_out0,
159 tegra_clk_pll_c4_out1,
160 tegra_clk_pll_c4_out2,
161 tegra_clk_pll_c4_out3,
162 tegra_clk_pll_c_out1,
165 tegra_clk_pll_d2_out0,
166 tegra_clk_pll_d_out0,
168 tegra_clk_pll_e_out0,
171 tegra_clk_pll_m_out1,
174 tegra_clk_pll_p_out1,
175 tegra_clk_pll_p_out2,
176 tegra_clk_pll_p_out2_int,
177 tegra_clk_pll_p_out3,
178 tegra_clk_pll_p_out4,
179 tegra_clk_pll_p_out4_cpu,
180 tegra_clk_pll_p_out5,
181 tegra_clk_pll_p_out_hsio,
182 tegra_clk_pll_p_out_xusb,
183 tegra_clk_pll_p_out_cpu,
184 tegra_clk_pll_p_out_adsp,
186 tegra_clk_pll_re_out,
187 tegra_clk_pll_re_vco,
190 tegra_clk_pll_u_out1,
191 tegra_clk_pll_u_out2,
193 tegra_clk_pll_u_480m,
197 tegra_clk_pll_x_out0,
205 tegra_clk_sata_oob_8,
223 tegra_clk_sdmmc_legacy,
239 tegra_clk_soc_therm_8,
247 tegra_clk_spdif_in_8,
248 tegra_clk_spdif_in_sync,
271 tegra_clk_usb2_hsic_trk,
287 tegra_clk_vimclk_sync,
289 tegra_clk_vi_sensor_8,
290 tegra_clk_vi_sensor_9,
291 tegra_clk_vi_sensor2,
292 tegra_clk_vi_sensor2_8,
294 tegra_clk_xusb_dev_src,
295 tegra_clk_xusb_dev_src_8,
296 tegra_clk_xusb_falcon_src,
297 tegra_clk_xusb_falcon_src_8,
298 tegra_clk_xusb_fs_src,
301 tegra_clk_xusb_host_src,
302 tegra_clk_xusb_host_src_8,
303 tegra_clk_xusb_hs_src,
304 tegra_clk_xusb_hs_src_4,
306 tegra_clk_xusb_ss_src,
307 tegra_clk_xusb_ss_src_8,
308 tegra_clk_xusb_ss_div2,
309 tegra_clk_xusb_ssp_src,
317 tegra_clk_dmic1_sync_clk,
318 tegra_clk_dmic2_sync_clk,
319 tegra_clk_dmic3_sync_clk,
320 tegra_clk_dmic1_sync_clk_mux,
321 tegra_clk_dmic2_sync_clk_mux,
322 tegra_clk_dmic3_sync_clk_mux,
325 tegra_clk_pll_a_out_adsp,
326 tegra_clk_pll_a_out0_out_adsp,
332 #endif /* _TEGRA_CLK_ID_H */