2 * drivers/clk/tegra/clk-emc.c
4 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
7 * Mikko Perttunen <mperttunen@nvidia.com>
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/clk-provider.h>
20 #include <linux/clk.h>
21 #include <linux/clkdev.h>
22 #include <linux/delay.h>
23 #include <linux/module.h>
24 #include <linux/of_address.h>
25 #include <linux/of_platform.h>
26 #include <linux/platform_device.h>
27 #include <linux/sort.h>
28 #include <linux/string.h>
30 #include <soc/tegra/fuse.h>
31 #include <soc/tegra/emc.h>
35 #define CLK_SOURCE_EMC 0x19c
37 #define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_SHIFT 0
38 #define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_MASK 0xff
39 #define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR(x) (((x) & CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_MASK) << \
40 CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_SHIFT)
42 #define CLK_SOURCE_EMC_EMC_2X_CLK_SRC_SHIFT 29
43 #define CLK_SOURCE_EMC_EMC_2X_CLK_SRC_MASK 0x7
44 #define CLK_SOURCE_EMC_EMC_2X_CLK_SRC(x) (((x) & CLK_SOURCE_EMC_EMC_2X_CLK_SRC_MASK) << \
45 CLK_SOURCE_EMC_EMC_2X_CLK_SRC_SHIFT)
47 static const char * const emc_parent_clk_names[] = {
48 "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud",
49 "pll_c2", "pll_c3", "pll_c_ud"
53 * List of clock sources for various parents the EMC clock can have.
54 * When we change the timing to a timing with a parent that has the same
55 * clock source as the current parent, we must first change to a backup
56 * timing that has a different clock source.
59 #define EMC_SRC_PLL_M 0
60 #define EMC_SRC_PLL_C 1
61 #define EMC_SRC_PLL_P 2
62 #define EMC_SRC_CLK_M 3
63 #define EMC_SRC_PLL_C2 4
64 #define EMC_SRC_PLL_C3 5
66 static const char emc_parent_clk_sources[] = {
67 EMC_SRC_PLL_M, EMC_SRC_PLL_C, EMC_SRC_PLL_P, EMC_SRC_CLK_M,
68 EMC_SRC_PLL_M, EMC_SRC_PLL_C2, EMC_SRC_PLL_C3, EMC_SRC_PLL_C
72 unsigned long rate, parent_rate;
78 struct tegra_clk_emc {
80 void __iomem *clk_regs;
81 struct clk *prev_parent;
84 struct device_node *emc_node;
85 struct tegra_emc *emc;
88 struct emc_timing *timings;
92 /* Common clock framework callback implementations */
94 static unsigned long emc_recalc_rate(struct clk_hw *hw,
95 unsigned long parent_rate)
97 struct tegra_clk_emc *tegra;
100 tegra = container_of(hw, struct tegra_clk_emc, hw);
103 * CCF wrongly assumes that the parent won't change during set_rate,
104 * so get the parent rate explicitly.
106 parent_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
108 val = readl(tegra->clk_regs + CLK_SOURCE_EMC);
109 div = val & CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_MASK;
111 return parent_rate / (div + 2) * 2;
115 * Rounds up unless no higher rate exists, in which case down. This way is
116 * safer since things have EMC rate floors. Also don't touch parent_rate
117 * since we don't want the CCF to play with our parent clocks.
119 static int emc_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
121 struct tegra_clk_emc *tegra;
122 u8 ram_code = tegra_read_ram_code();
123 struct emc_timing *timing = NULL;
126 tegra = container_of(hw, struct tegra_clk_emc, hw);
128 for (i = 0; i < tegra->num_timings; i++) {
129 if (tegra->timings[i].ram_code != ram_code)
132 timing = tegra->timings + i;
134 if (timing->rate > req->max_rate) {
136 req->rate = tegra->timings[i - 1].rate;
140 if (timing->rate < req->min_rate)
143 if (timing->rate >= req->rate) {
144 req->rate = timing->rate;
150 req->rate = timing->rate;
154 req->rate = clk_hw_get_rate(hw);
158 static u8 emc_get_parent(struct clk_hw *hw)
160 struct tegra_clk_emc *tegra;
163 tegra = container_of(hw, struct tegra_clk_emc, hw);
165 val = readl(tegra->clk_regs + CLK_SOURCE_EMC);
167 return (val >> CLK_SOURCE_EMC_EMC_2X_CLK_SRC_SHIFT)
168 & CLK_SOURCE_EMC_EMC_2X_CLK_SRC_MASK;
171 static struct tegra_emc *emc_ensure_emc_driver(struct tegra_clk_emc *tegra)
173 struct platform_device *pdev;
178 if (!tegra->emc_node)
181 pdev = of_find_device_by_node(tegra->emc_node);
183 pr_err("%s: could not get external memory controller\n",
188 of_node_put(tegra->emc_node);
189 tegra->emc_node = NULL;
191 tegra->emc = platform_get_drvdata(pdev);
193 put_device(&pdev->dev);
194 pr_err("%s: cannot find EMC driver\n", __func__);
201 static int emc_set_timing(struct tegra_clk_emc *tegra,
202 struct emc_timing *timing)
207 unsigned long flags = 0;
208 struct tegra_emc *emc = emc_ensure_emc_driver(tegra);
213 pr_debug("going to rate %ld prate %ld p %s\n", timing->rate,
214 timing->parent_rate, __clk_get_name(timing->parent));
216 if (emc_get_parent(&tegra->hw) == timing->parent_index &&
217 clk_get_rate(timing->parent) != timing->parent_rate) {
222 tegra->changing_timing = true;
224 err = clk_set_rate(timing->parent, timing->parent_rate);
226 pr_err("cannot change parent %s rate to %ld: %d\n",
227 __clk_get_name(timing->parent), timing->parent_rate,
233 err = clk_prepare_enable(timing->parent);
235 pr_err("cannot enable parent clock: %d\n", err);
239 div = timing->parent_rate / (timing->rate / 2) - 2;
241 err = tegra_emc_prepare_timing_change(emc, timing->rate);
245 spin_lock_irqsave(tegra->lock, flags);
247 car_value = readl(tegra->clk_regs + CLK_SOURCE_EMC);
249 car_value &= ~CLK_SOURCE_EMC_EMC_2X_CLK_SRC(~0);
250 car_value |= CLK_SOURCE_EMC_EMC_2X_CLK_SRC(timing->parent_index);
252 car_value &= ~CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR(~0);
253 car_value |= CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR(div);
255 writel(car_value, tegra->clk_regs + CLK_SOURCE_EMC);
257 spin_unlock_irqrestore(tegra->lock, flags);
259 tegra_emc_complete_timing_change(emc, timing->rate);
261 clk_hw_reparent(&tegra->hw, __clk_get_hw(timing->parent));
262 clk_disable_unprepare(tegra->prev_parent);
264 tegra->prev_parent = timing->parent;
265 tegra->changing_timing = false;
271 * Get backup timing to use as an intermediate step when a change between
272 * two timings with the same clock source has been requested. First try to
273 * find a timing with a higher clock rate to avoid a rate below any set rate
274 * floors. If that is not possible, find a lower rate.
276 static struct emc_timing *get_backup_timing(struct tegra_clk_emc *tegra,
280 u32 ram_code = tegra_read_ram_code();
281 struct emc_timing *timing;
283 for (i = timing_index+1; i < tegra->num_timings; i++) {
284 timing = tegra->timings + i;
285 if (timing->ram_code != ram_code)
288 if (emc_parent_clk_sources[timing->parent_index] !=
289 emc_parent_clk_sources[
290 tegra->timings[timing_index].parent_index])
294 for (i = timing_index-1; i >= 0; --i) {
295 timing = tegra->timings + i;
296 if (timing->ram_code != ram_code)
299 if (emc_parent_clk_sources[timing->parent_index] !=
300 emc_parent_clk_sources[
301 tegra->timings[timing_index].parent_index])
308 static int emc_set_rate(struct clk_hw *hw, unsigned long rate,
309 unsigned long parent_rate)
311 struct tegra_clk_emc *tegra;
312 struct emc_timing *timing = NULL;
314 u32 ram_code = tegra_read_ram_code();
316 tegra = container_of(hw, struct tegra_clk_emc, hw);
318 if (clk_hw_get_rate(hw) == rate)
322 * When emc_set_timing changes the parent rate, CCF will propagate
323 * that downward to us, so ignore any set_rate calls while a rate
324 * change is already going on.
326 if (tegra->changing_timing)
329 for (i = 0; i < tegra->num_timings; i++) {
330 if (tegra->timings[i].rate == rate &&
331 tegra->timings[i].ram_code == ram_code) {
332 timing = tegra->timings + i;
338 pr_err("cannot switch to rate %ld without emc table\n", rate);
342 if (emc_parent_clk_sources[emc_get_parent(hw)] ==
343 emc_parent_clk_sources[timing->parent_index] &&
344 clk_get_rate(timing->parent) != timing->parent_rate) {
346 * Parent clock source not changed but parent rate has changed,
347 * need to temporarily switch to another parent
350 struct emc_timing *backup_timing;
352 backup_timing = get_backup_timing(tegra, i);
353 if (!backup_timing) {
354 pr_err("cannot find backup timing\n");
358 pr_debug("using %ld as backup rate when going to %ld\n",
359 backup_timing->rate, rate);
361 err = emc_set_timing(tegra, backup_timing);
363 pr_err("cannot set backup timing: %d\n", err);
368 return emc_set_timing(tegra, timing);
371 /* Initialization and deinitialization */
373 static int load_one_timing_from_dt(struct tegra_clk_emc *tegra,
374 struct emc_timing *timing,
375 struct device_node *node)
380 err = of_property_read_u32(node, "clock-frequency", &tmp);
382 pr_err("timing %pOF: failed to read rate\n", node);
388 err = of_property_read_u32(node, "nvidia,parent-clock-frequency", &tmp);
390 pr_err("timing %pOF: failed to read parent rate\n", node);
394 timing->parent_rate = tmp;
396 timing->parent = of_clk_get_by_name(node, "emc-parent");
397 if (IS_ERR(timing->parent)) {
398 pr_err("timing %pOF: failed to get parent clock\n", node);
399 return PTR_ERR(timing->parent);
402 timing->parent_index = 0xff;
403 for (i = 0; i < ARRAY_SIZE(emc_parent_clk_names); i++) {
404 if (!strcmp(emc_parent_clk_names[i],
405 __clk_get_name(timing->parent))) {
406 timing->parent_index = i;
410 if (timing->parent_index == 0xff) {
411 pr_err("timing %pOF: %s is not a valid parent\n",
412 node, __clk_get_name(timing->parent));
413 clk_put(timing->parent);
420 static int cmp_timings(const void *_a, const void *_b)
422 const struct emc_timing *a = _a;
423 const struct emc_timing *b = _b;
425 if (a->rate < b->rate)
427 else if (a->rate == b->rate)
433 static int load_timings_from_dt(struct tegra_clk_emc *tegra,
434 struct device_node *node,
437 struct device_node *child;
438 int child_count = of_get_child_count(node);
441 tegra->timings = kcalloc(child_count, sizeof(struct emc_timing),
446 tegra->num_timings = child_count;
448 for_each_child_of_node(node, child) {
449 struct emc_timing *timing = tegra->timings + (i++);
451 err = load_one_timing_from_dt(tegra, timing, child);
457 timing->ram_code = ram_code;
460 sort(tegra->timings, tegra->num_timings, sizeof(struct emc_timing),
466 static const struct clk_ops tegra_clk_emc_ops = {
467 .recalc_rate = emc_recalc_rate,
468 .determine_rate = emc_determine_rate,
469 .set_rate = emc_set_rate,
470 .get_parent = emc_get_parent,
473 struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np,
476 struct tegra_clk_emc *tegra;
477 struct clk_init_data init;
478 struct device_node *node;
483 tegra = kcalloc(1, sizeof(*tegra), GFP_KERNEL);
485 return ERR_PTR(-ENOMEM);
487 tegra->clk_regs = base;
490 tegra->num_timings = 0;
492 for_each_child_of_node(np, node) {
493 err = of_property_read_u32(node, "nvidia,ram-code",
499 * Store timings for all ram codes as we cannot read the
500 * fuses until the apbmisc driver is loaded.
502 err = load_timings_from_dt(tegra, node, node_ram_code);
509 if (tegra->num_timings == 0)
510 pr_warn("%s: no memory timings registered\n", __func__);
512 tegra->emc_node = of_parse_phandle(np,
513 "nvidia,external-memory-controller", 0);
514 if (!tegra->emc_node)
515 pr_warn("%s: couldn't find node for EMC driver\n", __func__);
518 init.ops = &tegra_clk_emc_ops;
519 init.flags = CLK_IS_CRITICAL;
520 init.parent_names = emc_parent_clk_names;
521 init.num_parents = ARRAY_SIZE(emc_parent_clk_names);
523 tegra->hw.init = &init;
525 clk = clk_register(NULL, &tegra->hw);
529 tegra->prev_parent = clk_hw_get_parent_by_index(
530 &tegra->hw, emc_get_parent(&tegra->hw))->clk;
531 tegra->changing_timing = false;
533 /* Allow debugging tools to see the EMC clock */
534 clk_register_clkdev(clk, "emc", "tegra-clk-debug");
536 clk_prepare_enable(clk);