2 * Copyright (C) 2016 Maxime Ripard
3 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
11 #include <linux/clk-provider.h>
18 unsigned long n, min_n, max_n;
19 unsigned long m, min_m, max_m;
22 static void ccu_nm_find_best(unsigned long parent, unsigned long rate,
25 unsigned long best_rate = 0;
26 unsigned long best_n = 0, best_m = 0;
29 for (_n = nm->min_n; _n <= nm->max_n; _n++) {
30 for (_m = nm->min_m; _m <= nm->max_m; _m++) {
31 unsigned long tmp_rate = parent * _n / _m;
36 if ((rate - tmp_rate) < (rate - best_rate)) {
48 static void ccu_nm_disable(struct clk_hw *hw)
50 struct ccu_nm *nm = hw_to_ccu_nm(hw);
52 return ccu_gate_helper_disable(&nm->common, nm->enable);
55 static int ccu_nm_enable(struct clk_hw *hw)
57 struct ccu_nm *nm = hw_to_ccu_nm(hw);
59 return ccu_gate_helper_enable(&nm->common, nm->enable);
62 static int ccu_nm_is_enabled(struct clk_hw *hw)
64 struct ccu_nm *nm = hw_to_ccu_nm(hw);
66 return ccu_gate_helper_is_enabled(&nm->common, nm->enable);
69 static unsigned long ccu_nm_recalc_rate(struct clk_hw *hw,
70 unsigned long parent_rate)
72 struct ccu_nm *nm = hw_to_ccu_nm(hw);
76 if (ccu_frac_helper_is_enabled(&nm->common, &nm->frac))
77 return ccu_frac_helper_read_rate(&nm->common, &nm->frac);
79 reg = readl(nm->common.base + nm->common.reg);
81 n = reg >> nm->n.shift;
82 n &= (1 << nm->n.width) - 1;
87 m = reg >> nm->m.shift;
88 m &= (1 << nm->m.width) - 1;
93 return parent_rate * n / m;
96 static long ccu_nm_round_rate(struct clk_hw *hw, unsigned long rate,
97 unsigned long *parent_rate)
99 struct ccu_nm *nm = hw_to_ccu_nm(hw);
102 if (ccu_frac_helper_has_rate(&nm->common, &nm->frac, rate))
105 _nm.min_n = nm->n.min ?: 1;
106 _nm.max_n = nm->n.max ?: 1 << nm->n.width;
108 _nm.max_m = nm->m.max ?: 1 << nm->m.width;
110 ccu_nm_find_best(*parent_rate, rate, &_nm);
112 return *parent_rate * _nm.n / _nm.m;
115 static int ccu_nm_set_rate(struct clk_hw *hw, unsigned long rate,
116 unsigned long parent_rate)
118 struct ccu_nm *nm = hw_to_ccu_nm(hw);
123 if (ccu_frac_helper_has_rate(&nm->common, &nm->frac, rate)) {
124 spin_lock_irqsave(nm->common.lock, flags);
126 /* most SoCs require M to be 0 if fractional mode is used */
127 reg = readl(nm->common.base + nm->common.reg);
128 reg &= ~GENMASK(nm->m.width + nm->m.shift - 1, nm->m.shift);
129 writel(reg, nm->common.base + nm->common.reg);
131 spin_unlock_irqrestore(nm->common.lock, flags);
133 ccu_frac_helper_enable(&nm->common, &nm->frac);
135 return ccu_frac_helper_set_rate(&nm->common, &nm->frac,
138 ccu_frac_helper_disable(&nm->common, &nm->frac);
141 _nm.min_n = nm->n.min ?: 1;
142 _nm.max_n = nm->n.max ?: 1 << nm->n.width;
144 _nm.max_m = nm->m.max ?: 1 << nm->m.width;
146 ccu_nm_find_best(parent_rate, rate, &_nm);
148 spin_lock_irqsave(nm->common.lock, flags);
150 reg = readl(nm->common.base + nm->common.reg);
151 reg &= ~GENMASK(nm->n.width + nm->n.shift - 1, nm->n.shift);
152 reg &= ~GENMASK(nm->m.width + nm->m.shift - 1, nm->m.shift);
154 reg |= (_nm.n - nm->n.offset) << nm->n.shift;
155 reg |= (_nm.m - nm->m.offset) << nm->m.shift;
156 writel(reg, nm->common.base + nm->common.reg);
158 spin_unlock_irqrestore(nm->common.lock, flags);
160 ccu_helper_wait_for_lock(&nm->common, nm->lock);
165 const struct clk_ops ccu_nm_ops = {
166 .disable = ccu_nm_disable,
167 .enable = ccu_nm_enable,
168 .is_enabled = ccu_nm_is_enabled,
170 .recalc_rate = ccu_nm_recalc_rate,
171 .round_rate = ccu_nm_round_rate,
172 .set_rate = ccu_nm_set_rate,