GNU Linux-libre 4.19.314-gnu1
[releases.git] / drivers / clk / sunxi-ng / ccu-sun8i-v3s.c
1 /*
2  * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz>
3  *
4  * Based on ccu-sun8i-h3.c, which is:
5  * Copyright (c) 2016 Maxime Ripard. All rights reserved.
6  *
7  * This software is licensed under the terms of the GNU General Public
8  * License version 2, as published by the Free Software Foundation, and
9  * may be copied, distributed, and modified under those terms.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  */
16
17 #include <linux/clk-provider.h>
18 #include <linux/of_address.h>
19
20 #include "ccu_common.h"
21 #include "ccu_reset.h"
22
23 #include "ccu_div.h"
24 #include "ccu_gate.h"
25 #include "ccu_mp.h"
26 #include "ccu_mult.h"
27 #include "ccu_nk.h"
28 #include "ccu_nkm.h"
29 #include "ccu_nkmp.h"
30 #include "ccu_nm.h"
31 #include "ccu_phase.h"
32
33 #include "ccu-sun8i-v3s.h"
34
35 static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu",
36                                      "osc24M", 0x000,
37                                      8, 5,      /* N */
38                                      4, 2,      /* K */
39                                      0, 2,      /* M */
40                                      16, 2,     /* P */
41                                      BIT(31),   /* gate */
42                                      BIT(28),   /* lock */
43                                      0);
44
45 /*
46  * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
47  * the base (2x, 4x and 8x), and one variable divider (the one true
48  * pll audio).
49  *
50  * We don't have any need for the variable divider for now, so we just
51  * hardcode it to match with the clock names
52  */
53 #define SUN8I_V3S_PLL_AUDIO_REG 0x008
54
55 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
56                                    "osc24M", 0x008,
57                                    8, 7,        /* N */
58                                    0, 5,        /* M */
59                                    BIT(31),     /* gate */
60                                    BIT(28),     /* lock */
61                                    0);
62
63 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
64                                         "osc24M", 0x0010,
65                                         8, 7,           /* N */
66                                         0, 4,           /* M */
67                                         BIT(24),        /* frac enable */
68                                         BIT(25),        /* frac select */
69                                         270000000,      /* frac rate 0 */
70                                         297000000,      /* frac rate 1 */
71                                         BIT(31),        /* gate */
72                                         BIT(28),        /* lock */
73                                         0);
74
75 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
76                                         "osc24M", 0x0018,
77                                         8, 7,           /* N */
78                                         0, 4,           /* M */
79                                         BIT(24),        /* frac enable */
80                                         BIT(25),        /* frac select */
81                                         270000000,      /* frac rate 0 */
82                                         297000000,      /* frac rate 1 */
83                                         BIT(31),        /* gate */
84                                         BIT(28),        /* lock */
85                                         0);
86
87 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
88                                     "osc24M", 0x020,
89                                     8, 5,       /* N */
90                                     4, 2,       /* K */
91                                     0, 2,       /* M */
92                                     BIT(31),    /* gate */
93                                     BIT(28),    /* lock */
94                                     0);
95
96 static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph0_clk, "pll-periph0",
97                                            "osc24M", 0x028,
98                                            8, 5,        /* N */
99                                            4, 2,        /* K */
100                                            BIT(31),     /* gate */
101                                            BIT(28),     /* lock */
102                                            2,           /* post-div */
103                                            0);
104
105 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_isp_clk, "pll-isp",
106                                         "osc24M", 0x002c,
107                                         8, 7,           /* N */
108                                         0, 4,           /* M */
109                                         BIT(24),        /* frac enable */
110                                         BIT(25),        /* frac select */
111                                         270000000,      /* frac rate 0 */
112                                         297000000,      /* frac rate 1 */
113                                         BIT(31),        /* gate */
114                                         BIT(28),        /* lock */
115                                         0);
116
117 static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph1_clk, "pll-periph1",
118                                            "osc24M", 0x044,
119                                            8, 5,        /* N */
120                                            4, 2,        /* K */
121                                            BIT(31),     /* gate */
122                                            BIT(28),     /* lock */
123                                            2,           /* post-div */
124                                            0);
125
126 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1",
127                                    "osc24M", 0x04c,
128                                    8, 7,        /* N */
129                                    0, 2,        /* M */
130                                    BIT(31),     /* gate */
131                                    BIT(28),     /* lock */
132                                    0);
133
134 static const char * const cpu_parents[] = { "osc32k", "osc24M",
135                                              "pll-cpu", "pll-cpu" };
136 static SUNXI_CCU_MUX(cpu_clk, "cpu", cpu_parents,
137                      0x050, 16, 2, CLK_IS_CRITICAL);
138
139 static SUNXI_CCU_M(axi_clk, "axi", "cpu", 0x050, 0, 2, 0);
140
141 static const char * const ahb1_parents[] = { "osc32k", "osc24M",
142                                              "axi", "pll-periph0" };
143 static const struct ccu_mux_var_prediv ahb1_predivs[] = {
144         { .index = 3, .shift = 6, .width = 2 },
145 };
146 static struct ccu_div ahb1_clk = {
147         .div            = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
148
149         .mux            = {
150                 .shift  = 12,
151                 .width  = 2,
152
153                 .var_predivs    = ahb1_predivs,
154                 .n_var_predivs  = ARRAY_SIZE(ahb1_predivs),
155         },
156
157         .common         = {
158                 .reg            = 0x054,
159                 .features       = CCU_FEATURE_VARIABLE_PREDIV,
160                 .hw.init        = CLK_HW_INIT_PARENTS("ahb1",
161                                                       ahb1_parents,
162                                                       &ccu_div_ops,
163                                                       0),
164         },
165 };
166
167 static struct clk_div_table apb1_div_table[] = {
168         { .val = 0, .div = 2 },
169         { .val = 1, .div = 2 },
170         { .val = 2, .div = 4 },
171         { .val = 3, .div = 8 },
172         { /* Sentinel */ },
173 };
174 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
175                            0x054, 8, 2, apb1_div_table, 0);
176
177 static const char * const apb2_parents[] = { "osc32k", "osc24M",
178                                              "pll-periph0", "pll-periph0" };
179 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
180                              0, 5,      /* M */
181                              16, 2,     /* P */
182                              24, 2,     /* mux */
183                              0);
184
185 static const char * const ahb2_parents[] = { "ahb1", "pll-periph0" };
186 static const struct ccu_mux_fixed_prediv ahb2_fixed_predivs[] = {
187         { .index = 1, .div = 2 },
188 };
189 static struct ccu_mux ahb2_clk = {
190         .mux            = {
191                 .shift  = 0,
192                 .width  = 1,
193                 .fixed_predivs  = ahb2_fixed_predivs,
194                 .n_predivs      = ARRAY_SIZE(ahb2_fixed_predivs),
195         },
196
197         .common         = {
198                 .reg            = 0x05c,
199                 .features       = CCU_FEATURE_FIXED_PREDIV,
200                 .hw.init        = CLK_HW_INIT_PARENTS("ahb2",
201                                                       ahb2_parents,
202                                                       &ccu_mux_ops,
203                                                       0),
204         },
205 };
206
207 static SUNXI_CCU_GATE(bus_ce_clk,       "bus-ce",       "ahb1",
208                       0x060, BIT(5), 0);
209 static SUNXI_CCU_GATE(bus_dma_clk,      "bus-dma",      "ahb1",
210                       0x060, BIT(6), 0);
211 static SUNXI_CCU_GATE(bus_mmc0_clk,     "bus-mmc0",     "ahb1",
212                       0x060, BIT(8), 0);
213 static SUNXI_CCU_GATE(bus_mmc1_clk,     "bus-mmc1",     "ahb1",
214                       0x060, BIT(9), 0);
215 static SUNXI_CCU_GATE(bus_mmc2_clk,     "bus-mmc2",     "ahb1",
216                       0x060, BIT(10), 0);
217 static SUNXI_CCU_GATE(bus_dram_clk,     "bus-dram",     "ahb1",
218                       0x060, BIT(14), 0);
219 static SUNXI_CCU_GATE(bus_emac_clk,     "bus-emac",     "ahb2",
220                       0x060, BIT(17), 0);
221 static SUNXI_CCU_GATE(bus_hstimer_clk,  "bus-hstimer",  "ahb1",
222                       0x060, BIT(19), 0);
223 static SUNXI_CCU_GATE(bus_spi0_clk,     "bus-spi0",     "ahb1",
224                       0x060, BIT(20), 0);
225 static SUNXI_CCU_GATE(bus_otg_clk,      "bus-otg",      "ahb1",
226                       0x060, BIT(24), 0);
227 static SUNXI_CCU_GATE(bus_ehci0_clk,    "bus-ehci0",    "ahb1",
228                       0x060, BIT(26), 0);
229 static SUNXI_CCU_GATE(bus_ohci0_clk,    "bus-ohci0",    "ahb1",
230                       0x060, BIT(29), 0);
231
232 static SUNXI_CCU_GATE(bus_ve_clk,       "bus-ve",       "ahb1",
233                       0x064, BIT(0), 0);
234 static SUNXI_CCU_GATE(bus_tcon0_clk,    "bus-tcon0",    "ahb1",
235                       0x064, BIT(4), 0);
236 static SUNXI_CCU_GATE(bus_csi_clk,      "bus-csi",      "ahb1",
237                       0x064, BIT(8), 0);
238 static SUNXI_CCU_GATE(bus_de_clk,       "bus-de",       "ahb1",
239                       0x064, BIT(12), 0);
240
241 static SUNXI_CCU_GATE(bus_codec_clk,    "bus-codec",    "apb1",
242                       0x068, BIT(0), 0);
243 static SUNXI_CCU_GATE(bus_pio_clk,      "bus-pio",      "apb1",
244                       0x068, BIT(5), 0);
245
246 static SUNXI_CCU_GATE(bus_i2c0_clk,     "bus-i2c0",     "apb2",
247                       0x06c, BIT(0), 0);
248 static SUNXI_CCU_GATE(bus_i2c1_clk,     "bus-i2c1",     "apb2",
249                       0x06c, BIT(1), 0);
250 static SUNXI_CCU_GATE(bus_uart0_clk,    "bus-uart0",    "apb2",
251                       0x06c, BIT(16), 0);
252 static SUNXI_CCU_GATE(bus_uart1_clk,    "bus-uart1",    "apb2",
253                       0x06c, BIT(17), 0);
254 static SUNXI_CCU_GATE(bus_uart2_clk,    "bus-uart2",    "apb2",
255                       0x06c, BIT(18), 0);
256
257 static SUNXI_CCU_GATE(bus_ephy_clk,     "bus-ephy",     "ahb1",
258                       0x070, BIT(0), 0);
259 static SUNXI_CCU_GATE(bus_dbg_clk,      "bus-dbg",      "ahb1",
260                       0x070, BIT(7), 0);
261
262 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0",
263                                                      "pll-periph1" };
264 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
265                                   0, 4,         /* M */
266                                   16, 2,        /* P */
267                                   24, 2,        /* mux */
268                                   BIT(31),      /* gate */
269                                   0);
270
271 static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0",
272                        0x088, 20, 3, 0);
273 static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0",
274                        0x088, 8, 3, 0);
275
276 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
277                                   0, 4,         /* M */
278                                   16, 2,        /* P */
279                                   24, 2,        /* mux */
280                                   BIT(31),      /* gate */
281                                   0);
282
283 static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1",
284                        0x08c, 20, 3, 0);
285 static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1",
286                        0x08c, 8, 3, 0);
287
288 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
289                                   0, 4,         /* M */
290                                   16, 2,        /* P */
291                                   24, 2,        /* mux */
292                                   BIT(31),      /* gate */
293                                   0);
294
295 static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2",
296                        0x090, 20, 3, 0);
297 static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2",
298                        0x090, 8, 3, 0);
299
300 static const char * const ce_parents[] = { "osc24M", "pll-periph0", };
301
302 static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0x09c,
303                                   0, 4,         /* M */
304                                   16, 2,        /* P */
305                                   24, 2,        /* mux */
306                                   BIT(31),      /* gate */
307                                   0);
308
309 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
310                                   0, 4,         /* M */
311                                   16, 2,        /* P */
312                                   24, 2,        /* mux */
313                                   BIT(31),      /* gate */
314                                   0);
315
316 static SUNXI_CCU_GATE(usb_phy0_clk,     "usb-phy0",     "osc24M",
317                       0x0cc, BIT(8), 0);
318 static SUNXI_CCU_GATE(usb_ohci0_clk,    "usb-ohci0",    "osc24M",
319                       0x0cc, BIT(16), 0);
320
321 static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1",
322                                              "pll-periph0-2x" };
323 static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents,
324                             0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL);
325
326 static SUNXI_CCU_GATE(dram_ve_clk,      "dram-ve",      "dram",
327                       0x100, BIT(0), 0);
328 static SUNXI_CCU_GATE(dram_csi_clk,     "dram-csi",     "dram",
329                       0x100, BIT(1), 0);
330 static SUNXI_CCU_GATE(dram_ehci_clk,    "dram-ehci",    "dram",
331                       0x100, BIT(17), 0);
332 static SUNXI_CCU_GATE(dram_ohci_clk,    "dram-ohci",    "dram",
333                       0x100, BIT(18), 0);
334
335 static const char * const de_parents[] = { "pll-video", "pll-periph0" };
336 static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
337                                  0x104, 0, 4, 24, 2, BIT(31), 0);
338
339 static const char * const tcon_parents[] = { "pll-video" };
340 static SUNXI_CCU_M_WITH_MUX_GATE(tcon_clk, "tcon", tcon_parents,
341                                  0x118, 0, 4, 24, 3, BIT(31), 0);
342
343 static SUNXI_CCU_GATE(csi_misc_clk,     "csi-misc",     "osc24M",
344                       0x130, BIT(31), 0);
345
346 static const char * const csi_mclk_parents[] = { "osc24M", "pll-video",
347                                                  "pll-periph0", "pll-periph1" };
348 static SUNXI_CCU_M_WITH_MUX_GATE(csi0_mclk_clk, "csi0-mclk", csi_mclk_parents,
349                                  0x130, 0, 5, 8, 3, BIT(15), 0);
350
351 static const char * const csi1_sclk_parents[] = { "pll-video", "pll-isp" };
352 static SUNXI_CCU_M_WITH_MUX_GATE(csi1_sclk_clk, "csi-sclk", csi1_sclk_parents,
353                                  0x134, 16, 4, 24, 3, BIT(31), 0);
354
355 static SUNXI_CCU_M_WITH_MUX_GATE(csi1_mclk_clk, "csi-mclk", csi_mclk_parents,
356                                  0x134, 0, 5, 8, 3, BIT(15), 0);
357
358 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
359                              0x13c, 16, 3, BIT(31), 0);
360
361 static SUNXI_CCU_GATE(ac_dig_clk,       "ac-dig",       "pll-audio",
362                       0x140, BIT(31), CLK_SET_RATE_PARENT);
363 static SUNXI_CCU_GATE(avs_clk,          "avs",          "osc24M",
364                       0x144, BIT(31), 0);
365
366 static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x",
367                                              "pll-ddr" };
368 static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
369                                  0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
370
371 static const char * const mipi_csi_parents[] = { "pll-video", "pll-periph0",
372                                                  "pll-isp" };
373 static SUNXI_CCU_M_WITH_MUX_GATE(mipi_csi_clk, "mipi-csi", mipi_csi_parents,
374                              0x16c, 0, 3, 24, 2, BIT(31), 0);
375
376 static struct ccu_common *sun8i_v3s_ccu_clks[] = {
377         &pll_cpu_clk.common,
378         &pll_audio_base_clk.common,
379         &pll_video_clk.common,
380         &pll_ve_clk.common,
381         &pll_ddr0_clk.common,
382         &pll_periph0_clk.common,
383         &pll_isp_clk.common,
384         &pll_periph1_clk.common,
385         &pll_ddr1_clk.common,
386         &cpu_clk.common,
387         &axi_clk.common,
388         &ahb1_clk.common,
389         &apb1_clk.common,
390         &apb2_clk.common,
391         &ahb2_clk.common,
392         &bus_ce_clk.common,
393         &bus_dma_clk.common,
394         &bus_mmc0_clk.common,
395         &bus_mmc1_clk.common,
396         &bus_mmc2_clk.common,
397         &bus_dram_clk.common,
398         &bus_emac_clk.common,
399         &bus_hstimer_clk.common,
400         &bus_spi0_clk.common,
401         &bus_otg_clk.common,
402         &bus_ehci0_clk.common,
403         &bus_ohci0_clk.common,
404         &bus_ve_clk.common,
405         &bus_tcon0_clk.common,
406         &bus_csi_clk.common,
407         &bus_de_clk.common,
408         &bus_codec_clk.common,
409         &bus_pio_clk.common,
410         &bus_i2c0_clk.common,
411         &bus_i2c1_clk.common,
412         &bus_uart0_clk.common,
413         &bus_uart1_clk.common,
414         &bus_uart2_clk.common,
415         &bus_ephy_clk.common,
416         &bus_dbg_clk.common,
417         &mmc0_clk.common,
418         &mmc0_sample_clk.common,
419         &mmc0_output_clk.common,
420         &mmc1_clk.common,
421         &mmc1_sample_clk.common,
422         &mmc1_output_clk.common,
423         &mmc2_clk.common,
424         &mmc2_sample_clk.common,
425         &mmc2_output_clk.common,
426         &ce_clk.common,
427         &spi0_clk.common,
428         &usb_phy0_clk.common,
429         &usb_ohci0_clk.common,
430         &dram_clk.common,
431         &dram_ve_clk.common,
432         &dram_csi_clk.common,
433         &dram_ohci_clk.common,
434         &dram_ehci_clk.common,
435         &de_clk.common,
436         &tcon_clk.common,
437         &csi_misc_clk.common,
438         &csi0_mclk_clk.common,
439         &csi1_sclk_clk.common,
440         &csi1_mclk_clk.common,
441         &ve_clk.common,
442         &ac_dig_clk.common,
443         &avs_clk.common,
444         &mbus_clk.common,
445         &mipi_csi_clk.common,
446 };
447
448 /* We hardcode the divider to 4 for now */
449 static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
450                         "pll-audio-base", 4, 1, CLK_SET_RATE_PARENT);
451 static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
452                         "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
453 static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
454                         "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
455 static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
456                         "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
457 static CLK_FIXED_FACTOR(pll_periph0_2x_clk, "pll-periph0-2x",
458                         "pll-periph0", 1, 2, 0);
459
460 static struct clk_hw_onecell_data sun8i_v3s_hw_clks = {
461         .hws    = {
462                 [CLK_PLL_CPU]           = &pll_cpu_clk.common.hw,
463                 [CLK_PLL_AUDIO_BASE]    = &pll_audio_base_clk.common.hw,
464                 [CLK_PLL_AUDIO]         = &pll_audio_clk.hw,
465                 [CLK_PLL_AUDIO_2X]      = &pll_audio_2x_clk.hw,
466                 [CLK_PLL_AUDIO_4X]      = &pll_audio_4x_clk.hw,
467                 [CLK_PLL_AUDIO_8X]      = &pll_audio_8x_clk.hw,
468                 [CLK_PLL_VIDEO]         = &pll_video_clk.common.hw,
469                 [CLK_PLL_VE]            = &pll_ve_clk.common.hw,
470                 [CLK_PLL_DDR0]          = &pll_ddr0_clk.common.hw,
471                 [CLK_PLL_PERIPH0]       = &pll_periph0_clk.common.hw,
472                 [CLK_PLL_PERIPH0_2X]    = &pll_periph0_2x_clk.hw,
473                 [CLK_PLL_ISP]           = &pll_isp_clk.common.hw,
474                 [CLK_PLL_PERIPH1]       = &pll_periph1_clk.common.hw,
475                 [CLK_PLL_DDR1]          = &pll_ddr1_clk.common.hw,
476                 [CLK_CPU]               = &cpu_clk.common.hw,
477                 [CLK_AXI]               = &axi_clk.common.hw,
478                 [CLK_AHB1]              = &ahb1_clk.common.hw,
479                 [CLK_APB1]              = &apb1_clk.common.hw,
480                 [CLK_APB2]              = &apb2_clk.common.hw,
481                 [CLK_AHB2]              = &ahb2_clk.common.hw,
482                 [CLK_BUS_CE]            = &bus_ce_clk.common.hw,
483                 [CLK_BUS_DMA]           = &bus_dma_clk.common.hw,
484                 [CLK_BUS_MMC0]          = &bus_mmc0_clk.common.hw,
485                 [CLK_BUS_MMC1]          = &bus_mmc1_clk.common.hw,
486                 [CLK_BUS_MMC2]          = &bus_mmc2_clk.common.hw,
487                 [CLK_BUS_DRAM]          = &bus_dram_clk.common.hw,
488                 [CLK_BUS_EMAC]          = &bus_emac_clk.common.hw,
489                 [CLK_BUS_HSTIMER]       = &bus_hstimer_clk.common.hw,
490                 [CLK_BUS_SPI0]          = &bus_spi0_clk.common.hw,
491                 [CLK_BUS_OTG]           = &bus_otg_clk.common.hw,
492                 [CLK_BUS_EHCI0]         = &bus_ehci0_clk.common.hw,
493                 [CLK_BUS_OHCI0]         = &bus_ohci0_clk.common.hw,
494                 [CLK_BUS_VE]            = &bus_ve_clk.common.hw,
495                 [CLK_BUS_TCON0]         = &bus_tcon0_clk.common.hw,
496                 [CLK_BUS_CSI]           = &bus_csi_clk.common.hw,
497                 [CLK_BUS_DE]            = &bus_de_clk.common.hw,
498                 [CLK_BUS_CODEC]         = &bus_codec_clk.common.hw,
499                 [CLK_BUS_PIO]           = &bus_pio_clk.common.hw,
500                 [CLK_BUS_I2C0]          = &bus_i2c0_clk.common.hw,
501                 [CLK_BUS_I2C1]          = &bus_i2c1_clk.common.hw,
502                 [CLK_BUS_UART0]         = &bus_uart0_clk.common.hw,
503                 [CLK_BUS_UART1]         = &bus_uart1_clk.common.hw,
504                 [CLK_BUS_UART2]         = &bus_uart2_clk.common.hw,
505                 [CLK_BUS_EPHY]          = &bus_ephy_clk.common.hw,
506                 [CLK_BUS_DBG]           = &bus_dbg_clk.common.hw,
507                 [CLK_MMC0]              = &mmc0_clk.common.hw,
508                 [CLK_MMC0_SAMPLE]       = &mmc0_sample_clk.common.hw,
509                 [CLK_MMC0_OUTPUT]       = &mmc0_output_clk.common.hw,
510                 [CLK_MMC1]              = &mmc1_clk.common.hw,
511                 [CLK_MMC1_SAMPLE]       = &mmc1_sample_clk.common.hw,
512                 [CLK_MMC1_OUTPUT]       = &mmc1_output_clk.common.hw,
513                 [CLK_MMC2]              = &mmc2_clk.common.hw,
514                 [CLK_MMC2_SAMPLE]       = &mmc2_sample_clk.common.hw,
515                 [CLK_MMC2_OUTPUT]       = &mmc2_output_clk.common.hw,
516                 [CLK_CE]                = &ce_clk.common.hw,
517                 [CLK_SPI0]              = &spi0_clk.common.hw,
518                 [CLK_USB_PHY0]          = &usb_phy0_clk.common.hw,
519                 [CLK_USB_OHCI0]         = &usb_ohci0_clk.common.hw,
520                 [CLK_DRAM]              = &dram_clk.common.hw,
521                 [CLK_DRAM_VE]           = &dram_ve_clk.common.hw,
522                 [CLK_DRAM_CSI]          = &dram_csi_clk.common.hw,
523                 [CLK_DRAM_EHCI]         = &dram_ehci_clk.common.hw,
524                 [CLK_DRAM_OHCI]         = &dram_ohci_clk.common.hw,
525                 [CLK_DE]                = &de_clk.common.hw,
526                 [CLK_TCON0]             = &tcon_clk.common.hw,
527                 [CLK_CSI_MISC]          = &csi_misc_clk.common.hw,
528                 [CLK_CSI0_MCLK]         = &csi0_mclk_clk.common.hw,
529                 [CLK_CSI1_SCLK]         = &csi1_sclk_clk.common.hw,
530                 [CLK_CSI1_MCLK]         = &csi1_mclk_clk.common.hw,
531                 [CLK_VE]                = &ve_clk.common.hw,
532                 [CLK_AC_DIG]            = &ac_dig_clk.common.hw,
533                 [CLK_AVS]               = &avs_clk.common.hw,
534                 [CLK_MBUS]              = &mbus_clk.common.hw,
535                 [CLK_MIPI_CSI]          = &mipi_csi_clk.common.hw,
536         },
537         .num    = CLK_NUMBER,
538 };
539
540 static struct ccu_reset_map sun8i_v3s_ccu_resets[] = {
541         [RST_USB_PHY0]          =  { 0x0cc, BIT(0) },
542
543         [RST_MBUS]              =  { 0x0fc, BIT(31) },
544
545         [RST_BUS_CE]            =  { 0x2c0, BIT(5) },
546         [RST_BUS_DMA]           =  { 0x2c0, BIT(6) },
547         [RST_BUS_MMC0]          =  { 0x2c0, BIT(8) },
548         [RST_BUS_MMC1]          =  { 0x2c0, BIT(9) },
549         [RST_BUS_MMC2]          =  { 0x2c0, BIT(10) },
550         [RST_BUS_DRAM]          =  { 0x2c0, BIT(14) },
551         [RST_BUS_EMAC]          =  { 0x2c0, BIT(17) },
552         [RST_BUS_HSTIMER]       =  { 0x2c0, BIT(19) },
553         [RST_BUS_SPI0]          =  { 0x2c0, BIT(20) },
554         [RST_BUS_OTG]           =  { 0x2c0, BIT(24) },
555         [RST_BUS_EHCI0]         =  { 0x2c0, BIT(26) },
556         [RST_BUS_OHCI0]         =  { 0x2c0, BIT(29) },
557
558         [RST_BUS_VE]            =  { 0x2c4, BIT(0) },
559         [RST_BUS_TCON0]         =  { 0x2c4, BIT(4) },
560         [RST_BUS_CSI]           =  { 0x2c4, BIT(8) },
561         [RST_BUS_DE]            =  { 0x2c4, BIT(12) },
562         [RST_BUS_DBG]           =  { 0x2c4, BIT(31) },
563
564         [RST_BUS_EPHY]          =  { 0x2c8, BIT(2) },
565
566         [RST_BUS_CODEC]         =  { 0x2d0, BIT(0) },
567
568         [RST_BUS_I2C0]          =  { 0x2d8, BIT(0) },
569         [RST_BUS_I2C1]          =  { 0x2d8, BIT(1) },
570         [RST_BUS_UART0]         =  { 0x2d8, BIT(16) },
571         [RST_BUS_UART1]         =  { 0x2d8, BIT(17) },
572         [RST_BUS_UART2]         =  { 0x2d8, BIT(18) },
573 };
574
575 static const struct sunxi_ccu_desc sun8i_v3s_ccu_desc = {
576         .ccu_clks       = sun8i_v3s_ccu_clks,
577         .num_ccu_clks   = ARRAY_SIZE(sun8i_v3s_ccu_clks),
578
579         .hw_clks        = &sun8i_v3s_hw_clks,
580
581         .resets         = sun8i_v3s_ccu_resets,
582         .num_resets     = ARRAY_SIZE(sun8i_v3s_ccu_resets),
583 };
584
585 static void __init sun8i_v3s_ccu_setup(struct device_node *node)
586 {
587         void __iomem *reg;
588         u32 val;
589
590         reg = of_io_request_and_map(node, 0, of_node_full_name(node));
591         if (IS_ERR(reg)) {
592                 pr_err("%pOF: Could not map the clock registers\n", node);
593                 return;
594         }
595
596         /* Force the PLL-Audio-1x divider to 4 */
597         val = readl(reg + SUN8I_V3S_PLL_AUDIO_REG);
598         val &= ~GENMASK(19, 16);
599         writel(val | (3 << 16), reg + SUN8I_V3S_PLL_AUDIO_REG);
600
601         sunxi_ccu_probe(node, reg, &sun8i_v3s_ccu_desc);
602 }
603 CLK_OF_DECLARE(sun8i_v3s_ccu, "allwinner,sun8i-v3s-ccu",
604                sun8i_v3s_ccu_setup);