drivers/clk/sunxi-ng/ccu-sun8i-h3.c

   1 /*
   2  * Copyright (c) 2016 Maxime Ripard. All rights reserved.
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/clk-provider.h>
  15 #include <linux/of_address.h>
  16
  17 #include "ccu_common.h"
  18 #include "ccu_reset.h"
  19
  20 #include "ccu_div.h"
  21 #include "ccu_gate.h"
  22 #include "ccu_mp.h"
  23 #include "ccu_mult.h"
  24 #include "ccu_nk.h"
  25 #include "ccu_nkm.h"
  26 #include "ccu_nkmp.h"
  27 #include "ccu_nm.h"
  28 #include "ccu_phase.h"
  29 #include "ccu_sdm.h"
  30
  31 #include "ccu-sun8i-h3.h"
  32
  33 static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpux_clk, "pll-cpux",
  34                                      "osc24M", 0x000,
  35                                      8, 5,      /* N */
  36                                      4, 2,      /* K */
  37                                      0, 2,      /* M */
  38                                      16, 2,     /* P */
  39                                      BIT(31),   /* gate */
  40                                      BIT(28),   /* lock */
  41                                      CLK_SET_RATE_UNGATE);
  42
  43 /*
  44  * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
  45  * the base (2x, 4x and 8x), and one variable divider (the one true
  46  * pll audio).
  47  *
  48  * With sigma-delta modulation for fractional-N on the audio PLL,
  49  * we have to use specific dividers. This means the variable divider
  50  * can no longer be used, as the audio codec requests the exact clock
  51  * rates we support through this mechanism. So we now hard code the
  52  * variable divider to 1. This means the clock rates will no longer
  53  * match the clock names.
  54  */
  55 #define SUN8I_H3_PLL_AUDIO_REG  0x008
  56
  57 static struct ccu_sdm_setting pll_audio_sdm_table[] = {
  58         { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
  59         { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
  60 };
  61
  62 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
  63                                        "osc24M", 0x008,
  64                                        8, 7,    /* N */
  65                                        0, 5,    /* M */
  66                                        pll_audio_sdm_table, BIT(24),
  67                                        0x284, BIT(31),
  68                                        BIT(31), /* gate */
  69                                        BIT(28), /* lock */
  70                                        CLK_SET_RATE_UNGATE);
  71
  72 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video_clk, "pll-video",
  73                                             "osc24M", 0x0010,
  74                                             192000000,  /* Minimum rate */
  75                                             8, 7,       /* N */
  76                                             0, 4,       /* M */
  77                                             BIT(24),    /* frac enable */
  78                                             BIT(25),    /* frac select */
  79                                             270000000,  /* frac rate 0 */
  80                                             297000000,  /* frac rate 1 */
  81                                             BIT(31),    /* gate */
  82                                             BIT(28),    /* lock */
  83                                             CLK_SET_RATE_UNGATE);
  84
  85 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
  86                                         "osc24M", 0x0018,
  87                                         8, 7,           /* N */
  88                                         0, 4,           /* M */
  89                                         BIT(24),        /* frac enable */
  90                                         BIT(25),        /* frac select */
  91                                         270000000,      /* frac rate 0 */
  92                                         297000000,      /* frac rate 1 */
  93                                         BIT(31),        /* gate */
  94                                         BIT(28),        /* lock */
  95                                         CLK_SET_RATE_UNGATE);
  96
  97 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr",
  98                                     "osc24M", 0x020,
  99                                     8, 5,       /* N */
 100                                     4, 2,       /* K */
 101                                     0, 2,       /* M */
 102                                     BIT(31),    /* gate */
 103                                     BIT(28),    /* lock */
 104                                     CLK_SET_RATE_UNGATE);
 105
 106 static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph0_clk, "pll-periph0",
 107                                            "osc24M", 0x028,
 108                                            8, 5,        /* N */
 109                                            4, 2,        /* K */
 110                                            BIT(31),     /* gate */
 111                                            BIT(28),     /* lock */
 112                                            2,           /* post-div */
 113                                            CLK_SET_RATE_UNGATE);
 114
 115 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
 116                                         "osc24M", 0x0038,
 117                                         8, 7,           /* N */
 118                                         0, 4,           /* M */
 119                                         BIT(24),        /* frac enable */
 120                                         BIT(25),        /* frac select */
 121                                         270000000,      /* frac rate 0 */
 122                                         297000000,      /* frac rate 1 */
 123                                         BIT(31),        /* gate */
 124                                         BIT(28),        /* lock */
 125                                         CLK_SET_RATE_UNGATE);
 126
 127 static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph1_clk, "pll-periph1",
 128                                            "osc24M", 0x044,
 129                                            8, 5,        /* N */
 130                                            4, 2,        /* K */
 131                                            BIT(31),     /* gate */
 132                                            BIT(28),     /* lock */
 133                                            2,           /* post-div */
 134                                            CLK_SET_RATE_UNGATE);
 135
 136 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
 137                                         "osc24M", 0x0048,
 138                                         8, 7,           /* N */
 139                                         0, 4,           /* M */
 140                                         BIT(24),        /* frac enable */
 141                                         BIT(25),        /* frac select */
 142                                         270000000,      /* frac rate 0 */
 143                                         297000000,      /* frac rate 1 */
 144                                         BIT(31),        /* gate */
 145                                         BIT(28),        /* lock */
 146                                         CLK_SET_RATE_UNGATE);
 147
 148 static const char * const cpux_parents[] = { "osc32k", "osc24M",
 149                                              "pll-cpux" , "pll-cpux" };
 150 static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
 151                      0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT);
 152
 153 static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
 154
 155 static const char * const ahb1_parents[] = { "osc32k", "osc24M",
 156                                              "axi" , "pll-periph0" };
 157 static const struct ccu_mux_var_prediv ahb1_predivs[] = {
 158         { .index = 3, .shift = 6, .width = 2 },
 159 };
 160 static struct ccu_div ahb1_clk = {
 161         .div            = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
 162
 163         .mux            = {
 164                 .shift  = 12,
 165                 .width  = 2,
 166
 167                 .var_predivs    = ahb1_predivs,
 168                 .n_var_predivs  = ARRAY_SIZE(ahb1_predivs),
 169         },
 170
 171         .common         = {
 172                 .reg            = 0x054,
 173                 .features       = CCU_FEATURE_VARIABLE_PREDIV,
 174                 .hw.init        = CLK_HW_INIT_PARENTS("ahb1",
 175                                                       ahb1_parents,
 176                                                       &ccu_div_ops,
 177                                                       0),
 178         },
 179 };
 180
 181 static struct clk_div_table apb1_div_table[] = {
 182         { .val = 0, .div = 2 },
 183         { .val = 1, .div = 2 },
 184         { .val = 2, .div = 4 },
 185         { .val = 3, .div = 8 },
 186         { /* Sentinel */ },
 187 };
 188 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
 189                            0x054, 8, 2, apb1_div_table, 0);
 190
 191 static const char * const apb2_parents[] = { "osc32k", "osc24M",
 192                                              "pll-periph0" , "pll-periph0" };
 193 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
 194                              0, 5,      /* M */
 195                              16, 2,     /* P */
 196                              24, 2,     /* mux */
 197                              0);
 198
 199 static const char * const ahb2_parents[] = { "ahb1" , "pll-periph0" };
 200 static const struct ccu_mux_fixed_prediv ahb2_fixed_predivs[] = {
 201         { .index = 1, .div = 2 },
 202 };
 203 static struct ccu_mux ahb2_clk = {
 204         .mux            = {
 205                 .shift  = 0,
 206                 .width  = 1,
 207                 .fixed_predivs  = ahb2_fixed_predivs,
 208                 .n_predivs      = ARRAY_SIZE(ahb2_fixed_predivs),
 209         },
 210
 211         .common         = {
 212                 .reg            = 0x05c,
 213                 .features       = CCU_FEATURE_FIXED_PREDIV,
 214                 .hw.init        = CLK_HW_INIT_PARENTS("ahb2",
 215                                                       ahb2_parents,
 216                                                       &ccu_mux_ops,
 217                                                       0),
 218         },
 219 };
 220
 221 static SUNXI_CCU_GATE(bus_ce_clk,       "bus-ce",       "ahb1",
 222                       0x060, BIT(5), 0);
 223 static SUNXI_CCU_GATE(bus_dma_clk,      "bus-dma",      "ahb1",
 224                       0x060, BIT(6), 0);
 225 static SUNXI_CCU_GATE(bus_mmc0_clk,     "bus-mmc0",     "ahb1",
 226                       0x060, BIT(8), 0);
 227 static SUNXI_CCU_GATE(bus_mmc1_clk,     "bus-mmc1",     "ahb1",
 228                       0x060, BIT(9), 0);
 229 static SUNXI_CCU_GATE(bus_mmc2_clk,     "bus-mmc2",     "ahb1",
 230                       0x060, BIT(10), 0);
 231 static SUNXI_CCU_GATE(bus_nand_clk,     "bus-nand",     "ahb1",
 232                       0x060, BIT(13), 0);
 233 static SUNXI_CCU_GATE(bus_dram_clk,     "bus-dram",     "ahb1",
 234                       0x060, BIT(14), 0);
 235 static SUNXI_CCU_GATE(bus_emac_clk,     "bus-emac",     "ahb2",
 236                       0x060, BIT(17), 0);
 237 static SUNXI_CCU_GATE(bus_ts_clk,       "bus-ts",       "ahb1",
 238                       0x060, BIT(18), 0);
 239 static SUNXI_CCU_GATE(bus_hstimer_clk,  "bus-hstimer",  "ahb1",
 240                       0x060, BIT(19), 0);
 241 static SUNXI_CCU_GATE(bus_spi0_clk,     "bus-spi0",     "ahb1",
 242                       0x060, BIT(20), 0);
 243 static SUNXI_CCU_GATE(bus_spi1_clk,     "bus-spi1",     "ahb1",
 244                       0x060, BIT(21), 0);
 245 static SUNXI_CCU_GATE(bus_otg_clk,      "bus-otg",      "ahb1",
 246                       0x060, BIT(23), 0);
 247 static SUNXI_CCU_GATE(bus_ehci0_clk,    "bus-ehci0",    "ahb1",
 248                       0x060, BIT(24), 0);
 249 static SUNXI_CCU_GATE(bus_ehci1_clk,    "bus-ehci1",    "ahb2",
 250                       0x060, BIT(25), 0);
 251 static SUNXI_CCU_GATE(bus_ehci2_clk,    "bus-ehci2",    "ahb2",
 252                       0x060, BIT(26), 0);
 253 static SUNXI_CCU_GATE(bus_ehci3_clk,    "bus-ehci3",    "ahb2",
 254                       0x060, BIT(27), 0);
 255 static SUNXI_CCU_GATE(bus_ohci0_clk,    "bus-ohci0",    "ahb1",
 256                       0x060, BIT(28), 0);
 257 static SUNXI_CCU_GATE(bus_ohci1_clk,    "bus-ohci1",    "ahb2",
 258                       0x060, BIT(29), 0);
 259 static SUNXI_CCU_GATE(bus_ohci2_clk,    "bus-ohci2",    "ahb2",
 260                       0x060, BIT(30), 0);
 261 static SUNXI_CCU_GATE(bus_ohci3_clk,    "bus-ohci3",    "ahb2",
 262                       0x060, BIT(31), 0);
 263
 264 static SUNXI_CCU_GATE(bus_ve_clk,       "bus-ve",       "ahb1",
 265                       0x064, BIT(0), 0);
 266 static SUNXI_CCU_GATE(bus_tcon0_clk,    "bus-tcon0",    "ahb1",
 267                       0x064, BIT(3), 0);
 268 static SUNXI_CCU_GATE(bus_tcon1_clk,    "bus-tcon1",    "ahb1",
 269                       0x064, BIT(4), 0);
 270 static SUNXI_CCU_GATE(bus_deinterlace_clk,      "bus-deinterlace",      "ahb1",
 271                       0x064, BIT(5), 0);
 272 static SUNXI_CCU_GATE(bus_csi_clk,      "bus-csi",      "ahb1",
 273                       0x064, BIT(8), 0);
 274 static SUNXI_CCU_GATE(bus_tve_clk,      "bus-tve",      "ahb1",
 275                       0x064, BIT(9), 0);
 276 static SUNXI_CCU_GATE(bus_hdmi_clk,     "bus-hdmi",     "ahb1",
 277                       0x064, BIT(11), 0);
 278 static SUNXI_CCU_GATE(bus_de_clk,       "bus-de",       "ahb1",
 279                       0x064, BIT(12), 0);
 280 static SUNXI_CCU_GATE(bus_gpu_clk,      "bus-gpu",      "ahb1",
 281                       0x064, BIT(20), 0);
 282 static SUNXI_CCU_GATE(bus_msgbox_clk,   "bus-msgbox",   "ahb1",
 283                       0x064, BIT(21), 0);
 284 static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",
 285                       0x064, BIT(22), 0);
 286
 287 static SUNXI_CCU_GATE(bus_codec_clk,    "bus-codec",    "apb1",
 288                       0x068, BIT(0), 0);
 289 static SUNXI_CCU_GATE(bus_spdif_clk,    "bus-spdif",    "apb1",
 290                       0x068, BIT(1), 0);
 291 static SUNXI_CCU_GATE(bus_pio_clk,      "bus-pio",      "apb1",
 292                       0x068, BIT(5), 0);
 293 static SUNXI_CCU_GATE(bus_ths_clk,      "bus-ths",      "apb1",
 294                       0x068, BIT(8), 0);
 295 static SUNXI_CCU_GATE(bus_i2s0_clk,     "bus-i2s0",     "apb1",
 296                       0x068, BIT(12), 0);
 297 static SUNXI_CCU_GATE(bus_i2s1_clk,     "bus-i2s1",     "apb1",
 298                       0x068, BIT(13), 0);
 299 static SUNXI_CCU_GATE(bus_i2s2_clk,     "bus-i2s2",     "apb1",
 300                       0x068, BIT(14), 0);
 301
 302 static SUNXI_CCU_GATE(bus_i2c0_clk,     "bus-i2c0",     "apb2",
 303                       0x06c, BIT(0), 0);
 304 static SUNXI_CCU_GATE(bus_i2c1_clk,     "bus-i2c1",     "apb2",
 305                       0x06c, BIT(1), 0);
 306 static SUNXI_CCU_GATE(bus_i2c2_clk,     "bus-i2c2",     "apb2",
 307                       0x06c, BIT(2), 0);
 308 static SUNXI_CCU_GATE(bus_uart0_clk,    "bus-uart0",    "apb2",
 309                       0x06c, BIT(16), 0);
 310 static SUNXI_CCU_GATE(bus_uart1_clk,    "bus-uart1",    "apb2",
 311                       0x06c, BIT(17), 0);
 312 static SUNXI_CCU_GATE(bus_uart2_clk,    "bus-uart2",    "apb2",
 313                       0x06c, BIT(18), 0);
 314 static SUNXI_CCU_GATE(bus_uart3_clk,    "bus-uart3",    "apb2",
 315                       0x06c, BIT(19), 0);
 316 static SUNXI_CCU_GATE(bus_scr0_clk,     "bus-scr0",     "apb2",
 317                       0x06c, BIT(20), 0);
 318 static SUNXI_CCU_GATE(bus_scr1_clk,     "bus-scr1",     "apb2",
 319                       0x06c, BIT(21), 0);
 320
 321 static SUNXI_CCU_GATE(bus_ephy_clk,     "bus-ephy",     "ahb1",
 322                       0x070, BIT(0), 0);
 323 static SUNXI_CCU_GATE(bus_dbg_clk,      "bus-dbg",      "ahb1",
 324                       0x070, BIT(7), 0);
 325
 326 static struct clk_div_table ths_div_table[] = {
 327         { .val = 0, .div = 1 },
 328         { .val = 1, .div = 2 },
 329         { .val = 2, .div = 4 },
 330         { .val = 3, .div = 6 },
 331         { /* Sentinel */ },
 332 };
 333 static SUNXI_CCU_DIV_TABLE_WITH_GATE(ths_clk, "ths", "osc24M",
 334                                      0x074, 0, 2, ths_div_table, BIT(31), 0);
 335
 336 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0",
 337                                                      "pll-periph1" };
 338 static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
 339                                   0, 4,         /* M */
 340                                   16, 2,        /* P */
 341                                   24, 2,        /* mux */
 342                                   BIT(31),      /* gate */
 343                                   0);
 344
 345 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
 346                                   0, 4,         /* M */
 347                                   16, 2,        /* P */
 348                                   24, 2,        /* mux */
 349                                   BIT(31),      /* gate */
 350                                   0);
 351
 352 static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0",
 353                        0x088, 20, 3, 0);
 354 static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0",
 355                        0x088, 8, 3, 0);
 356
 357 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
 358                                   0, 4,         /* M */
 359                                   16, 2,        /* P */
 360                                   24, 2,        /* mux */
 361                                   BIT(31),      /* gate */
 362                                   0);
 363
 364 static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1",
 365                        0x08c, 20, 3, 0);
 366 static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1",
 367                        0x08c, 8, 3, 0);
 368
 369 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
 370                                   0, 4,         /* M */
 371                                   16, 2,        /* P */
 372                                   24, 2,        /* mux */
 373                                   BIT(31),      /* gate */
 374                                   0);
 375
 376 static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2",
 377                        0x090, 20, 3, 0);
 378 static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2",
 379                        0x090, 8, 3, 0);
 380
 381 static const char * const ts_parents[] = { "osc24M", "pll-periph0", };
 382 static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x098,
 383                                   0, 4,         /* M */
 384                                   16, 2,        /* P */
 385                                   24, 2,        /* mux */
 386                                   BIT(31),      /* gate */
 387                                   0);
 388
 389 static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", mod0_default_parents, 0x09c,
 390                                   0, 4,         /* M */
 391                                   16, 2,        /* P */
 392                                   24, 2,        /* mux */
 393                                   BIT(31),      /* gate */
 394                                   0);
 395
 396 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
 397                                   0, 4,         /* M */
 398                                   16, 2,        /* P */
 399                                   24, 2,        /* mux */
 400                                   BIT(31),      /* gate */
 401                                   0);
 402
 403 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
 404                                   0, 4,         /* M */
 405                                   16, 2,        /* P */
 406                                   24, 2,        /* mux */
 407                                   BIT(31),      /* gate */
 408                                   0);
 409
 410 static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
 411                                             "pll-audio-2x", "pll-audio" };
 412 static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents,
 413                                0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
 414
 415 static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents,
 416                                0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
 417
 418 static SUNXI_CCU_MUX_WITH_GATE(i2s2_clk, "i2s2", i2s_parents,
 419                                0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
 420
 421 static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio",
 422                              0x0c0, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
 423
 424 static SUNXI_CCU_GATE(usb_phy0_clk,     "usb-phy0",     "osc24M",
 425                       0x0cc, BIT(8), 0);
 426 static SUNXI_CCU_GATE(usb_phy1_clk,     "usb-phy1",     "osc24M",
 427                       0x0cc, BIT(9), 0);
 428 static SUNXI_CCU_GATE(usb_phy2_clk,     "usb-phy2",     "osc24M",
 429                       0x0cc, BIT(10), 0);
 430 static SUNXI_CCU_GATE(usb_phy3_clk,     "usb-phy3",     "osc24M",
 431                       0x0cc, BIT(11), 0);
 432 static SUNXI_CCU_GATE(usb_ohci0_clk,    "usb-ohci0",    "osc24M",
 433                       0x0cc, BIT(16), 0);
 434 static SUNXI_CCU_GATE(usb_ohci1_clk,    "usb-ohci1",    "osc24M",
 435                       0x0cc, BIT(17), 0);
 436 static SUNXI_CCU_GATE(usb_ohci2_clk,    "usb-ohci2",    "osc24M",
 437                       0x0cc, BIT(18), 0);
 438 static SUNXI_CCU_GATE(usb_ohci3_clk,    "usb-ohci3",    "osc24M",
 439                       0x0cc, BIT(19), 0);
 440
 441 static const char * const dram_parents[] = { "pll-ddr", "pll-periph0-2x" };
 442 static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents,
 443                             0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL);
 444
 445 static SUNXI_CCU_GATE(dram_ve_clk,      "dram-ve",      "dram",
 446                       0x100, BIT(0), 0);
 447 static SUNXI_CCU_GATE(dram_csi_clk,     "dram-csi",     "dram",
 448                       0x100, BIT(1), 0);
 449 static SUNXI_CCU_GATE(dram_deinterlace_clk,     "dram-deinterlace",     "dram",
 450                       0x100, BIT(2), 0);
 451 static SUNXI_CCU_GATE(dram_ts_clk,      "dram-ts",      "dram",
 452                       0x100, BIT(3), 0);
 453
 454 static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };
 455 static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
 456                                  0x104, 0, 4, 24, 3, BIT(31),
 457                                  CLK_SET_RATE_PARENT);
 458
 459 static const char * const tcon_parents[] = { "pll-video" };
 460 static SUNXI_CCU_M_WITH_MUX_GATE(tcon_clk, "tcon", tcon_parents,
 461                                  0x118, 0, 4, 24, 3, BIT(31),
 462                                  CLK_SET_RATE_PARENT);
 463
 464 static const char * const tve_parents[] = { "pll-de", "pll-periph1" };
 465 static SUNXI_CCU_M_WITH_MUX_GATE(tve_clk, "tve", tve_parents,
 466                                  0x120, 0, 4, 24, 3, BIT(31), 0);
 467
 468 static const char * const deinterlace_parents[] = { "pll-periph0", "pll-periph1" };
 469 static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace", deinterlace_parents,
 470                                  0x124, 0, 4, 24, 3, BIT(31), 0);
 471
 472 static SUNXI_CCU_GATE(csi_misc_clk,     "csi-misc",     "osc24M",
 473                       0x130, BIT(31), 0);
 474
 475 static const char * const csi_sclk_parents[] = { "pll-periph0", "pll-periph1" };
 476 static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents,
 477                                  0x134, 16, 4, 24, 3, BIT(31), 0);
 478
 479 static const char * const csi_mclk_parents[] = { "osc24M", "pll-video", "pll-periph1" };
 480 static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents,
 481                                  0x134, 0, 5, 8, 3, BIT(15), 0);
 482
 483 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
 484                              0x13c, 16, 3, BIT(31), 0);
 485
 486 static SUNXI_CCU_GATE(ac_dig_clk,       "ac-dig",       "pll-audio",
 487                       0x140, BIT(31), CLK_SET_RATE_PARENT);
 488 static SUNXI_CCU_GATE(avs_clk,          "avs",          "osc24M",
 489                       0x144, BIT(31), 0);
 490
 491 static const char * const hdmi_parents[] = { "pll-video" };
 492 static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
 493                                  0x150, 0, 4, 24, 2, BIT(31),
 494                                  CLK_SET_RATE_PARENT);
 495
 496 static SUNXI_CCU_GATE(hdmi_ddc_clk,     "hdmi-ddc",     "osc24M",
 497                       0x154, BIT(31), 0);
 498
 499 static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x", "pll-ddr" };
 500 static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
 501                                  0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
 502
 503 static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
 504                              0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
 505
 506 static struct ccu_common *sun8i_h3_ccu_clks[] = {
 507         &pll_cpux_clk.common,
 508         &pll_audio_base_clk.common,
 509         &pll_video_clk.common,
 510         &pll_ve_clk.common,
 511         &pll_ddr_clk.common,
 512         &pll_periph0_clk.common,
 513         &pll_gpu_clk.common,
 514         &pll_periph1_clk.common,
 515         &pll_de_clk.common,
 516         &cpux_clk.common,
 517         &axi_clk.common,
 518         &ahb1_clk.common,
 519         &apb1_clk.common,
 520         &apb2_clk.common,
 521         &ahb2_clk.common,
 522         &bus_ce_clk.common,
 523         &bus_dma_clk.common,
 524         &bus_mmc0_clk.common,
 525         &bus_mmc1_clk.common,
 526         &bus_mmc2_clk.common,
 527         &bus_nand_clk.common,
 528         &bus_dram_clk.common,
 529         &bus_emac_clk.common,
 530         &bus_ts_clk.common,
 531         &bus_hstimer_clk.common,
 532         &bus_spi0_clk.common,
 533         &bus_spi1_clk.common,
 534         &bus_otg_clk.common,
 535         &bus_ehci0_clk.common,
 536         &bus_ehci1_clk.common,
 537         &bus_ehci2_clk.common,
 538         &bus_ehci3_clk.common,
 539         &bus_ohci0_clk.common,
 540         &bus_ohci1_clk.common,
 541         &bus_ohci2_clk.common,
 542         &bus_ohci3_clk.common,
 543         &bus_ve_clk.common,
 544         &bus_tcon0_clk.common,
 545         &bus_tcon1_clk.common,
 546         &bus_deinterlace_clk.common,
 547         &bus_csi_clk.common,
 548         &bus_tve_clk.common,
 549         &bus_hdmi_clk.common,
 550         &bus_de_clk.common,
 551         &bus_gpu_clk.common,
 552         &bus_msgbox_clk.common,
 553         &bus_spinlock_clk.common,
 554         &bus_codec_clk.common,
 555         &bus_spdif_clk.common,
 556         &bus_pio_clk.common,
 557         &bus_ths_clk.common,
 558         &bus_i2s0_clk.common,
 559         &bus_i2s1_clk.common,
 560         &bus_i2s2_clk.common,
 561         &bus_i2c0_clk.common,
 562         &bus_i2c1_clk.common,
 563         &bus_i2c2_clk.common,
 564         &bus_uart0_clk.common,
 565         &bus_uart1_clk.common,
 566         &bus_uart2_clk.common,
 567         &bus_uart3_clk.common,
 568         &bus_scr0_clk.common,
 569         &bus_ephy_clk.common,
 570         &bus_dbg_clk.common,
 571         &ths_clk.common,
 572         &nand_clk.common,
 573         &mmc0_clk.common,
 574         &mmc0_sample_clk.common,
 575         &mmc0_output_clk.common,
 576         &mmc1_clk.common,
 577         &mmc1_sample_clk.common,
 578         &mmc1_output_clk.common,
 579         &mmc2_clk.common,
 580         &mmc2_sample_clk.common,
 581         &mmc2_output_clk.common,
 582         &ts_clk.common,
 583         &ce_clk.common,
 584         &spi0_clk.common,
 585         &spi1_clk.common,
 586         &i2s0_clk.common,
 587         &i2s1_clk.common,
 588         &i2s2_clk.common,
 589         &spdif_clk.common,
 590         &usb_phy0_clk.common,
 591         &usb_phy1_clk.common,
 592         &usb_phy2_clk.common,
 593         &usb_phy3_clk.common,
 594         &usb_ohci0_clk.common,
 595         &usb_ohci1_clk.common,
 596         &usb_ohci2_clk.common,
 597         &usb_ohci3_clk.common,
 598         &dram_clk.common,
 599         &dram_ve_clk.common,
 600         &dram_csi_clk.common,
 601         &dram_deinterlace_clk.common,
 602         &dram_ts_clk.common,
 603         &de_clk.common,
 604         &tcon_clk.common,
 605         &tve_clk.common,
 606         &deinterlace_clk.common,
 607         &csi_misc_clk.common,
 608         &csi_sclk_clk.common,
 609         &csi_mclk_clk.common,
 610         &ve_clk.common,
 611         &ac_dig_clk.common,
 612         &avs_clk.common,
 613         &hdmi_clk.common,
 614         &hdmi_ddc_clk.common,
 615         &mbus_clk.common,
 616         &gpu_clk.common,
 617 };
 618
 619 static struct ccu_common *sun50i_h5_ccu_clks[] = {
 620         &pll_cpux_clk.common,
 621         &pll_audio_base_clk.common,
 622         &pll_video_clk.common,
 623         &pll_ve_clk.common,
 624         &pll_ddr_clk.common,
 625         &pll_periph0_clk.common,
 626         &pll_gpu_clk.common,
 627         &pll_periph1_clk.common,
 628         &pll_de_clk.common,
 629         &cpux_clk.common,
 630         &axi_clk.common,
 631         &ahb1_clk.common,
 632         &apb1_clk.common,
 633         &apb2_clk.common,
 634         &ahb2_clk.common,
 635         &bus_ce_clk.common,
 636         &bus_dma_clk.common,
 637         &bus_mmc0_clk.common,
 638         &bus_mmc1_clk.common,
 639         &bus_mmc2_clk.common,
 640         &bus_nand_clk.common,
 641         &bus_dram_clk.common,
 642         &bus_emac_clk.common,
 643         &bus_ts_clk.common,
 644         &bus_hstimer_clk.common,
 645         &bus_spi0_clk.common,
 646         &bus_spi1_clk.common,
 647         &bus_otg_clk.common,
 648         &bus_ehci0_clk.common,
 649         &bus_ehci1_clk.common,
 650         &bus_ehci2_clk.common,
 651         &bus_ehci3_clk.common,
 652         &bus_ohci0_clk.common,
 653         &bus_ohci1_clk.common,
 654         &bus_ohci2_clk.common,
 655         &bus_ohci3_clk.common,
 656         &bus_ve_clk.common,
 657         &bus_tcon0_clk.common,
 658         &bus_tcon1_clk.common,
 659         &bus_deinterlace_clk.common,
 660         &bus_csi_clk.common,
 661         &bus_tve_clk.common,
 662         &bus_hdmi_clk.common,
 663         &bus_de_clk.common,
 664         &bus_gpu_clk.common,
 665         &bus_msgbox_clk.common,
 666         &bus_spinlock_clk.common,
 667         &bus_codec_clk.common,
 668         &bus_spdif_clk.common,
 669         &bus_pio_clk.common,
 670         &bus_ths_clk.common,
 671         &bus_i2s0_clk.common,
 672         &bus_i2s1_clk.common,
 673         &bus_i2s2_clk.common,
 674         &bus_i2c0_clk.common,
 675         &bus_i2c1_clk.common,
 676         &bus_i2c2_clk.common,
 677         &bus_uart0_clk.common,
 678         &bus_uart1_clk.common,
 679         &bus_uart2_clk.common,
 680         &bus_uart3_clk.common,
 681         &bus_scr0_clk.common,
 682         &bus_scr1_clk.common,
 683         &bus_ephy_clk.common,
 684         &bus_dbg_clk.common,
 685         &ths_clk.common,
 686         &nand_clk.common,
 687         &mmc0_clk.common,
 688         &mmc1_clk.common,
 689         &mmc2_clk.common,
 690         &ts_clk.common,
 691         &ce_clk.common,
 692         &spi0_clk.common,
 693         &spi1_clk.common,
 694         &i2s0_clk.common,
 695         &i2s1_clk.common,
 696         &i2s2_clk.common,
 697         &spdif_clk.common,
 698         &usb_phy0_clk.common,
 699         &usb_phy1_clk.common,
 700         &usb_phy2_clk.common,
 701         &usb_phy3_clk.common,
 702         &usb_ohci0_clk.common,
 703         &usb_ohci1_clk.common,
 704         &usb_ohci2_clk.common,
 705         &usb_ohci3_clk.common,
 706         &dram_clk.common,
 707         &dram_ve_clk.common,
 708         &dram_csi_clk.common,
 709         &dram_deinterlace_clk.common,
 710         &dram_ts_clk.common,
 711         &de_clk.common,
 712         &tcon_clk.common,
 713         &tve_clk.common,
 714         &deinterlace_clk.common,
 715         &csi_misc_clk.common,
 716         &csi_sclk_clk.common,
 717         &csi_mclk_clk.common,
 718         &ve_clk.common,
 719         &ac_dig_clk.common,
 720         &avs_clk.common,
 721         &hdmi_clk.common,
 722         &hdmi_ddc_clk.common,
 723         &mbus_clk.common,
 724         &gpu_clk.common,
 725 };
 726
 727 /* We hardcode the divider to 1 for now */
 728 static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
 729                         "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
 730 static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
 731                         "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
 732 static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
 733                         "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
 734 static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
 735                         "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
 736 static CLK_FIXED_FACTOR(pll_periph0_2x_clk, "pll-periph0-2x",
 737                         "pll-periph0", 1, 2, 0);
 738
 739 static struct clk_hw_onecell_data sun8i_h3_hw_clks = {
 740         .hws    = {
 741                 [CLK_PLL_CPUX]          = &pll_cpux_clk.common.hw,
 742                 [CLK_PLL_AUDIO_BASE]    = &pll_audio_base_clk.common.hw,
 743                 [CLK_PLL_AUDIO]         = &pll_audio_clk.hw,
 744                 [CLK_PLL_AUDIO_2X]      = &pll_audio_2x_clk.hw,
 745                 [CLK_PLL_AUDIO_4X]      = &pll_audio_4x_clk.hw,
 746                 [CLK_PLL_AUDIO_8X]      = &pll_audio_8x_clk.hw,
 747                 [CLK_PLL_VIDEO]         = &pll_video_clk.common.hw,
 748                 [CLK_PLL_VE]            = &pll_ve_clk.common.hw,
 749                 [CLK_PLL_DDR]           = &pll_ddr_clk.common.hw,
 750                 [CLK_PLL_PERIPH0]       = &pll_periph0_clk.common.hw,
 751                 [CLK_PLL_PERIPH0_2X]    = &pll_periph0_2x_clk.hw,
 752                 [CLK_PLL_GPU]           = &pll_gpu_clk.common.hw,
 753                 [CLK_PLL_PERIPH1]       = &pll_periph1_clk.common.hw,
 754                 [CLK_PLL_DE]            = &pll_de_clk.common.hw,
 755                 [CLK_CPUX]              = &cpux_clk.common.hw,
 756                 [CLK_AXI]               = &axi_clk.common.hw,
 757                 [CLK_AHB1]              = &ahb1_clk.common.hw,
 758                 [CLK_APB1]              = &apb1_clk.common.hw,
 759                 [CLK_APB2]              = &apb2_clk.common.hw,
 760                 [CLK_AHB2]              = &ahb2_clk.common.hw,
 761                 [CLK_BUS_CE]            = &bus_ce_clk.common.hw,
 762                 [CLK_BUS_DMA]           = &bus_dma_clk.common.hw,
 763                 [CLK_BUS_MMC0]          = &bus_mmc0_clk.common.hw,
 764                 [CLK_BUS_MMC1]          = &bus_mmc1_clk.common.hw,
 765                 [CLK_BUS_MMC2]          = &bus_mmc2_clk.common.hw,
 766                 [CLK_BUS_NAND]          = &bus_nand_clk.common.hw,
 767                 [CLK_BUS_DRAM]          = &bus_dram_clk.common.hw,
 768                 [CLK_BUS_EMAC]          = &bus_emac_clk.common.hw,
 769                 [CLK_BUS_TS]            = &bus_ts_clk.common.hw,
 770                 [CLK_BUS_HSTIMER]       = &bus_hstimer_clk.common.hw,
 771                 [CLK_BUS_SPI0]          = &bus_spi0_clk.common.hw,
 772                 [CLK_BUS_SPI1]          = &bus_spi1_clk.common.hw,
 773                 [CLK_BUS_OTG]           = &bus_otg_clk.common.hw,
 774                 [CLK_BUS_EHCI0]         = &bus_ehci0_clk.common.hw,
 775                 [CLK_BUS_EHCI1]         = &bus_ehci1_clk.common.hw,
 776                 [CLK_BUS_EHCI2]         = &bus_ehci2_clk.common.hw,
 777                 [CLK_BUS_EHCI3]         = &bus_ehci3_clk.common.hw,
 778                 [CLK_BUS_OHCI0]         = &bus_ohci0_clk.common.hw,
 779                 [CLK_BUS_OHCI1]         = &bus_ohci1_clk.common.hw,
 780                 [CLK_BUS_OHCI2]         = &bus_ohci2_clk.common.hw,
 781                 [CLK_BUS_OHCI3]         = &bus_ohci3_clk.common.hw,
 782                 [CLK_BUS_VE]            = &bus_ve_clk.common.hw,
 783                 [CLK_BUS_TCON0]         = &bus_tcon0_clk.common.hw,
 784                 [CLK_BUS_TCON1]         = &bus_tcon1_clk.common.hw,
 785                 [CLK_BUS_DEINTERLACE]   = &bus_deinterlace_clk.common.hw,
 786                 [CLK_BUS_CSI]           = &bus_csi_clk.common.hw,
 787                 [CLK_BUS_TVE]           = &bus_tve_clk.common.hw,
 788                 [CLK_BUS_HDMI]          = &bus_hdmi_clk.common.hw,
 789                 [CLK_BUS_DE]            = &bus_de_clk.common.hw,
 790                 [CLK_BUS_GPU]           = &bus_gpu_clk.common.hw,
 791                 [CLK_BUS_MSGBOX]        = &bus_msgbox_clk.common.hw,
 792                 [CLK_BUS_SPINLOCK]      = &bus_spinlock_clk.common.hw,
 793                 [CLK_BUS_CODEC]         = &bus_codec_clk.common.hw,
 794                 [CLK_BUS_SPDIF]         = &bus_spdif_clk.common.hw,
 795                 [CLK_BUS_PIO]           = &bus_pio_clk.common.hw,
 796                 [CLK_BUS_THS]           = &bus_ths_clk.common.hw,
 797                 [CLK_BUS_I2S0]          = &bus_i2s0_clk.common.hw,
 798                 [CLK_BUS_I2S1]          = &bus_i2s1_clk.common.hw,
 799                 [CLK_BUS_I2S2]          = &bus_i2s2_clk.common.hw,
 800                 [CLK_BUS_I2C0]          = &bus_i2c0_clk.common.hw,
 801                 [CLK_BUS_I2C1]          = &bus_i2c1_clk.common.hw,
 802                 [CLK_BUS_I2C2]          = &bus_i2c2_clk.common.hw,
 803                 [CLK_BUS_UART0]         = &bus_uart0_clk.common.hw,
 804                 [CLK_BUS_UART1]         = &bus_uart1_clk.common.hw,
 805                 [CLK_BUS_UART2]         = &bus_uart2_clk.common.hw,
 806                 [CLK_BUS_UART3]         = &bus_uart3_clk.common.hw,
 807                 [CLK_BUS_SCR0]          = &bus_scr0_clk.common.hw,
 808                 [CLK_BUS_EPHY]          = &bus_ephy_clk.common.hw,
 809                 [CLK_BUS_DBG]           = &bus_dbg_clk.common.hw,
 810                 [CLK_THS]               = &ths_clk.common.hw,
 811                 [CLK_NAND]              = &nand_clk.common.hw,
 812                 [CLK_MMC0]              = &mmc0_clk.common.hw,
 813                 [CLK_MMC0_SAMPLE]       = &mmc0_sample_clk.common.hw,
 814                 [CLK_MMC0_OUTPUT]       = &mmc0_output_clk.common.hw,
 815                 [CLK_MMC1]              = &mmc1_clk.common.hw,
 816                 [CLK_MMC1_SAMPLE]       = &mmc1_sample_clk.common.hw,
 817                 [CLK_MMC1_OUTPUT]       = &mmc1_output_clk.common.hw,
 818                 [CLK_MMC2]              = &mmc2_clk.common.hw,
 819                 [CLK_MMC2_SAMPLE]       = &mmc2_sample_clk.common.hw,
 820                 [CLK_MMC2_OUTPUT]       = &mmc2_output_clk.common.hw,
 821                 [CLK_TS]                = &ts_clk.common.hw,
 822                 [CLK_CE]                = &ce_clk.common.hw,
 823                 [CLK_SPI0]              = &spi0_clk.common.hw,
 824                 [CLK_SPI1]              = &spi1_clk.common.hw,
 825                 [CLK_I2S0]              = &i2s0_clk.common.hw,
 826                 [CLK_I2S1]              = &i2s1_clk.common.hw,
 827                 [CLK_I2S2]              = &i2s2_clk.common.hw,
 828                 [CLK_SPDIF]             = &spdif_clk.common.hw,
 829                 [CLK_USB_PHY0]          = &usb_phy0_clk.common.hw,
 830                 [CLK_USB_PHY1]          = &usb_phy1_clk.common.hw,
 831                 [CLK_USB_PHY2]          = &usb_phy2_clk.common.hw,
 832                 [CLK_USB_PHY3]          = &usb_phy3_clk.common.hw,
 833                 [CLK_USB_OHCI0]         = &usb_ohci0_clk.common.hw,
 834                 [CLK_USB_OHCI1]         = &usb_ohci1_clk.common.hw,
 835                 [CLK_USB_OHCI2]         = &usb_ohci2_clk.common.hw,
 836                 [CLK_USB_OHCI3]         = &usb_ohci3_clk.common.hw,
 837                 [CLK_DRAM]              = &dram_clk.common.hw,
 838                 [CLK_DRAM_VE]           = &dram_ve_clk.common.hw,
 839                 [CLK_DRAM_CSI]          = &dram_csi_clk.common.hw,
 840                 [CLK_DRAM_DEINTERLACE]  = &dram_deinterlace_clk.common.hw,
 841                 [CLK_DRAM_TS]           = &dram_ts_clk.common.hw,
 842                 [CLK_DE]                = &de_clk.common.hw,
 843                 [CLK_TCON0]             = &tcon_clk.common.hw,
 844                 [CLK_TVE]               = &tve_clk.common.hw,
 845                 [CLK_DEINTERLACE]       = &deinterlace_clk.common.hw,
 846                 [CLK_CSI_MISC]          = &csi_misc_clk.common.hw,
 847                 [CLK_CSI_SCLK]          = &csi_sclk_clk.common.hw,
 848                 [CLK_CSI_MCLK]          = &csi_mclk_clk.common.hw,
 849                 [CLK_VE]                = &ve_clk.common.hw,
 850                 [CLK_AC_DIG]            = &ac_dig_clk.common.hw,
 851                 [CLK_AVS]               = &avs_clk.common.hw,
 852                 [CLK_HDMI]              = &hdmi_clk.common.hw,
 853                 [CLK_HDMI_DDC]          = &hdmi_ddc_clk.common.hw,
 854                 [CLK_MBUS]              = &mbus_clk.common.hw,
 855                 [CLK_GPU]               = &gpu_clk.common.hw,
 856         },
 857         .num    = CLK_NUMBER_H3,
 858 };
 859
 860 static struct clk_hw_onecell_data sun50i_h5_hw_clks = {
 861         .hws    = {
 862                 [CLK_PLL_CPUX]          = &pll_cpux_clk.common.hw,
 863                 [CLK_PLL_AUDIO_BASE]    = &pll_audio_base_clk.common.hw,
 864                 [CLK_PLL_AUDIO]         = &pll_audio_clk.hw,
 865                 [CLK_PLL_AUDIO_2X]      = &pll_audio_2x_clk.hw,
 866                 [CLK_PLL_AUDIO_4X]      = &pll_audio_4x_clk.hw,
 867                 [CLK_PLL_AUDIO_8X]      = &pll_audio_8x_clk.hw,
 868                 [CLK_PLL_VIDEO]         = &pll_video_clk.common.hw,
 869                 [CLK_PLL_VE]            = &pll_ve_clk.common.hw,
 870                 [CLK_PLL_DDR]           = &pll_ddr_clk.common.hw,
 871                 [CLK_PLL_PERIPH0]       = &pll_periph0_clk.common.hw,
 872                 [CLK_PLL_PERIPH0_2X]    = &pll_periph0_2x_clk.hw,
 873                 [CLK_PLL_GPU]           = &pll_gpu_clk.common.hw,
 874                 [CLK_PLL_PERIPH1]       = &pll_periph1_clk.common.hw,
 875                 [CLK_PLL_DE]            = &pll_de_clk.common.hw,
 876                 [CLK_CPUX]              = &cpux_clk.common.hw,
 877                 [CLK_AXI]               = &axi_clk.common.hw,
 878                 [CLK_AHB1]              = &ahb1_clk.common.hw,
 879                 [CLK_APB1]              = &apb1_clk.common.hw,
 880                 [CLK_APB2]              = &apb2_clk.common.hw,
 881                 [CLK_AHB2]              = &ahb2_clk.common.hw,
 882                 [CLK_BUS_CE]            = &bus_ce_clk.common.hw,
 883                 [CLK_BUS_DMA]           = &bus_dma_clk.common.hw,
 884                 [CLK_BUS_MMC0]          = &bus_mmc0_clk.common.hw,
 885                 [CLK_BUS_MMC1]          = &bus_mmc1_clk.common.hw,
 886                 [CLK_BUS_MMC2]          = &bus_mmc2_clk.common.hw,
 887                 [CLK_BUS_NAND]          = &bus_nand_clk.common.hw,
 888                 [CLK_BUS_DRAM]          = &bus_dram_clk.common.hw,
 889                 [CLK_BUS_EMAC]          = &bus_emac_clk.common.hw,
 890                 [CLK_BUS_TS]            = &bus_ts_clk.common.hw,
 891                 [CLK_BUS_HSTIMER]       = &bus_hstimer_clk.common.hw,
 892                 [CLK_BUS_SPI0]          = &bus_spi0_clk.common.hw,
 893                 [CLK_BUS_SPI1]          = &bus_spi1_clk.common.hw,
 894                 [CLK_BUS_OTG]           = &bus_otg_clk.common.hw,
 895                 [CLK_BUS_EHCI0]         = &bus_ehci0_clk.common.hw,
 896                 [CLK_BUS_EHCI1]         = &bus_ehci1_clk.common.hw,
 897                 [CLK_BUS_EHCI2]         = &bus_ehci2_clk.common.hw,
 898                 [CLK_BUS_EHCI3]         = &bus_ehci3_clk.common.hw,
 899                 [CLK_BUS_OHCI0]         = &bus_ohci0_clk.common.hw,
 900                 [CLK_BUS_OHCI1]         = &bus_ohci1_clk.common.hw,
 901                 [CLK_BUS_OHCI2]         = &bus_ohci2_clk.common.hw,
 902                 [CLK_BUS_OHCI3]         = &bus_ohci3_clk.common.hw,
 903                 [CLK_BUS_VE]            = &bus_ve_clk.common.hw,
 904                 [CLK_BUS_TCON0]         = &bus_tcon0_clk.common.hw,
 905                 [CLK_BUS_TCON1]         = &bus_tcon1_clk.common.hw,
 906                 [CLK_BUS_DEINTERLACE]   = &bus_deinterlace_clk.common.hw,
 907                 [CLK_BUS_CSI]           = &bus_csi_clk.common.hw,
 908                 [CLK_BUS_TVE]           = &bus_tve_clk.common.hw,
 909                 [CLK_BUS_HDMI]          = &bus_hdmi_clk.common.hw,
 910                 [CLK_BUS_DE]            = &bus_de_clk.common.hw,
 911                 [CLK_BUS_GPU]           = &bus_gpu_clk.common.hw,
 912                 [CLK_BUS_MSGBOX]        = &bus_msgbox_clk.common.hw,
 913                 [CLK_BUS_SPINLOCK]      = &bus_spinlock_clk.common.hw,
 914                 [CLK_BUS_CODEC]         = &bus_codec_clk.common.hw,
 915                 [CLK_BUS_SPDIF]         = &bus_spdif_clk.common.hw,
 916                 [CLK_BUS_PIO]           = &bus_pio_clk.common.hw,
 917                 [CLK_BUS_THS]           = &bus_ths_clk.common.hw,
 918                 [CLK_BUS_I2S0]          = &bus_i2s0_clk.common.hw,
 919                 [CLK_BUS_I2S1]          = &bus_i2s1_clk.common.hw,
 920                 [CLK_BUS_I2S2]          = &bus_i2s2_clk.common.hw,
 921                 [CLK_BUS_I2C0]          = &bus_i2c0_clk.common.hw,
 922                 [CLK_BUS_I2C1]          = &bus_i2c1_clk.common.hw,
 923                 [CLK_BUS_I2C2]          = &bus_i2c2_clk.common.hw,
 924                 [CLK_BUS_UART0]         = &bus_uart0_clk.common.hw,
 925                 [CLK_BUS_UART1]         = &bus_uart1_clk.common.hw,
 926                 [CLK_BUS_UART2]         = &bus_uart2_clk.common.hw,
 927                 [CLK_BUS_UART3]         = &bus_uart3_clk.common.hw,
 928                 [CLK_BUS_SCR0]          = &bus_scr0_clk.common.hw,
 929                 [CLK_BUS_SCR1]          = &bus_scr1_clk.common.hw,
 930                 [CLK_BUS_EPHY]          = &bus_ephy_clk.common.hw,
 931                 [CLK_BUS_DBG]           = &bus_dbg_clk.common.hw,
 932                 [CLK_THS]               = &ths_clk.common.hw,
 933                 [CLK_NAND]              = &nand_clk.common.hw,
 934                 [CLK_MMC0]              = &mmc0_clk.common.hw,
 935                 [CLK_MMC1]              = &mmc1_clk.common.hw,
 936                 [CLK_MMC2]              = &mmc2_clk.common.hw,
 937                 [CLK_TS]                = &ts_clk.common.hw,
 938                 [CLK_CE]                = &ce_clk.common.hw,
 939                 [CLK_SPI0]              = &spi0_clk.common.hw,
 940                 [CLK_SPI1]              = &spi1_clk.common.hw,
 941                 [CLK_I2S0]              = &i2s0_clk.common.hw,
 942                 [CLK_I2S1]              = &i2s1_clk.common.hw,
 943                 [CLK_I2S2]              = &i2s2_clk.common.hw,
 944                 [CLK_SPDIF]             = &spdif_clk.common.hw,
 945                 [CLK_USB_PHY0]          = &usb_phy0_clk.common.hw,
 946                 [CLK_USB_PHY1]          = &usb_phy1_clk.common.hw,
 947                 [CLK_USB_PHY2]          = &usb_phy2_clk.common.hw,
 948                 [CLK_USB_PHY3]          = &usb_phy3_clk.common.hw,
 949                 [CLK_USB_OHCI0]         = &usb_ohci0_clk.common.hw,
 950                 [CLK_USB_OHCI1]         = &usb_ohci1_clk.common.hw,
 951                 [CLK_USB_OHCI2]         = &usb_ohci2_clk.common.hw,
 952                 [CLK_USB_OHCI3]         = &usb_ohci3_clk.common.hw,
 953                 [CLK_DRAM]              = &dram_clk.common.hw,
 954                 [CLK_DRAM_VE]           = &dram_ve_clk.common.hw,
 955                 [CLK_DRAM_CSI]          = &dram_csi_clk.common.hw,
 956                 [CLK_DRAM_DEINTERLACE]  = &dram_deinterlace_clk.common.hw,
 957                 [CLK_DRAM_TS]           = &dram_ts_clk.common.hw,
 958                 [CLK_DE]                = &de_clk.common.hw,
 959                 [CLK_TCON0]             = &tcon_clk.common.hw,
 960                 [CLK_TVE]               = &tve_clk.common.hw,
 961                 [CLK_DEINTERLACE]       = &deinterlace_clk.common.hw,
 962                 [CLK_CSI_MISC]          = &csi_misc_clk.common.hw,
 963                 [CLK_CSI_SCLK]          = &csi_sclk_clk.common.hw,
 964                 [CLK_CSI_MCLK]          = &csi_mclk_clk.common.hw,
 965                 [CLK_VE]                = &ve_clk.common.hw,
 966                 [CLK_AC_DIG]            = &ac_dig_clk.common.hw,
 967                 [CLK_AVS]               = &avs_clk.common.hw,
 968                 [CLK_HDMI]              = &hdmi_clk.common.hw,
 969                 [CLK_HDMI_DDC]          = &hdmi_ddc_clk.common.hw,
 970                 [CLK_MBUS]              = &mbus_clk.common.hw,
 971                 [CLK_GPU]               = &gpu_clk.common.hw,
 972         },
 973         .num    = CLK_NUMBER_H5,
 974 };
 975
 976 static struct ccu_reset_map sun8i_h3_ccu_resets[] = {
 977         [RST_USB_PHY0]          =  { 0x0cc, BIT(0) },
 978         [RST_USB_PHY1]          =  { 0x0cc, BIT(1) },
 979         [RST_USB_PHY2]          =  { 0x0cc, BIT(2) },
 980         [RST_USB_PHY3]          =  { 0x0cc, BIT(3) },
 981
 982         [RST_MBUS]              =  { 0x0fc, BIT(31) },
 983
 984         [RST_BUS_CE]            =  { 0x2c0, BIT(5) },
 985         [RST_BUS_DMA]           =  { 0x2c0, BIT(6) },
 986         [RST_BUS_MMC0]          =  { 0x2c0, BIT(8) },
 987         [RST_BUS_MMC1]          =  { 0x2c0, BIT(9) },
 988         [RST_BUS_MMC2]          =  { 0x2c0, BIT(10) },
 989         [RST_BUS_NAND]          =  { 0x2c0, BIT(13) },
 990         [RST_BUS_DRAM]          =  { 0x2c0, BIT(14) },
 991         [RST_BUS_EMAC]          =  { 0x2c0, BIT(17) },
 992         [RST_BUS_TS]            =  { 0x2c0, BIT(18) },
 993         [RST_BUS_HSTIMER]       =  { 0x2c0, BIT(19) },
 994         [RST_BUS_SPI0]          =  { 0x2c0, BIT(20) },
 995         [RST_BUS_SPI1]          =  { 0x2c0, BIT(21) },
 996         [RST_BUS_OTG]           =  { 0x2c0, BIT(23) },
 997         [RST_BUS_EHCI0]         =  { 0x2c0, BIT(24) },
 998         [RST_BUS_EHCI1]         =  { 0x2c0, BIT(25) },
 999         [RST_BUS_EHCI2]         =  { 0x2c0, BIT(26) },
1000         [RST_BUS_EHCI3]         =  { 0x2c0, BIT(27) },
1001         [RST_BUS_OHCI0]         =  { 0x2c0, BIT(28) },
1002         [RST_BUS_OHCI1]         =  { 0x2c0, BIT(29) },
1003         [RST_BUS_OHCI2]         =  { 0x2c0, BIT(30) },
1004         [RST_BUS_OHCI3]         =  { 0x2c0, BIT(31) },
1005
1006         [RST_BUS_VE]            =  { 0x2c4, BIT(0) },
1007         [RST_BUS_TCON0]         =  { 0x2c4, BIT(3) },
1008         [RST_BUS_TCON1]         =  { 0x2c4, BIT(4) },
1009         [RST_BUS_DEINTERLACE]   =  { 0x2c4, BIT(5) },
1010         [RST_BUS_CSI]           =  { 0x2c4, BIT(8) },
1011         [RST_BUS_TVE]           =  { 0x2c4, BIT(9) },
1012         [RST_BUS_HDMI0]         =  { 0x2c4, BIT(10) },
1013         [RST_BUS_HDMI1]         =  { 0x2c4, BIT(11) },
1014         [RST_BUS_DE]            =  { 0x2c4, BIT(12) },
1015         [RST_BUS_GPU]           =  { 0x2c4, BIT(20) },
1016         [RST_BUS_MSGBOX]        =  { 0x2c4, BIT(21) },
1017         [RST_BUS_SPINLOCK]      =  { 0x2c4, BIT(22) },
1018         [RST_BUS_DBG]           =  { 0x2c4, BIT(31) },
1019
1020         [RST_BUS_EPHY]          =  { 0x2c8, BIT(2) },
1021
1022         [RST_BUS_CODEC]         =  { 0x2d0, BIT(0) },
1023         [RST_BUS_SPDIF]         =  { 0x2d0, BIT(1) },
1024         [RST_BUS_THS]           =  { 0x2d0, BIT(8) },
1025         [RST_BUS_I2S0]          =  { 0x2d0, BIT(12) },
1026         [RST_BUS_I2S1]          =  { 0x2d0, BIT(13) },
1027         [RST_BUS_I2S2]          =  { 0x2d0, BIT(14) },
1028
1029         [RST_BUS_I2C0]          =  { 0x2d8, BIT(0) },
1030         [RST_BUS_I2C1]          =  { 0x2d8, BIT(1) },
1031         [RST_BUS_I2C2]          =  { 0x2d8, BIT(2) },
1032         [RST_BUS_UART0]         =  { 0x2d8, BIT(16) },
1033         [RST_BUS_UART1]         =  { 0x2d8, BIT(17) },
1034         [RST_BUS_UART2]         =  { 0x2d8, BIT(18) },
1035         [RST_BUS_UART3]         =  { 0x2d8, BIT(19) },
1036         [RST_BUS_SCR0]          =  { 0x2d8, BIT(20) },
1037 };
1038
1039 static struct ccu_reset_map sun50i_h5_ccu_resets[] = {
1040         [RST_USB_PHY0]          =  { 0x0cc, BIT(0) },
1041         [RST_USB_PHY1]          =  { 0x0cc, BIT(1) },
1042         [RST_USB_PHY2]          =  { 0x0cc, BIT(2) },
1043         [RST_USB_PHY3]          =  { 0x0cc, BIT(3) },
1044
1045         [RST_MBUS]              =  { 0x0fc, BIT(31) },
1046
1047         [RST_BUS_CE]            =  { 0x2c0, BIT(5) },
1048         [RST_BUS_DMA]           =  { 0x2c0, BIT(6) },
1049         [RST_BUS_MMC0]          =  { 0x2c0, BIT(8) },
1050         [RST_BUS_MMC1]          =  { 0x2c0, BIT(9) },
1051         [RST_BUS_MMC2]          =  { 0x2c0, BIT(10) },
1052         [RST_BUS_NAND]          =  { 0x2c0, BIT(13) },
1053         [RST_BUS_DRAM]          =  { 0x2c0, BIT(14) },
1054         [RST_BUS_EMAC]          =  { 0x2c0, BIT(17) },
1055         [RST_BUS_TS]            =  { 0x2c0, BIT(18) },
1056         [RST_BUS_HSTIMER]       =  { 0x2c0, BIT(19) },
1057         [RST_BUS_SPI0]          =  { 0x2c0, BIT(20) },
1058         [RST_BUS_SPI1]          =  { 0x2c0, BIT(21) },
1059         [RST_BUS_OTG]           =  { 0x2c0, BIT(23) },
1060         [RST_BUS_EHCI0]         =  { 0x2c0, BIT(24) },
1061         [RST_BUS_EHCI1]         =  { 0x2c0, BIT(25) },
1062         [RST_BUS_EHCI2]         =  { 0x2c0, BIT(26) },
1063         [RST_BUS_EHCI3]         =  { 0x2c0, BIT(27) },
1064         [RST_BUS_OHCI0]         =  { 0x2c0, BIT(28) },
1065         [RST_BUS_OHCI1]         =  { 0x2c0, BIT(29) },
1066         [RST_BUS_OHCI2]         =  { 0x2c0, BIT(30) },
1067         [RST_BUS_OHCI3]         =  { 0x2c0, BIT(31) },
1068
1069         [RST_BUS_VE]            =  { 0x2c4, BIT(0) },
1070         [RST_BUS_TCON0]         =  { 0x2c4, BIT(3) },
1071         [RST_BUS_TCON1]         =  { 0x2c4, BIT(4) },
1072         [RST_BUS_DEINTERLACE]   =  { 0x2c4, BIT(5) },
1073         [RST_BUS_CSI]           =  { 0x2c4, BIT(8) },
1074         [RST_BUS_TVE]           =  { 0x2c4, BIT(9) },
1075         [RST_BUS_HDMI0]         =  { 0x2c4, BIT(10) },
1076         [RST_BUS_HDMI1]         =  { 0x2c4, BIT(11) },
1077         [RST_BUS_DE]            =  { 0x2c4, BIT(12) },
1078         [RST_BUS_GPU]           =  { 0x2c4, BIT(20) },
1079         [RST_BUS_MSGBOX]        =  { 0x2c4, BIT(21) },
1080         [RST_BUS_SPINLOCK]      =  { 0x2c4, BIT(22) },
1081         [RST_BUS_DBG]           =  { 0x2c4, BIT(31) },
1082
1083         [RST_BUS_EPHY]          =  { 0x2c8, BIT(2) },
1084
1085         [RST_BUS_CODEC]         =  { 0x2d0, BIT(0) },
1086         [RST_BUS_SPDIF]         =  { 0x2d0, BIT(1) },
1087         [RST_BUS_THS]           =  { 0x2d0, BIT(8) },
1088         [RST_BUS_I2S0]          =  { 0x2d0, BIT(12) },
1089         [RST_BUS_I2S1]          =  { 0x2d0, BIT(13) },
1090         [RST_BUS_I2S2]          =  { 0x2d0, BIT(14) },
1091
1092         [RST_BUS_I2C0]          =  { 0x2d8, BIT(0) },
1093         [RST_BUS_I2C1]          =  { 0x2d8, BIT(1) },
1094         [RST_BUS_I2C2]          =  { 0x2d8, BIT(2) },
1095         [RST_BUS_UART0]         =  { 0x2d8, BIT(16) },
1096         [RST_BUS_UART1]         =  { 0x2d8, BIT(17) },
1097         [RST_BUS_UART2]         =  { 0x2d8, BIT(18) },
1098         [RST_BUS_UART3]         =  { 0x2d8, BIT(19) },
1099         [RST_BUS_SCR0]          =  { 0x2d8, BIT(20) },
1100         [RST_BUS_SCR1]          =  { 0x2d8, BIT(20) },
1101 };
1102
1103 static const struct sunxi_ccu_desc sun8i_h3_ccu_desc = {
1104         .ccu_clks       = sun8i_h3_ccu_clks,
1105         .num_ccu_clks   = ARRAY_SIZE(sun8i_h3_ccu_clks),
1106
1107         .hw_clks        = &sun8i_h3_hw_clks,
1108
1109         .resets         = sun8i_h3_ccu_resets,
1110         .num_resets     = ARRAY_SIZE(sun8i_h3_ccu_resets),
1111 };
1112
1113 static const struct sunxi_ccu_desc sun50i_h5_ccu_desc = {
1114         .ccu_clks       = sun50i_h5_ccu_clks,
1115         .num_ccu_clks   = ARRAY_SIZE(sun50i_h5_ccu_clks),
1116
1117         .hw_clks        = &sun50i_h5_hw_clks,
1118
1119         .resets         = sun50i_h5_ccu_resets,
1120         .num_resets     = ARRAY_SIZE(sun50i_h5_ccu_resets),
1121 };
1122
1123 static struct ccu_pll_nb sun8i_h3_pll_cpu_nb = {
1124         .common = &pll_cpux_clk.common,
1125         /* copy from pll_cpux_clk */
1126         .enable = BIT(31),
1127         .lock   = BIT(28),
1128 };
1129
1130 static struct ccu_mux_nb sun8i_h3_cpu_nb = {
1131         .common         = &cpux_clk.common,
1132         .cm             = &cpux_clk.mux,
1133         .delay_us       = 1, /* > 8 clock cycles at 24 MHz */
1134         .bypass_index   = 1, /* index of 24 MHz oscillator */
1135 };
1136
1137 static void __init sunxi_h3_h5_ccu_init(struct device_node *node,
1138                                         const struct sunxi_ccu_desc *desc)
1139 {
1140         void __iomem *reg;
1141         u32 val;
1142
1143         reg = of_io_request_and_map(node, 0, of_node_full_name(node));
1144         if (IS_ERR(reg)) {
1145                 pr_err("%pOF: Could not map the clock registers\n", node);
1146                 return;
1147         }
1148
1149         /* Force the PLL-Audio-1x divider to 1 */
1150         val = readl(reg + SUN8I_H3_PLL_AUDIO_REG);
1151         val &= ~GENMASK(19, 16);
1152         writel(val | (0 << 16), reg + SUN8I_H3_PLL_AUDIO_REG);
1153
1154         sunxi_ccu_probe(node, reg, desc);
1155
1156         /* Gate then ungate PLL CPU after any rate changes */
1157         ccu_pll_notifier_register(&sun8i_h3_pll_cpu_nb);
1158
1159         /* Reparent CPU during PLL CPU rate changes */
1160         ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
1161                                   &sun8i_h3_cpu_nb);
1162 }
1163
1164 static void __init sun8i_h3_ccu_setup(struct device_node *node)
1165 {
1166         sunxi_h3_h5_ccu_init(node, &sun8i_h3_ccu_desc);
1167 }
1168 CLK_OF_DECLARE(sun8i_h3_ccu, "allwinner,sun8i-h3-ccu",
1169                sun8i_h3_ccu_setup);
1170
1171 static void __init sun50i_h5_ccu_setup(struct device_node *node)
1172 {
1173         sunxi_h3_h5_ccu_init(node, &sun50i_h5_ccu_desc);
1174 }
1175 CLK_OF_DECLARE(sun50i_h5_ccu, "allwinner,sun50i-h5-ccu",
1176                sun50i_h5_ccu_setup);