GNU Linux-libre 4.19.314-gnu1
[releases.git] / drivers / clk / sunxi-ng / ccu-sun8i-a83t.c
1 /*
2  * Copyright (c) 2017 Chen-Yu Tsai. All rights reserved.
3  *
4  * This software is licensed under the terms of the GNU General Public
5  * License version 2, as published by the Free Software Foundation, and
6  * may be copied, distributed, and modified under those terms.
7  *
8  * This program is distributed in the hope that it will be useful,
9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11  * GNU General Public License for more details.
12  */
13
14 #include <linux/clk-provider.h>
15 #include <linux/of_address.h>
16 #include <linux/platform_device.h>
17
18 #include "ccu_common.h"
19 #include "ccu_reset.h"
20
21 #include "ccu_div.h"
22 #include "ccu_gate.h"
23 #include "ccu_mp.h"
24 #include "ccu_mux.h"
25 #include "ccu_nkmp.h"
26 #include "ccu_nm.h"
27 #include "ccu_phase.h"
28
29 #include "ccu-sun8i-a83t.h"
30
31 #define CCU_SUN8I_A83T_LOCK_REG 0x20c
32
33 /*
34  * The CPU PLLs are actually NP clocks, with P being /1 or /4. However
35  * P should only be used for output frequencies lower than 228 MHz.
36  * Neither mainline Linux, U-boot, nor the vendor BSPs use these.
37  *
38  * For now we can just model it as a multiplier clock, and force P to /1.
39  */
40 #define SUN8I_A83T_PLL_C0CPUX_REG       0x000
41 #define SUN8I_A83T_PLL_C1CPUX_REG       0x004
42
43 static struct ccu_mult pll_c0cpux_clk = {
44         .enable         = BIT(31),
45         .lock           = BIT(0),
46         .mult           = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
47         .common         = {
48                 .reg            = SUN8I_A83T_PLL_C0CPUX_REG,
49                 .lock_reg       = CCU_SUN8I_A83T_LOCK_REG,
50                 .features       = CCU_FEATURE_LOCK_REG,
51                 .hw.init        = CLK_HW_INIT("pll-c0cpux", "osc24M",
52                                               &ccu_mult_ops,
53                                               CLK_SET_RATE_UNGATE),
54         },
55 };
56
57 static struct ccu_mult pll_c1cpux_clk = {
58         .enable         = BIT(31),
59         .lock           = BIT(1),
60         .mult           = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
61         .common         = {
62                 .reg            = SUN8I_A83T_PLL_C1CPUX_REG,
63                 .lock_reg       = CCU_SUN8I_A83T_LOCK_REG,
64                 .features       = CCU_FEATURE_LOCK_REG,
65                 .hw.init        = CLK_HW_INIT("pll-c1cpux", "osc24M",
66                                               &ccu_mult_ops,
67                                               CLK_SET_RATE_UNGATE),
68         },
69 };
70
71 /*
72  * The Audio PLL has d1, d2 dividers in addition to the usual N, M
73  * factors. Since we only need 2 frequencies from this PLL: 22.5792 MHz
74  * and 24.576 MHz, ignore them for now. Enforce the default for them,
75  * which is d1 = 0, d2 = 1.
76  */
77 #define SUN8I_A83T_PLL_AUDIO_REG        0x008
78
79 /* clock rates doubled for post divider */
80 static struct ccu_sdm_setting pll_audio_sdm_table[] = {
81         { .rate = 45158400, .pattern = 0xc00121ff, .m = 29, .n = 54 },
82         { .rate = 49152000, .pattern = 0xc000e147, .m = 30, .n = 61 },
83 };
84
85 static struct ccu_nm pll_audio_clk = {
86         .enable         = BIT(31),
87         .lock           = BIT(2),
88         .n              = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
89         .m              = _SUNXI_CCU_DIV(0, 6),
90         .fixed_post_div = 2,
91         .sdm            = _SUNXI_CCU_SDM(pll_audio_sdm_table, BIT(24),
92                                          0x284, BIT(31)),
93         .common         = {
94                 .reg            = SUN8I_A83T_PLL_AUDIO_REG,
95                 .lock_reg       = CCU_SUN8I_A83T_LOCK_REG,
96                 .features       = CCU_FEATURE_LOCK_REG |
97                                   CCU_FEATURE_FIXED_POSTDIV |
98                                   CCU_FEATURE_SIGMA_DELTA_MOD,
99                 .hw.init        = CLK_HW_INIT("pll-audio", "osc24M",
100                                               &ccu_nm_ops, CLK_SET_RATE_UNGATE),
101         },
102 };
103
104 /* Some PLLs are input * N / div1 / P. Model them as NKMP with no K */
105 static struct ccu_nkmp pll_video0_clk = {
106         .enable         = BIT(31),
107         .lock           = BIT(3),
108         .n              = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
109         .m              = _SUNXI_CCU_DIV(16, 1), /* input divider */
110         .p              = _SUNXI_CCU_DIV(0, 2), /* output divider */
111         .common         = {
112                 .reg            = 0x010,
113                 .lock_reg       = CCU_SUN8I_A83T_LOCK_REG,
114                 .features       = CCU_FEATURE_LOCK_REG,
115                 .hw.init        = CLK_HW_INIT("pll-video0", "osc24M",
116                                               &ccu_nkmp_ops,
117                                               CLK_SET_RATE_UNGATE),
118         },
119 };
120
121 static struct ccu_nkmp pll_ve_clk = {
122         .enable         = BIT(31),
123         .lock           = BIT(4),
124         .n              = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
125         .m              = _SUNXI_CCU_DIV(16, 1), /* input divider */
126         .p              = _SUNXI_CCU_DIV(18, 1), /* output divider */
127         .common         = {
128                 .reg            = 0x018,
129                 .lock_reg       = CCU_SUN8I_A83T_LOCK_REG,
130                 .features       = CCU_FEATURE_LOCK_REG,
131                 .hw.init        = CLK_HW_INIT("pll-ve", "osc24M",
132                                               &ccu_nkmp_ops,
133                                               CLK_SET_RATE_UNGATE),
134         },
135 };
136
137 static struct ccu_nkmp pll_ddr_clk = {
138         .enable         = BIT(31),
139         .lock           = BIT(5),
140         .n              = _SUNXI_CCU_MULT_MIN(8, 8, 12),
141         .m              = _SUNXI_CCU_DIV(16, 1), /* input divider */
142         .p              = _SUNXI_CCU_DIV(18, 1), /* output divider */
143         .common         = {
144                 .reg            = 0x020,
145                 .lock_reg       = CCU_SUN8I_A83T_LOCK_REG,
146                 .features       = CCU_FEATURE_LOCK_REG,
147                 .hw.init        = CLK_HW_INIT("pll-ddr", "osc24M",
148                                               &ccu_nkmp_ops,
149                                               CLK_SET_RATE_UNGATE),
150         },
151 };
152
153 static struct ccu_nkmp pll_periph_clk = {
154         .enable         = BIT(31),
155         .lock           = BIT(6),
156         .n              = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
157         .m              = _SUNXI_CCU_DIV(16, 1), /* input divider */
158         .p              = _SUNXI_CCU_DIV(18, 1), /* output divider */
159         .common         = {
160                 .reg            = 0x028,
161                 .lock_reg       = CCU_SUN8I_A83T_LOCK_REG,
162                 .features       = CCU_FEATURE_LOCK_REG,
163                 .hw.init        = CLK_HW_INIT("pll-periph", "osc24M",
164                                               &ccu_nkmp_ops,
165                                               CLK_SET_RATE_UNGATE),
166         },
167 };
168
169 static struct ccu_nkmp pll_gpu_clk = {
170         .enable         = BIT(31),
171         .lock           = BIT(7),
172         .n              = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
173         .m              = _SUNXI_CCU_DIV(16, 1), /* input divider */
174         .p              = _SUNXI_CCU_DIV(18, 1), /* output divider */
175         .common         = {
176                 .reg            = 0x038,
177                 .lock_reg       = CCU_SUN8I_A83T_LOCK_REG,
178                 .features       = CCU_FEATURE_LOCK_REG,
179                 .hw.init        = CLK_HW_INIT("pll-gpu", "osc24M",
180                                               &ccu_nkmp_ops,
181                                               CLK_SET_RATE_UNGATE),
182         },
183 };
184
185 static struct ccu_nkmp pll_hsic_clk = {
186         .enable         = BIT(31),
187         .lock           = BIT(8),
188         .n              = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
189         .m              = _SUNXI_CCU_DIV(16, 1), /* input divider */
190         .p              = _SUNXI_CCU_DIV(18, 1), /* output divider */
191         .common         = {
192                 .reg            = 0x044,
193                 .lock_reg       = CCU_SUN8I_A83T_LOCK_REG,
194                 .features       = CCU_FEATURE_LOCK_REG,
195                 .hw.init        = CLK_HW_INIT("pll-hsic", "osc24M",
196                                               &ccu_nkmp_ops,
197                                               CLK_SET_RATE_UNGATE),
198         },
199 };
200
201 static struct ccu_nkmp pll_de_clk = {
202         .enable         = BIT(31),
203         .lock           = BIT(9),
204         .n              = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
205         .m              = _SUNXI_CCU_DIV(16, 1), /* input divider */
206         .p              = _SUNXI_CCU_DIV(18, 1), /* output divider */
207         .common         = {
208                 .reg            = 0x048,
209                 .lock_reg       = CCU_SUN8I_A83T_LOCK_REG,
210                 .features       = CCU_FEATURE_LOCK_REG,
211                 .hw.init        = CLK_HW_INIT("pll-de", "osc24M",
212                                               &ccu_nkmp_ops,
213                                               CLK_SET_RATE_UNGATE),
214         },
215 };
216
217 static struct ccu_nkmp pll_video1_clk = {
218         .enable         = BIT(31),
219         .lock           = BIT(10),
220         .n              = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
221         .m              = _SUNXI_CCU_DIV(16, 1), /* input divider */
222         .p              = _SUNXI_CCU_DIV(0, 2), /* external divider p */
223         .common         = {
224                 .reg            = 0x04c,
225                 .lock_reg       = CCU_SUN8I_A83T_LOCK_REG,
226                 .features       = CCU_FEATURE_LOCK_REG,
227                 .hw.init        = CLK_HW_INIT("pll-video1", "osc24M",
228                                               &ccu_nkmp_ops,
229                                               CLK_SET_RATE_UNGATE),
230         },
231 };
232
233 static const char * const c0cpux_parents[] = { "osc24M", "pll-c0cpux" };
234 static SUNXI_CCU_MUX(c0cpux_clk, "c0cpux", c0cpux_parents,
235                      0x50, 12, 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
236
237 static const char * const c1cpux_parents[] = { "osc24M", "pll-c1cpux" };
238 static SUNXI_CCU_MUX(c1cpux_clk, "c1cpux", c1cpux_parents,
239                      0x50, 28, 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
240
241 static SUNXI_CCU_M(axi0_clk, "axi0", "c0cpux", 0x050, 0, 2, 0);
242 static SUNXI_CCU_M(axi1_clk, "axi1", "c1cpux", 0x050, 16, 2, 0);
243
244 static const char * const ahb1_parents[] = { "osc16M-d512", "osc24M",
245                                              "pll-periph",
246                                              "pll-periph" };
247 static const struct ccu_mux_var_prediv ahb1_predivs[] = {
248         { .index = 2, .shift = 6, .width = 2 },
249         { .index = 3, .shift = 6, .width = 2 },
250 };
251 static struct ccu_div ahb1_clk = {
252         .div            = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
253         .mux            = {
254                 .shift  = 12,
255                 .width  = 2,
256
257                 .var_predivs    = ahb1_predivs,
258                 .n_var_predivs  = ARRAY_SIZE(ahb1_predivs),
259         },
260         .common         = {
261                 .reg            = 0x054,
262                 .hw.init        = CLK_HW_INIT_PARENTS("ahb1",
263                                                       ahb1_parents,
264                                                       &ccu_div_ops,
265                                                       0),
266         },
267 };
268
269 static SUNXI_CCU_M(apb1_clk, "apb1", "ahb1", 0x054, 8, 2, 0);
270
271 static const char * const apb2_parents[] = { "osc16M-d512", "osc24M",
272                                              "pll-periph", "pll-periph" };
273
274 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
275                              0, 5,      /* M */
276                              16, 2,     /* P */
277                              24, 2,     /* mux */
278                              0);
279
280 static const char * const ahb2_parents[] = { "ahb1", "pll-periph" };
281 static const struct ccu_mux_fixed_prediv ahb2_prediv = {
282         .index = 1, .div = 2
283 };
284 static struct ccu_mux ahb2_clk = {
285         .mux            = {
286                 .shift          = 0,
287                 .width          = 2,
288                 .fixed_predivs  = &ahb2_prediv,
289                 .n_predivs      = 1,
290         },
291         .common         = {
292                 .reg            = 0x05c,
293                 .hw.init        = CLK_HW_INIT_PARENTS("ahb2",
294                                                       ahb2_parents,
295                                                       &ccu_mux_ops,
296                                                       0),
297         },
298 };
299
300 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
301                       0x060, BIT(1), 0);
302 static SUNXI_CCU_GATE(bus_ss_clk,       "bus-ss",       "ahb1",
303                       0x060, BIT(5), 0);
304 static SUNXI_CCU_GATE(bus_dma_clk,      "bus-dma",      "ahb1",
305                       0x060, BIT(6), 0);
306 static SUNXI_CCU_GATE(bus_mmc0_clk,     "bus-mmc0",     "ahb1",
307                       0x060, BIT(8), 0);
308 static SUNXI_CCU_GATE(bus_mmc1_clk,     "bus-mmc1",     "ahb1",
309                       0x060, BIT(9), 0);
310 static SUNXI_CCU_GATE(bus_mmc2_clk,     "bus-mmc2",     "ahb1",
311                       0x060, BIT(10), 0);
312 static SUNXI_CCU_GATE(bus_nand_clk,     "bus-nand",     "ahb1",
313                       0x060, BIT(13), 0);
314 static SUNXI_CCU_GATE(bus_dram_clk,     "bus-dram",     "ahb1",
315                       0x060, BIT(14), 0);
316 static SUNXI_CCU_GATE(bus_emac_clk,     "bus-emac",     "ahb2",
317                       0x060, BIT(17), 0);
318 static SUNXI_CCU_GATE(bus_hstimer_clk,  "bus-hstimer",  "ahb1",
319                       0x060, BIT(19), 0);
320 static SUNXI_CCU_GATE(bus_spi0_clk,     "bus-spi0",     "ahb1",
321                       0x060, BIT(20), 0);
322 static SUNXI_CCU_GATE(bus_spi1_clk,     "bus-spi1",     "ahb1",
323                       0x060, BIT(21), 0);
324 static SUNXI_CCU_GATE(bus_otg_clk,      "bus-otg",      "ahb1",
325                       0x060, BIT(24), 0);
326 static SUNXI_CCU_GATE(bus_ehci0_clk,    "bus-ehci0",    "ahb2",
327                       0x060, BIT(26), 0);
328 static SUNXI_CCU_GATE(bus_ehci1_clk,    "bus-ehci1",    "ahb2",
329                       0x060, BIT(27), 0);
330 static SUNXI_CCU_GATE(bus_ohci0_clk,    "bus-ohci0",    "ahb2",
331                       0x060, BIT(29), 0);
332
333 static SUNXI_CCU_GATE(bus_ve_clk,       "bus-ve",       "ahb1",
334                       0x064, BIT(0), 0);
335 static SUNXI_CCU_GATE(bus_tcon0_clk,    "bus-tcon0",    "ahb1",
336                       0x064, BIT(4), 0);
337 static SUNXI_CCU_GATE(bus_tcon1_clk,    "bus-tcon1",    "ahb1",
338                       0x064, BIT(5), 0);
339 static SUNXI_CCU_GATE(bus_csi_clk,      "bus-csi",      "ahb1",
340                       0x064, BIT(8), 0);
341 static SUNXI_CCU_GATE(bus_hdmi_clk,     "bus-hdmi",     "ahb1",
342                       0x064, BIT(11), 0);
343 static SUNXI_CCU_GATE(bus_de_clk,       "bus-de",       "ahb1",
344                       0x064, BIT(12), 0);
345 static SUNXI_CCU_GATE(bus_gpu_clk,      "bus-gpu",      "ahb1",
346                       0x064, BIT(20), 0);
347 static SUNXI_CCU_GATE(bus_msgbox_clk,   "bus-msgbox",   "ahb1",
348                       0x064, BIT(21), 0);
349 static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",
350                       0x064, BIT(22), 0);
351
352 static SUNXI_CCU_GATE(bus_spdif_clk,    "bus-spdif",    "apb1",
353                       0x068, BIT(1), 0);
354 static SUNXI_CCU_GATE(bus_pio_clk,      "bus-pio",      "apb1",
355                       0x068, BIT(5), 0);
356 static SUNXI_CCU_GATE(bus_i2s0_clk,     "bus-i2s0",     "apb1",
357                       0x068, BIT(12), 0);
358 static SUNXI_CCU_GATE(bus_i2s1_clk,     "bus-i2s1",     "apb1",
359                       0x068, BIT(13), 0);
360 static SUNXI_CCU_GATE(bus_i2s2_clk,     "bus-i2s2",     "apb1",
361                       0x068, BIT(14), 0);
362 static SUNXI_CCU_GATE(bus_tdm_clk,      "bus-tdm",      "apb1",
363                       0x068, BIT(15), 0);
364
365 static SUNXI_CCU_GATE(bus_i2c0_clk,     "bus-i2c0",     "apb2",
366                       0x06c, BIT(0), 0);
367 static SUNXI_CCU_GATE(bus_i2c1_clk,     "bus-i2c1",     "apb2",
368                       0x06c, BIT(1), 0);
369 static SUNXI_CCU_GATE(bus_i2c2_clk,     "bus-i2c2",     "apb2",
370                       0x06c, BIT(2), 0);
371 static SUNXI_CCU_GATE(bus_uart0_clk,    "bus-uart0",    "apb2",
372                       0x06c, BIT(16), 0);
373 static SUNXI_CCU_GATE(bus_uart1_clk,    "bus-uart1",    "apb2",
374                       0x06c, BIT(17), 0);
375 static SUNXI_CCU_GATE(bus_uart2_clk,    "bus-uart2",    "apb2",
376                       0x06c, BIT(18), 0);
377 static SUNXI_CCU_GATE(bus_uart3_clk,    "bus-uart3",    "apb2",
378                       0x06c, BIT(19), 0);
379 static SUNXI_CCU_GATE(bus_uart4_clk,    "bus-uart4",    "apb2",
380                       0x06c, BIT(20), 0);
381
382 static const char * const cci400_parents[] = { "osc24M", "pll-periph",
383                                                "pll-hsic" };
384 static struct ccu_div cci400_clk = {
385         .div            = _SUNXI_CCU_DIV_FLAGS(0, 2, 0),
386         .mux            = _SUNXI_CCU_MUX(24, 2),
387         .common         = {
388                 .reg            = 0x078,
389                 .hw.init        = CLK_HW_INIT_PARENTS("cci400",
390                                                       cci400_parents,
391                                                       &ccu_div_ops,
392                                                       CLK_IS_CRITICAL),
393         },
394 };
395
396 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" };
397
398 static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents,
399                                   0x080,
400                                   0, 4,         /* M */
401                                   16, 2,        /* P */
402                                   24, 2,        /* mux */
403                                   BIT(31),      /* gate */
404                                   0);
405
406 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents,
407                                   0x088,
408                                   0, 4,         /* M */
409                                   16, 2,        /* P */
410                                   24, 2,        /* mux */
411                                   BIT(31),      /* gate */
412                                   0);
413
414 static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0-sample", "mmc0",
415                        0x088, 20, 3, 0);
416 static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0-output", "mmc0",
417                        0x088, 8, 3, 0);
418
419 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents,
420                                   0x08c,
421                                   0, 4,         /* M */
422                                   16, 2,        /* P */
423                                   24, 2,        /* mux */
424                                   BIT(31),      /* gate */
425                                   0);
426
427 static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1-sample", "mmc1",
428                        0x08c, 20, 3, 0);
429 static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1-output", "mmc1",
430                        0x08c, 8, 3, 0);
431
432 static SUNXI_CCU_MP_MMC_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents,
433                                       0x090, 0);
434
435 static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2-sample", "mmc2",
436                        0x090, 20, 3, 0);
437 static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2-output", "mmc2",
438                        0x090, 8, 3, 0);
439
440 static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents,
441                                   0x09c,
442                                   0, 4,         /* M */
443                                   16, 2,        /* P */
444                                   24, 2,        /* mux */
445                                   BIT(31),      /* gate */
446                                   0);
447
448 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents,
449                                   0x0a0,
450                                   0, 4,         /* M */
451                                   16, 2,        /* P */
452                                   24, 4,        /* mux */
453                                   BIT(31),      /* gate */
454                                   0);
455
456 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents,
457                                   0x0a4,
458                                   0, 4,         /* M */
459                                   16, 2,        /* P */
460                                   24, 4,        /* mux */
461                                   BIT(31),      /* gate */
462                                   0);
463
464 static SUNXI_CCU_M_WITH_GATE(i2s0_clk, "i2s0", "pll-audio",
465                              0x0b0, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
466 static SUNXI_CCU_M_WITH_GATE(i2s1_clk, "i2s1", "pll-audio",
467                              0x0b4, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
468 static SUNXI_CCU_M_WITH_GATE(i2s2_clk, "i2s2", "pll-audio",
469                              0x0b8, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
470 static SUNXI_CCU_M_WITH_GATE(tdm_clk, "tdm", "pll-audio",
471                              0x0bc, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
472 static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio",
473                              0x0c0, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
474
475 static SUNXI_CCU_GATE(usb_phy0_clk,     "usb-phy0",     "osc24M",
476                       0x0cc, BIT(8), 0);
477 static SUNXI_CCU_GATE(usb_phy1_clk,     "usb-phy1",     "osc24M",
478                       0x0cc, BIT(9), 0);
479 static SUNXI_CCU_GATE(usb_hsic_clk,     "usb-hsic",     "pll-hsic",
480                       0x0cc, BIT(10), 0);
481 static struct ccu_gate usb_hsic_12m_clk = {
482         .enable = BIT(11),
483         .common = {
484                 .reg            = 0x0cc,
485                 .prediv         = 2,
486                 .features       = CCU_FEATURE_ALL_PREDIV,
487                 .hw.init        = CLK_HW_INIT("usb-hsic-12m", "osc24M",
488                                               &ccu_gate_ops, 0),
489         }
490 };
491 static SUNXI_CCU_GATE(usb_ohci0_clk,    "usb-ohci0",    "osc24M",
492                       0x0cc, BIT(16), 0);
493
494 /* TODO divider has minimum of 2 */
495 static SUNXI_CCU_M(dram_clk, "dram", "pll-ddr", 0x0f4, 0, 4, CLK_IS_CRITICAL);
496
497 static SUNXI_CCU_GATE(dram_ve_clk,      "dram-ve",      "dram",
498                       0x100, BIT(0), 0);
499 static SUNXI_CCU_GATE(dram_csi_clk,     "dram-csi",     "dram",
500                       0x100, BIT(1), 0);
501
502 static const char * const tcon0_parents[] = { "pll-video0" };
503 static SUNXI_CCU_MUX_WITH_GATE(tcon0_clk, "tcon0", tcon0_parents,
504                                  0x118, 24, 3, BIT(31), CLK_SET_RATE_PARENT);
505
506 static const char * const tcon1_parents[] = { "pll-video1" };
507 static SUNXI_CCU_M_WITH_MUX_GATE(tcon1_clk, "tcon1", tcon1_parents,
508                                  0x11c, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
509
510 static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M", 0x130, BIT(16), 0);
511
512 static SUNXI_CCU_GATE(mipi_csi_clk, "mipi-csi", "osc24M", 0x130, BIT(31), 0);
513
514 static const char * const csi_mclk_parents[] = { "pll-de", "osc24M" };
515 static const u8 csi_mclk_table[] = { 3, 5 };
516 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_mclk_clk, "csi-mclk",
517                                        csi_mclk_parents, csi_mclk_table,
518                                        0x134,
519                                        0, 5,    /* M */
520                                        8, 3,    /* mux */
521                                        BIT(15), /* gate */
522                                        0);
523
524 static const char * const csi_sclk_parents[] = { "pll-periph", "pll-ve" };
525 static const u8 csi_sclk_table[] = { 0, 5 };
526 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_sclk_clk, "csi-sclk",
527                                        csi_sclk_parents, csi_sclk_table,
528                                        0x134,
529                                        16, 4,   /* M */
530                                        24, 3,   /* mux */
531                                        BIT(31), /* gate */
532                                        0);
533
534 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", 0x13c,
535                              16, 3, BIT(31), CLK_SET_RATE_PARENT);
536
537 static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 0x144, BIT(31), 0);
538
539 static const char * const hdmi_parents[] = { "pll-video1" };
540 static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
541                                  0x150,
542                                  0, 4,  /* M */
543                                  24, 2, /* mux */
544                                  BIT(31),       /* gate */
545                                  CLK_SET_RATE_PARENT);
546
547 static SUNXI_CCU_GATE(hdmi_slow_clk, "hdmi-slow", "osc24M", 0x154, BIT(31), 0);
548
549 static const char * const mbus_parents[] = { "osc24M", "pll-periph",
550                                              "pll-ddr" };
551 static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
552                                  0x15c,
553                                  0, 3,  /* M */
554                                  24, 2, /* mux */
555                                  BIT(31),       /* gate */
556                                  CLK_IS_CRITICAL);
557
558 static const char * const mipi_dsi0_parents[] = { "pll-video0" };
559 static const u8 mipi_dsi0_table[] = { 8 };
560 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(mipi_dsi0_clk, "mipi-dsi0",
561                                        mipi_dsi0_parents, mipi_dsi0_table,
562                                        0x168,
563                                        0, 4,    /* M */
564                                        24, 4,   /* mux */
565                                        BIT(31), /* gate */
566                                        CLK_SET_RATE_PARENT);
567
568 static const char * const mipi_dsi1_parents[] = { "osc24M", "pll-video0" };
569 static const u8 mipi_dsi1_table[] = { 0, 9 };
570 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(mipi_dsi1_clk, "mipi-dsi1",
571                                        mipi_dsi1_parents, mipi_dsi1_table,
572                                        0x16c,
573                                        0, 4,    /* M */
574                                        24, 4,   /* mux */
575                                        BIT(31), /* gate */
576                                        CLK_SET_RATE_PARENT);
577
578 static SUNXI_CCU_M_WITH_GATE(gpu_core_clk, "gpu-core", "pll-gpu", 0x1a0,
579                              0, 3, BIT(31), CLK_SET_RATE_PARENT);
580
581 static const char * const gpu_memory_parents[] = { "pll-gpu", "pll-ddr" };
582 static SUNXI_CCU_M_WITH_MUX_GATE(gpu_memory_clk, "gpu-memory",
583                                  gpu_memory_parents,
584                                  0x1a4,
585                                  0, 3,          /* M */
586                                  24, 1,         /* mux */
587                                  BIT(31),       /* gate */
588                                  CLK_SET_RATE_PARENT);
589
590 static SUNXI_CCU_M_WITH_GATE(gpu_hyd_clk, "gpu-hyd", "pll-gpu", 0x1a8,
591                              0, 3, BIT(31), CLK_SET_RATE_PARENT);
592
593 static struct ccu_common *sun8i_a83t_ccu_clks[] = {
594         &pll_c0cpux_clk.common,
595         &pll_c1cpux_clk.common,
596         &pll_audio_clk.common,
597         &pll_video0_clk.common,
598         &pll_ve_clk.common,
599         &pll_ddr_clk.common,
600         &pll_periph_clk.common,
601         &pll_gpu_clk.common,
602         &pll_hsic_clk.common,
603         &pll_de_clk.common,
604         &pll_video1_clk.common,
605         &c0cpux_clk.common,
606         &c1cpux_clk.common,
607         &axi0_clk.common,
608         &axi1_clk.common,
609         &ahb1_clk.common,
610         &ahb2_clk.common,
611         &apb1_clk.common,
612         &apb2_clk.common,
613         &bus_mipi_dsi_clk.common,
614         &bus_ss_clk.common,
615         &bus_dma_clk.common,
616         &bus_mmc0_clk.common,
617         &bus_mmc1_clk.common,
618         &bus_mmc2_clk.common,
619         &bus_nand_clk.common,
620         &bus_dram_clk.common,
621         &bus_emac_clk.common,
622         &bus_hstimer_clk.common,
623         &bus_spi0_clk.common,
624         &bus_spi1_clk.common,
625         &bus_otg_clk.common,
626         &bus_ehci0_clk.common,
627         &bus_ehci1_clk.common,
628         &bus_ohci0_clk.common,
629         &bus_ve_clk.common,
630         &bus_tcon0_clk.common,
631         &bus_tcon1_clk.common,
632         &bus_csi_clk.common,
633         &bus_hdmi_clk.common,
634         &bus_de_clk.common,
635         &bus_gpu_clk.common,
636         &bus_msgbox_clk.common,
637         &bus_spinlock_clk.common,
638         &bus_spdif_clk.common,
639         &bus_pio_clk.common,
640         &bus_i2s0_clk.common,
641         &bus_i2s1_clk.common,
642         &bus_i2s2_clk.common,
643         &bus_tdm_clk.common,
644         &bus_i2c0_clk.common,
645         &bus_i2c1_clk.common,
646         &bus_i2c2_clk.common,
647         &bus_uart0_clk.common,
648         &bus_uart1_clk.common,
649         &bus_uart2_clk.common,
650         &bus_uart3_clk.common,
651         &bus_uart4_clk.common,
652         &cci400_clk.common,
653         &nand_clk.common,
654         &mmc0_clk.common,
655         &mmc0_sample_clk.common,
656         &mmc0_output_clk.common,
657         &mmc1_clk.common,
658         &mmc1_sample_clk.common,
659         &mmc1_output_clk.common,
660         &mmc2_clk.common,
661         &mmc2_sample_clk.common,
662         &mmc2_output_clk.common,
663         &ss_clk.common,
664         &spi0_clk.common,
665         &spi1_clk.common,
666         &i2s0_clk.common,
667         &i2s1_clk.common,
668         &i2s2_clk.common,
669         &tdm_clk.common,
670         &spdif_clk.common,
671         &usb_phy0_clk.common,
672         &usb_phy1_clk.common,
673         &usb_hsic_clk.common,
674         &usb_hsic_12m_clk.common,
675         &usb_ohci0_clk.common,
676         &dram_clk.common,
677         &dram_ve_clk.common,
678         &dram_csi_clk.common,
679         &tcon0_clk.common,
680         &tcon1_clk.common,
681         &csi_misc_clk.common,
682         &mipi_csi_clk.common,
683         &csi_mclk_clk.common,
684         &csi_sclk_clk.common,
685         &ve_clk.common,
686         &avs_clk.common,
687         &hdmi_clk.common,
688         &hdmi_slow_clk.common,
689         &mbus_clk.common,
690         &mipi_dsi0_clk.common,
691         &mipi_dsi1_clk.common,
692         &gpu_core_clk.common,
693         &gpu_memory_clk.common,
694         &gpu_hyd_clk.common,
695 };
696
697 static struct clk_hw_onecell_data sun8i_a83t_hw_clks = {
698         .hws    = {
699                 [CLK_PLL_C0CPUX]        = &pll_c0cpux_clk.common.hw,
700                 [CLK_PLL_C1CPUX]        = &pll_c1cpux_clk.common.hw,
701                 [CLK_PLL_AUDIO]         = &pll_audio_clk.common.hw,
702                 [CLK_PLL_VIDEO0]        = &pll_video0_clk.common.hw,
703                 [CLK_PLL_VE]            = &pll_ve_clk.common.hw,
704                 [CLK_PLL_DDR]           = &pll_ddr_clk.common.hw,
705                 [CLK_PLL_PERIPH]        = &pll_periph_clk.common.hw,
706                 [CLK_PLL_GPU]           = &pll_gpu_clk.common.hw,
707                 [CLK_PLL_HSIC]          = &pll_hsic_clk.common.hw,
708                 [CLK_PLL_DE]            = &pll_de_clk.common.hw,
709                 [CLK_PLL_VIDEO1]        = &pll_video1_clk.common.hw,
710                 [CLK_C0CPUX]            = &c0cpux_clk.common.hw,
711                 [CLK_C1CPUX]            = &c1cpux_clk.common.hw,
712                 [CLK_AXI0]              = &axi0_clk.common.hw,
713                 [CLK_AXI1]              = &axi1_clk.common.hw,
714                 [CLK_AHB1]              = &ahb1_clk.common.hw,
715                 [CLK_AHB2]              = &ahb2_clk.common.hw,
716                 [CLK_APB1]              = &apb1_clk.common.hw,
717                 [CLK_APB2]              = &apb2_clk.common.hw,
718                 [CLK_BUS_MIPI_DSI]      = &bus_mipi_dsi_clk.common.hw,
719                 [CLK_BUS_SS]            = &bus_ss_clk.common.hw,
720                 [CLK_BUS_DMA]           = &bus_dma_clk.common.hw,
721                 [CLK_BUS_MMC0]          = &bus_mmc0_clk.common.hw,
722                 [CLK_BUS_MMC1]          = &bus_mmc1_clk.common.hw,
723                 [CLK_BUS_MMC2]          = &bus_mmc2_clk.common.hw,
724                 [CLK_BUS_NAND]          = &bus_nand_clk.common.hw,
725                 [CLK_BUS_DRAM]          = &bus_dram_clk.common.hw,
726                 [CLK_BUS_EMAC]          = &bus_emac_clk.common.hw,
727                 [CLK_BUS_HSTIMER]       = &bus_hstimer_clk.common.hw,
728                 [CLK_BUS_SPI0]          = &bus_spi0_clk.common.hw,
729                 [CLK_BUS_SPI1]          = &bus_spi1_clk.common.hw,
730                 [CLK_BUS_OTG]           = &bus_otg_clk.common.hw,
731                 [CLK_BUS_EHCI0]         = &bus_ehci0_clk.common.hw,
732                 [CLK_BUS_EHCI1]         = &bus_ehci1_clk.common.hw,
733                 [CLK_BUS_OHCI0]         = &bus_ohci0_clk.common.hw,
734                 [CLK_BUS_VE]            = &bus_ve_clk.common.hw,
735                 [CLK_BUS_TCON0]         = &bus_tcon0_clk.common.hw,
736                 [CLK_BUS_TCON1]         = &bus_tcon1_clk.common.hw,
737                 [CLK_BUS_CSI]           = &bus_csi_clk.common.hw,
738                 [CLK_BUS_HDMI]          = &bus_hdmi_clk.common.hw,
739                 [CLK_BUS_DE]            = &bus_de_clk.common.hw,
740                 [CLK_BUS_GPU]           = &bus_gpu_clk.common.hw,
741                 [CLK_BUS_MSGBOX]        = &bus_msgbox_clk.common.hw,
742                 [CLK_BUS_SPINLOCK]      = &bus_spinlock_clk.common.hw,
743                 [CLK_BUS_SPDIF]         = &bus_spdif_clk.common.hw,
744                 [CLK_BUS_PIO]           = &bus_pio_clk.common.hw,
745                 [CLK_BUS_I2S0]          = &bus_i2s0_clk.common.hw,
746                 [CLK_BUS_I2S1]          = &bus_i2s1_clk.common.hw,
747                 [CLK_BUS_I2S2]          = &bus_i2s2_clk.common.hw,
748                 [CLK_BUS_TDM]           = &bus_tdm_clk.common.hw,
749                 [CLK_BUS_I2C0]          = &bus_i2c0_clk.common.hw,
750                 [CLK_BUS_I2C1]          = &bus_i2c1_clk.common.hw,
751                 [CLK_BUS_I2C2]          = &bus_i2c2_clk.common.hw,
752                 [CLK_BUS_UART0]         = &bus_uart0_clk.common.hw,
753                 [CLK_BUS_UART1]         = &bus_uart1_clk.common.hw,
754                 [CLK_BUS_UART2]         = &bus_uart2_clk.common.hw,
755                 [CLK_BUS_UART3]         = &bus_uart3_clk.common.hw,
756                 [CLK_BUS_UART4]         = &bus_uart4_clk.common.hw,
757                 [CLK_CCI400]            = &cci400_clk.common.hw,
758                 [CLK_NAND]              = &nand_clk.common.hw,
759                 [CLK_MMC0]              = &mmc0_clk.common.hw,
760                 [CLK_MMC0_SAMPLE]       = &mmc0_sample_clk.common.hw,
761                 [CLK_MMC0_OUTPUT]       = &mmc0_output_clk.common.hw,
762                 [CLK_MMC1]              = &mmc1_clk.common.hw,
763                 [CLK_MMC1_SAMPLE]       = &mmc1_sample_clk.common.hw,
764                 [CLK_MMC1_OUTPUT]       = &mmc1_output_clk.common.hw,
765                 [CLK_MMC2]              = &mmc2_clk.common.hw,
766                 [CLK_MMC2_SAMPLE]       = &mmc2_sample_clk.common.hw,
767                 [CLK_MMC2_OUTPUT]       = &mmc2_output_clk.common.hw,
768                 [CLK_SS]                = &ss_clk.common.hw,
769                 [CLK_SPI0]              = &spi0_clk.common.hw,
770                 [CLK_SPI1]              = &spi1_clk.common.hw,
771                 [CLK_I2S0]              = &i2s0_clk.common.hw,
772                 [CLK_I2S1]              = &i2s1_clk.common.hw,
773                 [CLK_I2S2]              = &i2s2_clk.common.hw,
774                 [CLK_TDM]               = &tdm_clk.common.hw,
775                 [CLK_SPDIF]             = &spdif_clk.common.hw,
776                 [CLK_USB_PHY0]          = &usb_phy0_clk.common.hw,
777                 [CLK_USB_PHY1]          = &usb_phy1_clk.common.hw,
778                 [CLK_USB_HSIC]          = &usb_hsic_clk.common.hw,
779                 [CLK_USB_HSIC_12M]      = &usb_hsic_12m_clk.common.hw,
780                 [CLK_USB_OHCI0]         = &usb_ohci0_clk.common.hw,
781                 [CLK_DRAM]              = &dram_clk.common.hw,
782                 [CLK_DRAM_VE]           = &dram_ve_clk.common.hw,
783                 [CLK_DRAM_CSI]          = &dram_csi_clk.common.hw,
784                 [CLK_TCON0]             = &tcon0_clk.common.hw,
785                 [CLK_TCON1]             = &tcon1_clk.common.hw,
786                 [CLK_CSI_MISC]          = &csi_misc_clk.common.hw,
787                 [CLK_MIPI_CSI]          = &mipi_csi_clk.common.hw,
788                 [CLK_CSI_MCLK]          = &csi_mclk_clk.common.hw,
789                 [CLK_CSI_SCLK]          = &csi_sclk_clk.common.hw,
790                 [CLK_VE]                = &ve_clk.common.hw,
791                 [CLK_AVS]               = &avs_clk.common.hw,
792                 [CLK_HDMI]              = &hdmi_clk.common.hw,
793                 [CLK_HDMI_SLOW]         = &hdmi_slow_clk.common.hw,
794                 [CLK_MBUS]              = &mbus_clk.common.hw,
795                 [CLK_MIPI_DSI0]         = &mipi_dsi0_clk.common.hw,
796                 [CLK_MIPI_DSI1]         = &mipi_dsi1_clk.common.hw,
797                 [CLK_GPU_CORE]          = &gpu_core_clk.common.hw,
798                 [CLK_GPU_MEMORY]        = &gpu_memory_clk.common.hw,
799                 [CLK_GPU_HYD]           = &gpu_hyd_clk.common.hw,
800         },
801         .num    = CLK_NUMBER,
802 };
803
804 static struct ccu_reset_map sun8i_a83t_ccu_resets[] = {
805         [RST_USB_PHY0]          = { 0x0cc, BIT(0) },
806         [RST_USB_PHY1]          = { 0x0cc, BIT(1) },
807         [RST_USB_HSIC]          = { 0x0cc, BIT(2) },
808         [RST_DRAM]              = { 0x0f4, BIT(31) },
809         [RST_MBUS]              = { 0x0fc, BIT(31) },
810         [RST_BUS_MIPI_DSI]      = { 0x2c0, BIT(1) },
811         [RST_BUS_SS]            = { 0x2c0, BIT(5) },
812         [RST_BUS_DMA]           = { 0x2c0, BIT(6) },
813         [RST_BUS_MMC0]          = { 0x2c0, BIT(8) },
814         [RST_BUS_MMC1]          = { 0x2c0, BIT(9) },
815         [RST_BUS_MMC2]          = { 0x2c0, BIT(10) },
816         [RST_BUS_NAND]          = { 0x2c0, BIT(13) },
817         [RST_BUS_DRAM]          = { 0x2c0, BIT(14) },
818         [RST_BUS_EMAC]          = { 0x2c0, BIT(17) },
819         [RST_BUS_HSTIMER]       = { 0x2c0, BIT(19) },
820         [RST_BUS_SPI0]          = { 0x2c0, BIT(20) },
821         [RST_BUS_SPI1]          = { 0x2c0, BIT(21) },
822         [RST_BUS_OTG]           = { 0x2c0, BIT(24) },
823         [RST_BUS_EHCI0]         = { 0x2c0, BIT(26) },
824         [RST_BUS_EHCI1]         = { 0x2c0, BIT(27) },
825         [RST_BUS_OHCI0]         = { 0x2c0, BIT(29) },
826         [RST_BUS_VE]            = { 0x2c4, BIT(0) },
827         [RST_BUS_TCON0]         = { 0x2c4, BIT(4) },
828         [RST_BUS_TCON1]         = { 0x2c4, BIT(5) },
829         [RST_BUS_CSI]           = { 0x2c4, BIT(8) },
830         [RST_BUS_HDMI0]         = { 0x2c4, BIT(10) },
831         [RST_BUS_HDMI1]         = { 0x2c4, BIT(11) },
832         [RST_BUS_DE]            = { 0x2c4, BIT(12) },
833         [RST_BUS_GPU]           = { 0x2c4, BIT(20) },
834         [RST_BUS_MSGBOX]        = { 0x2c4, BIT(21) },
835         [RST_BUS_SPINLOCK]      = { 0x2c4, BIT(22) },
836         [RST_BUS_LVDS]          = { 0x2c8, BIT(0) },
837         [RST_BUS_SPDIF]         = { 0x2d0, BIT(1) },
838         [RST_BUS_I2S0]          = { 0x2d0, BIT(12) },
839         [RST_BUS_I2S1]          = { 0x2d0, BIT(13) },
840         [RST_BUS_I2S2]          = { 0x2d0, BIT(14) },
841         [RST_BUS_TDM]           = { 0x2d0, BIT(15) },
842         [RST_BUS_I2C0]          = { 0x2d8, BIT(0) },
843         [RST_BUS_I2C1]          = { 0x2d8, BIT(1) },
844         [RST_BUS_I2C2]          = { 0x2d8, BIT(2) },
845         [RST_BUS_UART0]         = { 0x2d8, BIT(16) },
846         [RST_BUS_UART1]         = { 0x2d8, BIT(17) },
847         [RST_BUS_UART2]         = { 0x2d8, BIT(18) },
848         [RST_BUS_UART3]         = { 0x2d8, BIT(19) },
849         [RST_BUS_UART4]         = { 0x2d8, BIT(20) },
850 };
851
852 static const struct sunxi_ccu_desc sun8i_a83t_ccu_desc = {
853         .ccu_clks       = sun8i_a83t_ccu_clks,
854         .num_ccu_clks   = ARRAY_SIZE(sun8i_a83t_ccu_clks),
855
856         .hw_clks        = &sun8i_a83t_hw_clks,
857
858         .resets         = sun8i_a83t_ccu_resets,
859         .num_resets     = ARRAY_SIZE(sun8i_a83t_ccu_resets),
860 };
861
862 #define SUN8I_A83T_PLL_P_SHIFT  16
863 #define SUN8I_A83T_PLL_N_SHIFT  8
864 #define SUN8I_A83T_PLL_N_WIDTH  8
865
866 static void sun8i_a83t_cpu_pll_fixup(void __iomem *reg)
867 {
868         u32 val = readl(reg);
869
870         /* bail out if P divider is not used */
871         if (!(val & BIT(SUN8I_A83T_PLL_P_SHIFT)))
872                 return;
873
874         /*
875          * If P is used, output should be less than 288 MHz. When we
876          * set P to 1, we should also decrease the multiplier so the
877          * output doesn't go out of range, but not too much such that
878          * the multiplier stays above 12, the minimal operation value.
879          *
880          * To keep it simple, set the multiplier to 17, the reset value.
881          */
882         val &= ~GENMASK(SUN8I_A83T_PLL_N_SHIFT + SUN8I_A83T_PLL_N_WIDTH - 1,
883                         SUN8I_A83T_PLL_N_SHIFT);
884         val |= 17 << SUN8I_A83T_PLL_N_SHIFT;
885
886         /* And clear P */
887         val &= ~BIT(SUN8I_A83T_PLL_P_SHIFT);
888
889         writel(val, reg);
890 }
891
892 static int sun8i_a83t_ccu_probe(struct platform_device *pdev)
893 {
894         struct resource *res;
895         void __iomem *reg;
896         u32 val;
897
898         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
899         reg = devm_ioremap_resource(&pdev->dev, res);
900         if (IS_ERR(reg))
901                 return PTR_ERR(reg);
902
903         /* Enforce d1 = 0, d2 = 1 for Audio PLL */
904         val = readl(reg + SUN8I_A83T_PLL_AUDIO_REG);
905         val &= ~BIT(16);
906         val |= BIT(18);
907         writel(val, reg + SUN8I_A83T_PLL_AUDIO_REG);
908
909         /* Enforce P = 1 for both CPU cluster PLLs */
910         sun8i_a83t_cpu_pll_fixup(reg + SUN8I_A83T_PLL_C0CPUX_REG);
911         sun8i_a83t_cpu_pll_fixup(reg + SUN8I_A83T_PLL_C1CPUX_REG);
912
913         return sunxi_ccu_probe(pdev->dev.of_node, reg, &sun8i_a83t_ccu_desc);
914 }
915
916 static const struct of_device_id sun8i_a83t_ccu_ids[] = {
917         { .compatible = "allwinner,sun8i-a83t-ccu" },
918         { }
919 };
920
921 static struct platform_driver sun8i_a83t_ccu_driver = {
922         .probe  = sun8i_a83t_ccu_probe,
923         .driver = {
924                 .name   = "sun8i-a83t-ccu",
925                 .of_match_table = sun8i_a83t_ccu_ids,
926         },
927 };
928 builtin_platform_driver(sun8i_a83t_ccu_driver);