1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016 Maxime Ripard. All rights reserved.
6 #include <linux/clk-provider.h>
8 #include <linux/module.h>
9 #include <linux/platform_device.h>
11 #include "ccu_common.h"
12 #include "ccu_reset.h"
22 #include "ccu_phase.h"
24 #include "ccu-sun50i-a64.h"
26 static struct ccu_nkmp pll_cpux_clk = {
29 .n = _SUNXI_CCU_MULT(8, 5),
30 .k = _SUNXI_CCU_MULT(4, 2),
31 .m = _SUNXI_CCU_DIV(0, 2),
32 .p = _SUNXI_CCU_DIV_MAX(16, 2, 4),
35 .hw.init = CLK_HW_INIT("pll-cpux",
43 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
44 * the base (2x, 4x and 8x), and one variable divider (the one true
47 * With sigma-delta modulation for fractional-N on the audio PLL,
48 * we have to use specific dividers. This means the variable divider
49 * can no longer be used, as the audio codec requests the exact clock
50 * rates we support through this mechanism. So we now hard code the
51 * variable divider to 1. This means the clock rates will no longer
52 * match the clock names.
54 #define SUN50I_A64_PLL_AUDIO_REG 0x008
56 static struct ccu_sdm_setting pll_audio_sdm_table[] = {
57 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
58 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
61 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
65 pll_audio_sdm_table, BIT(24),
71 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX_CLOSEST(pll_video0_clk, "pll-video0",
73 192000000, /* Minimum rate */
74 1008000000, /* Maximum rate */
77 BIT(24), /* frac enable */
78 BIT(25), /* frac select */
79 270000000, /* frac rate 0 */
80 297000000, /* frac rate 1 */
85 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
89 BIT(24), /* frac enable */
90 BIT(25), /* frac select */
91 270000000, /* frac rate 0 */
92 297000000, /* frac rate 1 */
97 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
104 CLK_SET_RATE_UNGATE);
106 static struct ccu_nk pll_periph0_clk = {
109 .n = _SUNXI_CCU_MULT(8, 5),
110 .k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
114 .features = CCU_FEATURE_FIXED_POSTDIV,
115 .hw.init = CLK_HW_INIT("pll-periph0", "osc24M",
116 &ccu_nk_ops, CLK_SET_RATE_UNGATE),
120 static struct ccu_nk pll_periph1_clk = {
123 .n = _SUNXI_CCU_MULT(8, 5),
124 .k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
128 .features = CCU_FEATURE_FIXED_POSTDIV,
129 .hw.init = CLK_HW_INIT("pll-periph1", "osc24M",
130 &ccu_nk_ops, CLK_SET_RATE_UNGATE),
134 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video1_clk, "pll-video1",
136 192000000, /* Minimum rate */
137 1008000000, /* Maximum rate */
140 BIT(24), /* frac enable */
141 BIT(25), /* frac select */
142 270000000, /* frac rate 0 */
143 297000000, /* frac rate 1 */
146 CLK_SET_RATE_UNGATE);
148 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
152 BIT(24), /* frac enable */
153 BIT(25), /* frac select */
154 270000000, /* frac rate 0 */
155 297000000, /* frac rate 1 */
158 CLK_SET_RATE_UNGATE);
161 * The output function can be changed to something more complex that
162 * we do not handle yet.
164 * Hardcode the mode so that we don't fall in that case.
166 #define SUN50I_A64_PLL_MIPI_REG 0x040
168 static struct ccu_nkm pll_mipi_clk = {
170 * The bit 23 and 22 are called "LDO{1,2}_EN" on the SoC's
171 * user manual, and by experiments the PLL doesn't work without
172 * these bits toggled.
174 .enable = BIT(31) | BIT(23) | BIT(22),
176 .n = _SUNXI_CCU_MULT(8, 4),
177 .k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
178 .m = _SUNXI_CCU_DIV(0, 4),
181 .hw.init = CLK_HW_INIT("pll-mipi", "pll-video0",
183 CLK_SET_RATE_UNGATE | CLK_SET_RATE_PARENT),
184 .features = CCU_FEATURE_CLOSEST_RATE,
188 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_hsic_clk, "pll-hsic",
192 BIT(24), /* frac enable */
193 BIT(25), /* frac select */
194 270000000, /* frac rate 0 */
195 297000000, /* frac rate 1 */
198 CLK_SET_RATE_UNGATE);
200 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
204 BIT(24), /* frac enable */
205 BIT(25), /* frac select */
206 270000000, /* frac rate 0 */
207 297000000, /* frac rate 1 */
210 CLK_SET_RATE_UNGATE);
212 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1",
218 CLK_SET_RATE_UNGATE);
220 static const char * const cpux_parents[] = { "osc32k", "osc24M",
221 "pll-cpux", "pll-cpux" };
222 static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
223 0x050, 16, 2, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
225 static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
227 static const char * const ahb1_parents[] = { "osc32k", "osc24M",
228 "axi", "pll-periph0" };
229 static const struct ccu_mux_var_prediv ahb1_predivs[] = {
230 { .index = 3, .shift = 6, .width = 2 },
232 static struct ccu_div ahb1_clk = {
233 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
239 .var_predivs = ahb1_predivs,
240 .n_var_predivs = ARRAY_SIZE(ahb1_predivs),
245 .features = CCU_FEATURE_VARIABLE_PREDIV,
246 .hw.init = CLK_HW_INIT_PARENTS("ahb1",
253 static struct clk_div_table apb1_div_table[] = {
254 { .val = 0, .div = 2 },
255 { .val = 1, .div = 2 },
256 { .val = 2, .div = 4 },
257 { .val = 3, .div = 8 },
260 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
261 0x054, 8, 2, apb1_div_table, 0);
263 static const char * const apb2_parents[] = { "osc32k", "osc24M",
266 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
272 static const char * const ahb2_parents[] = { "ahb1", "pll-periph0" };
273 static const struct ccu_mux_fixed_prediv ahb2_fixed_predivs[] = {
274 { .index = 1, .div = 2 },
276 static struct ccu_mux ahb2_clk = {
280 .fixed_predivs = ahb2_fixed_predivs,
281 .n_predivs = ARRAY_SIZE(ahb2_fixed_predivs),
286 .features = CCU_FEATURE_FIXED_PREDIV,
287 .hw.init = CLK_HW_INIT_PARENTS("ahb2",
294 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
296 static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1",
298 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
300 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
302 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
304 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
306 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
308 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
310 static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb2",
312 static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb1",
314 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
316 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1",
318 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1",
320 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",
322 static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb1",
324 static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb2",
326 static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb1",
328 static SUNXI_CCU_GATE(bus_ohci1_clk, "bus-ohci1", "ahb2",
331 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1",
333 static SUNXI_CCU_GATE(bus_tcon0_clk, "bus-tcon0", "ahb1",
335 static SUNXI_CCU_GATE(bus_tcon1_clk, "bus-tcon1", "ahb1",
337 static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "ahb1",
339 static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1",
341 static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb1",
343 static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb1",
345 static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1",
347 static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1",
349 static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",
352 static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1",
354 static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1",
356 static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1",
358 static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1",
360 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1",
362 static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1",
364 static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1",
367 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
369 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
371 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",
373 static SUNXI_CCU_GATE(bus_scr_clk, "bus-scr", "apb2",
375 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",
377 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",
379 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
381 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2",
383 static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2",
386 static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "ahb1",
389 static struct clk_div_table ths_div_table[] = {
390 { .val = 0, .div = 1 },
391 { .val = 1, .div = 2 },
392 { .val = 2, .div = 4 },
393 { .val = 3, .div = 6 },
396 static const char * const ths_parents[] = { "osc24M" };
397 static struct ccu_div ths_clk = {
399 .div = _SUNXI_CCU_DIV_TABLE(0, 2, ths_div_table),
400 .mux = _SUNXI_CCU_MUX(24, 2),
403 .hw.init = CLK_HW_INIT_PARENTS("ths",
410 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0",
412 static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
420 * MMC clocks are the new timing mode (see A83T & H3) variety, but without
421 * the mode switch. This means they have a 2x post divider between the clock
422 * and the MMC module. This is not documented in the manual, but is taken
423 * into consideration when setting the mmc module clocks in the BSP kernel.
424 * Without it, MMC performance is degraded.
426 * We model it here to be consistent with other SoCs supporting this mode.
427 * The alternative would be to add the 2x multiplier when setting the MMC
428 * module clock in the MMC driver, just for the A64.
430 static const char * const mmc_default_parents[] = { "osc24M", "pll-periph0-2x",
432 static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc0_clk, "mmc0",
433 mmc_default_parents, 0x088,
441 static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1",
442 mmc_default_parents, 0x08c,
450 static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc2_clk, "mmc2",
451 mmc_default_parents, 0x090,
459 static const char * const ts_parents[] = { "osc24M", "pll-periph0", };
460 static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x098,
467 static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", mmc_default_parents, 0x09c,
474 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
481 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
488 static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
489 "pll-audio-2x", "pll-audio" };
490 static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents,
491 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
493 static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents,
494 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
496 static SUNXI_CCU_MUX_WITH_GATE(i2s2_clk, "i2s2", i2s_parents,
497 0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
499 static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio",
500 0x0c0, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
502 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
504 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
506 static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic",
508 static SUNXI_CCU_GATE(usb_hsic_12m_clk, "usb-hsic-12M", "osc12M",
510 static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M",
512 static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "usb-ohci0",
515 static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1" };
516 static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents,
517 0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL);
519 static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram",
521 static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "dram",
523 static SUNXI_CCU_GATE(dram_deinterlace_clk, "dram-deinterlace", "dram",
525 static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "dram",
528 static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };
529 static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
530 0x104, 0, 4, 24, 3, BIT(31),
531 CLK_SET_RATE_PARENT);
534 * DSI output seems to work only when PLL_MIPI selected. Set it and prevent
535 * the mux from reparenting.
537 #define SUN50I_A64_TCON0_CLK_REG 0x118
539 static const char * const tcon0_parents[] = { "pll-mipi", "pll-video0-2x" };
540 static const u8 tcon0_table[] = { 0, 2, };
541 static SUNXI_CCU_MUX_TABLE_WITH_GATE_CLOSEST(tcon0_clk, "tcon0", tcon0_parents,
542 tcon0_table, 0x118, 24, 3, BIT(31),
543 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT);
545 static const char * const tcon1_parents[] = { "pll-video0", "pll-video1" };
546 static const u8 tcon1_table[] = { 0, 2, };
547 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE_CLOSEST(tcon1_clk, "tcon1", tcon1_parents,
552 CLK_SET_RATE_PARENT);
554 static const char * const deinterlace_parents[] = { "pll-periph0", "pll-periph1" };
555 static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace", deinterlace_parents,
556 0x124, 0, 4, 24, 3, BIT(31), 0);
558 static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M",
561 static const char * const csi_sclk_parents[] = { "pll-periph0", "pll-periph1" };
562 static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents,
563 0x134, 16, 4, 24, 3, BIT(31), 0);
565 static const char * const csi_mclk_parents[] = { "osc24M", "pll-video1", "pll-periph1" };
566 static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents,
567 0x134, 0, 5, 8, 3, BIT(15), 0);
569 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
570 0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT);
572 static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio",
573 0x140, BIT(31), CLK_SET_RATE_PARENT);
575 static SUNXI_CCU_GATE(ac_dig_4x_clk, "ac-dig-4x", "pll-audio-4x",
576 0x140, BIT(30), CLK_SET_RATE_PARENT);
578 static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",
581 static const char * const hdmi_parents[] = { "pll-video0", "pll-video1" };
582 static SUNXI_CCU_M_WITH_MUX_GATE_CLOSEST(hdmi_clk, "hdmi", hdmi_parents,
583 0x150, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
585 static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M",
588 static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x",
589 "pll-ddr0", "pll-ddr1" };
590 static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
591 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
593 static const char * const dsi_dphy_parents[] = { "pll-video0", "pll-periph0" };
594 static const u8 dsi_dphy_table[] = { 0, 2, };
595 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE_CLOSEST(dsi_dphy_clk, "dsi-dphy",
596 dsi_dphy_parents, dsi_dphy_table,
597 0x168, 0, 4, 8, 2, BIT(15), CLK_SET_RATE_PARENT);
599 static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
600 0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
602 /* Fixed Factor clocks */
603 static CLK_FIXED_FACTOR_FW_NAME(osc12M_clk, "osc12M", "hosc", 2, 1, 0);
605 static const struct clk_hw *clk_parent_pll_audio[] = {
606 &pll_audio_base_clk.common.hw
609 /* We hardcode the divider to 1 for now */
610 static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
611 clk_parent_pll_audio,
612 1, 1, CLK_SET_RATE_PARENT);
613 static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
614 clk_parent_pll_audio,
615 2, 1, CLK_SET_RATE_PARENT);
616 static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
617 clk_parent_pll_audio,
618 1, 1, CLK_SET_RATE_PARENT);
619 static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
620 clk_parent_pll_audio,
621 1, 2, CLK_SET_RATE_PARENT);
622 static CLK_FIXED_FACTOR_HW(pll_periph0_2x_clk, "pll-periph0-2x",
623 &pll_periph0_clk.common.hw,
625 static CLK_FIXED_FACTOR_HW(pll_periph1_2x_clk, "pll-periph1-2x",
626 &pll_periph1_clk.common.hw,
628 static CLK_FIXED_FACTOR_HW(pll_video0_2x_clk, "pll-video0-2x",
629 &pll_video0_clk.common.hw,
630 1, 2, CLK_SET_RATE_PARENT);
632 static struct ccu_common *sun50i_a64_ccu_clks[] = {
633 &pll_cpux_clk.common,
634 &pll_audio_base_clk.common,
635 &pll_video0_clk.common,
637 &pll_ddr0_clk.common,
638 &pll_periph0_clk.common,
639 &pll_periph1_clk.common,
640 &pll_video1_clk.common,
642 &pll_mipi_clk.common,
643 &pll_hsic_clk.common,
645 &pll_ddr1_clk.common,
652 &bus_mipi_dsi_clk.common,
655 &bus_mmc0_clk.common,
656 &bus_mmc1_clk.common,
657 &bus_mmc2_clk.common,
658 &bus_nand_clk.common,
659 &bus_dram_clk.common,
660 &bus_emac_clk.common,
662 &bus_hstimer_clk.common,
663 &bus_spi0_clk.common,
664 &bus_spi1_clk.common,
666 &bus_ehci0_clk.common,
667 &bus_ehci1_clk.common,
668 &bus_ohci0_clk.common,
669 &bus_ohci1_clk.common,
671 &bus_tcon0_clk.common,
672 &bus_tcon1_clk.common,
673 &bus_deinterlace_clk.common,
675 &bus_hdmi_clk.common,
678 &bus_msgbox_clk.common,
679 &bus_spinlock_clk.common,
680 &bus_codec_clk.common,
681 &bus_spdif_clk.common,
684 &bus_i2s0_clk.common,
685 &bus_i2s1_clk.common,
686 &bus_i2s2_clk.common,
687 &bus_i2c0_clk.common,
688 &bus_i2c1_clk.common,
689 &bus_i2c2_clk.common,
691 &bus_uart0_clk.common,
692 &bus_uart1_clk.common,
693 &bus_uart2_clk.common,
694 &bus_uart3_clk.common,
695 &bus_uart4_clk.common,
710 &usb_phy0_clk.common,
711 &usb_phy1_clk.common,
712 &usb_hsic_clk.common,
713 &usb_hsic_12m_clk.common,
714 &usb_ohci0_clk.common,
715 &usb_ohci1_clk.common,
718 &dram_csi_clk.common,
719 &dram_deinterlace_clk.common,
724 &deinterlace_clk.common,
725 &csi_misc_clk.common,
726 &csi_sclk_clk.common,
727 &csi_mclk_clk.common,
730 &ac_dig_4x_clk.common,
733 &hdmi_ddc_clk.common,
735 &dsi_dphy_clk.common,
739 static struct clk_hw_onecell_data sun50i_a64_hw_clks = {
741 [CLK_OSC_12M] = &osc12M_clk.hw,
742 [CLK_PLL_CPUX] = &pll_cpux_clk.common.hw,
743 [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
744 [CLK_PLL_AUDIO] = &pll_audio_clk.hw,
745 [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
746 [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
747 [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
748 [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw,
749 [CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw,
750 [CLK_PLL_VE] = &pll_ve_clk.common.hw,
751 [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw,
752 [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw,
753 [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw,
754 [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw,
755 [CLK_PLL_PERIPH1_2X] = &pll_periph1_2x_clk.hw,
756 [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw,
757 [CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
758 [CLK_PLL_MIPI] = &pll_mipi_clk.common.hw,
759 [CLK_PLL_HSIC] = &pll_hsic_clk.common.hw,
760 [CLK_PLL_DE] = &pll_de_clk.common.hw,
761 [CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw,
762 [CLK_CPUX] = &cpux_clk.common.hw,
763 [CLK_AXI] = &axi_clk.common.hw,
764 [CLK_AHB1] = &ahb1_clk.common.hw,
765 [CLK_APB1] = &apb1_clk.common.hw,
766 [CLK_APB2] = &apb2_clk.common.hw,
767 [CLK_AHB2] = &ahb2_clk.common.hw,
768 [CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw,
769 [CLK_BUS_CE] = &bus_ce_clk.common.hw,
770 [CLK_BUS_DMA] = &bus_dma_clk.common.hw,
771 [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
772 [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
773 [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
774 [CLK_BUS_NAND] = &bus_nand_clk.common.hw,
775 [CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
776 [CLK_BUS_EMAC] = &bus_emac_clk.common.hw,
777 [CLK_BUS_TS] = &bus_ts_clk.common.hw,
778 [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
779 [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
780 [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
781 [CLK_BUS_OTG] = &bus_otg_clk.common.hw,
782 [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw,
783 [CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw,
784 [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw,
785 [CLK_BUS_OHCI1] = &bus_ohci1_clk.common.hw,
786 [CLK_BUS_VE] = &bus_ve_clk.common.hw,
787 [CLK_BUS_TCON0] = &bus_tcon0_clk.common.hw,
788 [CLK_BUS_TCON1] = &bus_tcon1_clk.common.hw,
789 [CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw,
790 [CLK_BUS_CSI] = &bus_csi_clk.common.hw,
791 [CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw,
792 [CLK_BUS_DE] = &bus_de_clk.common.hw,
793 [CLK_BUS_GPU] = &bus_gpu_clk.common.hw,
794 [CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw,
795 [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw,
796 [CLK_BUS_CODEC] = &bus_codec_clk.common.hw,
797 [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw,
798 [CLK_BUS_PIO] = &bus_pio_clk.common.hw,
799 [CLK_BUS_THS] = &bus_ths_clk.common.hw,
800 [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
801 [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw,
802 [CLK_BUS_I2S2] = &bus_i2s2_clk.common.hw,
803 [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
804 [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
805 [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
806 [CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
807 [CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
808 [CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
809 [CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
810 [CLK_BUS_UART4] = &bus_uart4_clk.common.hw,
811 [CLK_BUS_SCR] = &bus_scr_clk.common.hw,
812 [CLK_BUS_DBG] = &bus_dbg_clk.common.hw,
813 [CLK_THS] = &ths_clk.common.hw,
814 [CLK_NAND] = &nand_clk.common.hw,
815 [CLK_MMC0] = &mmc0_clk.common.hw,
816 [CLK_MMC1] = &mmc1_clk.common.hw,
817 [CLK_MMC2] = &mmc2_clk.common.hw,
818 [CLK_TS] = &ts_clk.common.hw,
819 [CLK_CE] = &ce_clk.common.hw,
820 [CLK_SPI0] = &spi0_clk.common.hw,
821 [CLK_SPI1] = &spi1_clk.common.hw,
822 [CLK_I2S0] = &i2s0_clk.common.hw,
823 [CLK_I2S1] = &i2s1_clk.common.hw,
824 [CLK_I2S2] = &i2s2_clk.common.hw,
825 [CLK_SPDIF] = &spdif_clk.common.hw,
826 [CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
827 [CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
828 [CLK_USB_HSIC] = &usb_hsic_clk.common.hw,
829 [CLK_USB_HSIC_12M] = &usb_hsic_12m_clk.common.hw,
830 [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
831 [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,
832 [CLK_DRAM] = &dram_clk.common.hw,
833 [CLK_DRAM_VE] = &dram_ve_clk.common.hw,
834 [CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
835 [CLK_DRAM_DEINTERLACE] = &dram_deinterlace_clk.common.hw,
836 [CLK_DRAM_TS] = &dram_ts_clk.common.hw,
837 [CLK_DE] = &de_clk.common.hw,
838 [CLK_TCON0] = &tcon0_clk.common.hw,
839 [CLK_TCON1] = &tcon1_clk.common.hw,
840 [CLK_DEINTERLACE] = &deinterlace_clk.common.hw,
841 [CLK_CSI_MISC] = &csi_misc_clk.common.hw,
842 [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw,
843 [CLK_CSI_MCLK] = &csi_mclk_clk.common.hw,
844 [CLK_VE] = &ve_clk.common.hw,
845 [CLK_AC_DIG] = &ac_dig_clk.common.hw,
846 [CLK_AC_DIG_4X] = &ac_dig_4x_clk.common.hw,
847 [CLK_AVS] = &avs_clk.common.hw,
848 [CLK_HDMI] = &hdmi_clk.common.hw,
849 [CLK_HDMI_DDC] = &hdmi_ddc_clk.common.hw,
850 [CLK_MBUS] = &mbus_clk.common.hw,
851 [CLK_DSI_DPHY] = &dsi_dphy_clk.common.hw,
852 [CLK_GPU] = &gpu_clk.common.hw,
857 static struct ccu_reset_map sun50i_a64_ccu_resets[] = {
858 [RST_USB_PHY0] = { 0x0cc, BIT(0) },
859 [RST_USB_PHY1] = { 0x0cc, BIT(1) },
860 [RST_USB_HSIC] = { 0x0cc, BIT(2) },
862 [RST_DRAM] = { 0x0f4, BIT(31) },
863 [RST_MBUS] = { 0x0fc, BIT(31) },
865 [RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) },
866 [RST_BUS_CE] = { 0x2c0, BIT(5) },
867 [RST_BUS_DMA] = { 0x2c0, BIT(6) },
868 [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
869 [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
870 [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
871 [RST_BUS_NAND] = { 0x2c0, BIT(13) },
872 [RST_BUS_DRAM] = { 0x2c0, BIT(14) },
873 [RST_BUS_EMAC] = { 0x2c0, BIT(17) },
874 [RST_BUS_TS] = { 0x2c0, BIT(18) },
875 [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
876 [RST_BUS_SPI0] = { 0x2c0, BIT(20) },
877 [RST_BUS_SPI1] = { 0x2c0, BIT(21) },
878 [RST_BUS_OTG] = { 0x2c0, BIT(23) },
879 [RST_BUS_EHCI0] = { 0x2c0, BIT(24) },
880 [RST_BUS_EHCI1] = { 0x2c0, BIT(25) },
881 [RST_BUS_OHCI0] = { 0x2c0, BIT(28) },
882 [RST_BUS_OHCI1] = { 0x2c0, BIT(29) },
884 [RST_BUS_VE] = { 0x2c4, BIT(0) },
885 [RST_BUS_TCON0] = { 0x2c4, BIT(3) },
886 [RST_BUS_TCON1] = { 0x2c4, BIT(4) },
887 [RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) },
888 [RST_BUS_CSI] = { 0x2c4, BIT(8) },
889 [RST_BUS_HDMI0] = { 0x2c4, BIT(10) },
890 [RST_BUS_HDMI1] = { 0x2c4, BIT(11) },
891 [RST_BUS_DE] = { 0x2c4, BIT(12) },
892 [RST_BUS_GPU] = { 0x2c4, BIT(20) },
893 [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) },
894 [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) },
895 [RST_BUS_DBG] = { 0x2c4, BIT(31) },
897 [RST_BUS_LVDS] = { 0x2c8, BIT(0) },
899 [RST_BUS_CODEC] = { 0x2d0, BIT(0) },
900 [RST_BUS_SPDIF] = { 0x2d0, BIT(1) },
901 [RST_BUS_THS] = { 0x2d0, BIT(8) },
902 [RST_BUS_I2S0] = { 0x2d0, BIT(12) },
903 [RST_BUS_I2S1] = { 0x2d0, BIT(13) },
904 [RST_BUS_I2S2] = { 0x2d0, BIT(14) },
906 [RST_BUS_I2C0] = { 0x2d8, BIT(0) },
907 [RST_BUS_I2C1] = { 0x2d8, BIT(1) },
908 [RST_BUS_I2C2] = { 0x2d8, BIT(2) },
909 [RST_BUS_SCR] = { 0x2d8, BIT(5) },
910 [RST_BUS_UART0] = { 0x2d8, BIT(16) },
911 [RST_BUS_UART1] = { 0x2d8, BIT(17) },
912 [RST_BUS_UART2] = { 0x2d8, BIT(18) },
913 [RST_BUS_UART3] = { 0x2d8, BIT(19) },
914 [RST_BUS_UART4] = { 0x2d8, BIT(20) },
917 static const struct sunxi_ccu_desc sun50i_a64_ccu_desc = {
918 .ccu_clks = sun50i_a64_ccu_clks,
919 .num_ccu_clks = ARRAY_SIZE(sun50i_a64_ccu_clks),
921 .hw_clks = &sun50i_a64_hw_clks,
923 .resets = sun50i_a64_ccu_resets,
924 .num_resets = ARRAY_SIZE(sun50i_a64_ccu_resets),
927 static struct ccu_pll_nb sun50i_a64_pll_cpu_nb = {
928 .common = &pll_cpux_clk.common,
929 /* copy from pll_cpux_clk */
934 static struct ccu_mux_nb sun50i_a64_cpu_nb = {
935 .common = &cpux_clk.common,
937 .delay_us = 1, /* > 8 clock cycles at 24 MHz */
938 .bypass_index = 1, /* index of 24 MHz oscillator */
941 static int sun50i_a64_ccu_probe(struct platform_device *pdev)
947 reg = devm_platform_ioremap_resource(pdev, 0);
951 /* Force the PLL-Audio-1x divider to 1 */
952 val = readl(reg + SUN50I_A64_PLL_AUDIO_REG);
953 val &= ~GENMASK(19, 16);
954 writel(val | (0 << 16), reg + SUN50I_A64_PLL_AUDIO_REG);
956 writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);
958 /* Set PLL MIPI as parent for TCON0 */
959 val = readl(reg + SUN50I_A64_TCON0_CLK_REG);
960 val &= ~GENMASK(26, 24);
961 writel(val | (0 << 24), reg + SUN50I_A64_TCON0_CLK_REG);
963 ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_a64_ccu_desc);
967 /* Gate then ungate PLL CPU after any rate changes */
968 ccu_pll_notifier_register(&sun50i_a64_pll_cpu_nb);
970 /* Reparent CPU during PLL CPU rate changes */
971 ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
977 static const struct of_device_id sun50i_a64_ccu_ids[] = {
978 { .compatible = "allwinner,sun50i-a64-ccu" },
982 static struct platform_driver sun50i_a64_ccu_driver = {
983 .probe = sun50i_a64_ccu_probe,
985 .name = "sun50i-a64-ccu",
986 .suppress_bind_attrs = true,
987 .of_match_table = sun50i_a64_ccu_ids,
990 module_platform_driver(sun50i_a64_ccu_driver);
992 MODULE_IMPORT_NS(SUNXI_CCU);
993 MODULE_LICENSE("GPL");