2 * Copyright (c) 2016 Maxime Ripard. All rights reserved.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/clk-provider.h>
15 #include <linux/of_address.h>
16 #include <linux/platform_device.h>
18 #include "ccu_common.h"
19 #include "ccu_reset.h"
29 #include "ccu_phase.h"
31 #include "ccu-sun50i-a64.h"
33 static struct ccu_nkmp pll_cpux_clk = {
36 .n = _SUNXI_CCU_MULT(8, 5),
37 .k = _SUNXI_CCU_MULT(4, 2),
38 .m = _SUNXI_CCU_DIV(0, 2),
39 .p = _SUNXI_CCU_DIV_MAX(16, 2, 4),
42 .hw.init = CLK_HW_INIT("pll-cpux",
50 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
51 * the base (2x, 4x and 8x), and one variable divider (the one true
54 * We don't have any need for the variable divider for now, so we just
55 * hardcode it to match with the clock names
57 #define SUN50I_A64_PLL_AUDIO_REG 0x008
59 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
67 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0",
71 BIT(24), /* frac enable */
72 BIT(25), /* frac select */
73 270000000, /* frac rate 0 */
74 297000000, /* frac rate 1 */
79 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
83 BIT(24), /* frac enable */
84 BIT(25), /* frac select */
85 270000000, /* frac rate 0 */
86 297000000, /* frac rate 1 */
91 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
100 static struct ccu_nk pll_periph0_clk = {
103 .n = _SUNXI_CCU_MULT(8, 5),
104 .k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
108 .features = CCU_FEATURE_FIXED_POSTDIV,
109 .hw.init = CLK_HW_INIT("pll-periph0", "osc24M",
110 &ccu_nk_ops, CLK_SET_RATE_UNGATE),
114 static struct ccu_nk pll_periph1_clk = {
117 .n = _SUNXI_CCU_MULT(8, 5),
118 .k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
122 .features = CCU_FEATURE_FIXED_POSTDIV,
123 .hw.init = CLK_HW_INIT("pll-periph1", "osc24M",
124 &ccu_nk_ops, CLK_SET_RATE_UNGATE),
128 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1",
132 BIT(24), /* frac enable */
133 BIT(25), /* frac select */
134 270000000, /* frac rate 0 */
135 297000000, /* frac rate 1 */
138 CLK_SET_RATE_UNGATE);
140 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
144 BIT(24), /* frac enable */
145 BIT(25), /* frac select */
146 270000000, /* frac rate 0 */
147 297000000, /* frac rate 1 */
150 CLK_SET_RATE_UNGATE);
153 * The output function can be changed to something more complex that
154 * we do not handle yet.
156 * Hardcode the mode so that we don't fall in that case.
158 #define SUN50I_A64_PLL_MIPI_REG 0x040
160 static struct ccu_nkm pll_mipi_clk = {
162 * The bit 23 and 22 are called "LDO{1,2}_EN" on the SoC's
163 * user manual, and by experiments the PLL doesn't work without
164 * these bits toggled.
166 .enable = BIT(31) | BIT(23) | BIT(22),
168 .n = _SUNXI_CCU_MULT(8, 4),
169 .k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
170 .m = _SUNXI_CCU_DIV(0, 4),
173 .hw.init = CLK_HW_INIT("pll-mipi", "pll-video0",
174 &ccu_nkm_ops, CLK_SET_RATE_UNGATE),
178 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_hsic_clk, "pll-hsic",
182 BIT(24), /* frac enable */
183 BIT(25), /* frac select */
184 270000000, /* frac rate 0 */
185 297000000, /* frac rate 1 */
188 CLK_SET_RATE_UNGATE);
190 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
194 BIT(24), /* frac enable */
195 BIT(25), /* frac select */
196 270000000, /* frac rate 0 */
197 297000000, /* frac rate 1 */
200 CLK_SET_RATE_UNGATE);
202 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1",
208 CLK_SET_RATE_UNGATE);
210 static const char * const cpux_parents[] = { "osc32k", "osc24M",
211 "pll-cpux", "pll-cpux" };
212 static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
213 0x050, 16, 2, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
215 static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
217 static const char * const ahb1_parents[] = { "osc32k", "osc24M",
218 "axi", "pll-periph0" };
219 static const struct ccu_mux_var_prediv ahb1_predivs[] = {
220 { .index = 3, .shift = 6, .width = 2 },
222 static struct ccu_div ahb1_clk = {
223 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
229 .var_predivs = ahb1_predivs,
230 .n_var_predivs = ARRAY_SIZE(ahb1_predivs),
235 .features = CCU_FEATURE_VARIABLE_PREDIV,
236 .hw.init = CLK_HW_INIT_PARENTS("ahb1",
243 static struct clk_div_table apb1_div_table[] = {
244 { .val = 0, .div = 2 },
245 { .val = 1, .div = 2 },
246 { .val = 2, .div = 4 },
247 { .val = 3, .div = 8 },
250 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
251 0x054, 8, 2, apb1_div_table, 0);
253 static const char * const apb2_parents[] = { "osc32k", "osc24M",
256 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
262 static const char * const ahb2_parents[] = { "ahb1", "pll-periph0" };
263 static const struct ccu_mux_fixed_prediv ahb2_fixed_predivs[] = {
264 { .index = 1, .div = 2 },
266 static struct ccu_mux ahb2_clk = {
270 .fixed_predivs = ahb2_fixed_predivs,
271 .n_predivs = ARRAY_SIZE(ahb2_fixed_predivs),
276 .features = CCU_FEATURE_FIXED_PREDIV,
277 .hw.init = CLK_HW_INIT_PARENTS("ahb2",
284 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
286 static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1",
288 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
290 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
292 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
294 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
296 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
298 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
300 static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb2",
302 static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb1",
304 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
306 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1",
308 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1",
310 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",
312 static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb1",
314 static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb2",
316 static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb1",
318 static SUNXI_CCU_GATE(bus_ohci1_clk, "bus-ohci1", "ahb2",
321 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1",
323 static SUNXI_CCU_GATE(bus_tcon0_clk, "bus-tcon0", "ahb1",
325 static SUNXI_CCU_GATE(bus_tcon1_clk, "bus-tcon1", "ahb1",
327 static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "ahb1",
329 static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1",
331 static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb1",
333 static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb1",
335 static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1",
337 static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1",
339 static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",
342 static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1",
344 static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1",
346 static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1",
348 static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1",
350 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1",
352 static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1",
354 static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1",
357 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
359 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
361 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",
363 static SUNXI_CCU_GATE(bus_scr_clk, "bus-scr", "apb2",
365 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",
367 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",
369 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
371 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2",
373 static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2",
376 static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "ahb1",
379 static struct clk_div_table ths_div_table[] = {
380 { .val = 0, .div = 1 },
381 { .val = 1, .div = 2 },
382 { .val = 2, .div = 4 },
383 { .val = 3, .div = 6 },
386 static const char * const ths_parents[] = { "osc24M" };
387 static struct ccu_div ths_clk = {
389 .div = _SUNXI_CCU_DIV_TABLE(0, 2, ths_div_table),
390 .mux = _SUNXI_CCU_MUX(24, 2),
393 .hw.init = CLK_HW_INIT_PARENTS("ths",
400 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0",
402 static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
409 static const char * const mmc_default_parents[] = { "osc24M", "pll-periph0-2x",
411 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mmc_default_parents, 0x088,
418 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mmc_default_parents, 0x08c,
425 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mmc_default_parents, 0x090,
432 static const char * const ts_parents[] = { "osc24M", "pll-periph0", };
433 static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x098,
440 static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", mmc_default_parents, 0x09c,
447 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
454 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
461 static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
462 "pll-audio-2x", "pll-audio" };
463 static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents,
464 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
466 static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents,
467 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
469 static SUNXI_CCU_MUX_WITH_GATE(i2s2_clk, "i2s2", i2s_parents,
470 0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
472 static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio",
473 0x0c0, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
475 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
477 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
479 static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic",
481 static SUNXI_CCU_GATE(usb_hsic_12m_clk, "usb-hsic-12M", "osc12M",
483 static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M",
485 static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "usb-ohci0",
488 static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1" };
489 static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents,
490 0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL);
492 static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram",
494 static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "dram",
496 static SUNXI_CCU_GATE(dram_deinterlace_clk, "dram-deinterlace", "dram",
498 static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "dram",
501 static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };
502 static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
503 0x104, 0, 4, 24, 3, BIT(31), 0);
505 static const char * const tcon0_parents[] = { "pll-mipi", "pll-video0-2x" };
506 static const u8 tcon0_table[] = { 0, 2, };
507 static SUNXI_CCU_MUX_TABLE_WITH_GATE(tcon0_clk, "tcon0", tcon0_parents,
508 tcon0_table, 0x118, 24, 3, BIT(31),
509 CLK_SET_RATE_PARENT);
511 static const char * const tcon1_parents[] = { "pll-video0", "pll-video1" };
512 static const u8 tcon1_table[] = { 0, 2, };
513 static struct ccu_div tcon1_clk = {
515 .div = _SUNXI_CCU_DIV(0, 4),
516 .mux = _SUNXI_CCU_MUX_TABLE(24, 2, tcon1_table),
519 .hw.init = CLK_HW_INIT_PARENTS("tcon1",
522 CLK_SET_RATE_PARENT),
526 static const char * const deinterlace_parents[] = { "pll-periph0", "pll-periph1" };
527 static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace", deinterlace_parents,
528 0x124, 0, 4, 24, 3, BIT(31), 0);
530 static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M",
533 static const char * const csi_sclk_parents[] = { "pll-periph0", "pll-periph1" };
534 static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents,
535 0x134, 16, 4, 24, 3, BIT(31), 0);
537 static const char * const csi_mclk_parents[] = { "osc24M", "pll-video1", "pll-periph1" };
538 static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents,
539 0x134, 0, 5, 8, 3, BIT(15), 0);
541 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
542 0x13c, 16, 3, BIT(31), 0);
544 static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio",
545 0x140, BIT(31), CLK_SET_RATE_PARENT);
547 static SUNXI_CCU_GATE(ac_dig_4x_clk, "ac-dig-4x", "pll-audio-4x",
548 0x140, BIT(30), CLK_SET_RATE_PARENT);
550 static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",
553 static const char * const hdmi_parents[] = { "pll-video0", "pll-video1" };
554 static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
555 0x150, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
557 static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M",
560 static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x",
561 "pll-ddr0", "pll-ddr1" };
562 static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
563 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
565 static const char * const dsi_dphy_parents[] = { "pll-video0", "pll-periph0" };
566 static const u8 dsi_dphy_table[] = { 0, 2, };
567 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy",
568 dsi_dphy_parents, dsi_dphy_table,
569 0x168, 0, 4, 8, 2, BIT(15), CLK_SET_RATE_PARENT);
571 static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
572 0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
574 /* Fixed Factor clocks */
575 static CLK_FIXED_FACTOR(osc12M_clk, "osc12M", "osc24M", 2, 1, 0);
577 /* We hardcode the divider to 4 for now */
578 static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
579 "pll-audio-base", 4, 1, CLK_SET_RATE_PARENT);
580 static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
581 "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
582 static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
583 "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
584 static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
585 "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
586 static CLK_FIXED_FACTOR(pll_periph0_2x_clk, "pll-periph0-2x",
587 "pll-periph0", 1, 2, 0);
588 static CLK_FIXED_FACTOR(pll_periph1_2x_clk, "pll-periph1-2x",
589 "pll-periph1", 1, 2, 0);
590 static CLK_FIXED_FACTOR(pll_video0_2x_clk, "pll-video0-2x",
591 "pll-video0", 1, 2, CLK_SET_RATE_PARENT);
593 static struct ccu_common *sun50i_a64_ccu_clks[] = {
594 &pll_cpux_clk.common,
595 &pll_audio_base_clk.common,
596 &pll_video0_clk.common,
598 &pll_ddr0_clk.common,
599 &pll_periph0_clk.common,
600 &pll_periph1_clk.common,
601 &pll_video1_clk.common,
603 &pll_mipi_clk.common,
604 &pll_hsic_clk.common,
606 &pll_ddr1_clk.common,
613 &bus_mipi_dsi_clk.common,
616 &bus_mmc0_clk.common,
617 &bus_mmc1_clk.common,
618 &bus_mmc2_clk.common,
619 &bus_nand_clk.common,
620 &bus_dram_clk.common,
621 &bus_emac_clk.common,
623 &bus_hstimer_clk.common,
624 &bus_spi0_clk.common,
625 &bus_spi1_clk.common,
627 &bus_ehci0_clk.common,
628 &bus_ehci1_clk.common,
629 &bus_ohci0_clk.common,
630 &bus_ohci1_clk.common,
632 &bus_tcon0_clk.common,
633 &bus_tcon1_clk.common,
634 &bus_deinterlace_clk.common,
636 &bus_hdmi_clk.common,
639 &bus_msgbox_clk.common,
640 &bus_spinlock_clk.common,
641 &bus_codec_clk.common,
642 &bus_spdif_clk.common,
645 &bus_i2s0_clk.common,
646 &bus_i2s1_clk.common,
647 &bus_i2s2_clk.common,
648 &bus_i2c0_clk.common,
649 &bus_i2c1_clk.common,
650 &bus_i2c2_clk.common,
652 &bus_uart0_clk.common,
653 &bus_uart1_clk.common,
654 &bus_uart2_clk.common,
655 &bus_uart3_clk.common,
656 &bus_uart4_clk.common,
671 &usb_phy0_clk.common,
672 &usb_phy1_clk.common,
673 &usb_hsic_clk.common,
674 &usb_hsic_12m_clk.common,
675 &usb_ohci0_clk.common,
676 &usb_ohci1_clk.common,
679 &dram_csi_clk.common,
680 &dram_deinterlace_clk.common,
685 &deinterlace_clk.common,
686 &csi_misc_clk.common,
687 &csi_sclk_clk.common,
688 &csi_mclk_clk.common,
691 &ac_dig_4x_clk.common,
694 &hdmi_ddc_clk.common,
696 &dsi_dphy_clk.common,
700 static struct clk_hw_onecell_data sun50i_a64_hw_clks = {
702 [CLK_OSC_12M] = &osc12M_clk.hw,
703 [CLK_PLL_CPUX] = &pll_cpux_clk.common.hw,
704 [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
705 [CLK_PLL_AUDIO] = &pll_audio_clk.hw,
706 [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
707 [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
708 [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
709 [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw,
710 [CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw,
711 [CLK_PLL_VE] = &pll_ve_clk.common.hw,
712 [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw,
713 [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw,
714 [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw,
715 [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw,
716 [CLK_PLL_PERIPH1_2X] = &pll_periph1_2x_clk.hw,
717 [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw,
718 [CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
719 [CLK_PLL_MIPI] = &pll_mipi_clk.common.hw,
720 [CLK_PLL_HSIC] = &pll_hsic_clk.common.hw,
721 [CLK_PLL_DE] = &pll_de_clk.common.hw,
722 [CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw,
723 [CLK_CPUX] = &cpux_clk.common.hw,
724 [CLK_AXI] = &axi_clk.common.hw,
725 [CLK_AHB1] = &ahb1_clk.common.hw,
726 [CLK_APB1] = &apb1_clk.common.hw,
727 [CLK_APB2] = &apb2_clk.common.hw,
728 [CLK_AHB2] = &ahb2_clk.common.hw,
729 [CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw,
730 [CLK_BUS_CE] = &bus_ce_clk.common.hw,
731 [CLK_BUS_DMA] = &bus_dma_clk.common.hw,
732 [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
733 [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
734 [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
735 [CLK_BUS_NAND] = &bus_nand_clk.common.hw,
736 [CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
737 [CLK_BUS_EMAC] = &bus_emac_clk.common.hw,
738 [CLK_BUS_TS] = &bus_ts_clk.common.hw,
739 [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
740 [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
741 [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
742 [CLK_BUS_OTG] = &bus_otg_clk.common.hw,
743 [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw,
744 [CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw,
745 [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw,
746 [CLK_BUS_OHCI1] = &bus_ohci1_clk.common.hw,
747 [CLK_BUS_VE] = &bus_ve_clk.common.hw,
748 [CLK_BUS_TCON0] = &bus_tcon0_clk.common.hw,
749 [CLK_BUS_TCON1] = &bus_tcon1_clk.common.hw,
750 [CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw,
751 [CLK_BUS_CSI] = &bus_csi_clk.common.hw,
752 [CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw,
753 [CLK_BUS_DE] = &bus_de_clk.common.hw,
754 [CLK_BUS_GPU] = &bus_gpu_clk.common.hw,
755 [CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw,
756 [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw,
757 [CLK_BUS_CODEC] = &bus_codec_clk.common.hw,
758 [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw,
759 [CLK_BUS_PIO] = &bus_pio_clk.common.hw,
760 [CLK_BUS_THS] = &bus_ths_clk.common.hw,
761 [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
762 [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw,
763 [CLK_BUS_I2S2] = &bus_i2s2_clk.common.hw,
764 [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
765 [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
766 [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
767 [CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
768 [CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
769 [CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
770 [CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
771 [CLK_BUS_UART4] = &bus_uart4_clk.common.hw,
772 [CLK_BUS_SCR] = &bus_scr_clk.common.hw,
773 [CLK_BUS_DBG] = &bus_dbg_clk.common.hw,
774 [CLK_THS] = &ths_clk.common.hw,
775 [CLK_NAND] = &nand_clk.common.hw,
776 [CLK_MMC0] = &mmc0_clk.common.hw,
777 [CLK_MMC1] = &mmc1_clk.common.hw,
778 [CLK_MMC2] = &mmc2_clk.common.hw,
779 [CLK_TS] = &ts_clk.common.hw,
780 [CLK_CE] = &ce_clk.common.hw,
781 [CLK_SPI0] = &spi0_clk.common.hw,
782 [CLK_SPI1] = &spi1_clk.common.hw,
783 [CLK_I2S0] = &i2s0_clk.common.hw,
784 [CLK_I2S1] = &i2s1_clk.common.hw,
785 [CLK_I2S2] = &i2s2_clk.common.hw,
786 [CLK_SPDIF] = &spdif_clk.common.hw,
787 [CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
788 [CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
789 [CLK_USB_HSIC] = &usb_hsic_clk.common.hw,
790 [CLK_USB_HSIC_12M] = &usb_hsic_12m_clk.common.hw,
791 [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
792 [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,
793 [CLK_DRAM] = &dram_clk.common.hw,
794 [CLK_DRAM_VE] = &dram_ve_clk.common.hw,
795 [CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
796 [CLK_DRAM_DEINTERLACE] = &dram_deinterlace_clk.common.hw,
797 [CLK_DRAM_TS] = &dram_ts_clk.common.hw,
798 [CLK_DE] = &de_clk.common.hw,
799 [CLK_TCON0] = &tcon0_clk.common.hw,
800 [CLK_TCON1] = &tcon1_clk.common.hw,
801 [CLK_DEINTERLACE] = &deinterlace_clk.common.hw,
802 [CLK_CSI_MISC] = &csi_misc_clk.common.hw,
803 [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw,
804 [CLK_CSI_MCLK] = &csi_mclk_clk.common.hw,
805 [CLK_VE] = &ve_clk.common.hw,
806 [CLK_AC_DIG] = &ac_dig_clk.common.hw,
807 [CLK_AC_DIG_4X] = &ac_dig_4x_clk.common.hw,
808 [CLK_AVS] = &avs_clk.common.hw,
809 [CLK_HDMI] = &hdmi_clk.common.hw,
810 [CLK_HDMI_DDC] = &hdmi_ddc_clk.common.hw,
811 [CLK_MBUS] = &mbus_clk.common.hw,
812 [CLK_DSI_DPHY] = &dsi_dphy_clk.common.hw,
813 [CLK_GPU] = &gpu_clk.common.hw,
818 static struct ccu_reset_map sun50i_a64_ccu_resets[] = {
819 [RST_USB_PHY0] = { 0x0cc, BIT(0) },
820 [RST_USB_PHY1] = { 0x0cc, BIT(1) },
821 [RST_USB_HSIC] = { 0x0cc, BIT(2) },
823 [RST_DRAM] = { 0x0f4, BIT(31) },
824 [RST_MBUS] = { 0x0fc, BIT(31) },
826 [RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) },
827 [RST_BUS_CE] = { 0x2c0, BIT(5) },
828 [RST_BUS_DMA] = { 0x2c0, BIT(6) },
829 [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
830 [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
831 [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
832 [RST_BUS_NAND] = { 0x2c0, BIT(13) },
833 [RST_BUS_DRAM] = { 0x2c0, BIT(14) },
834 [RST_BUS_EMAC] = { 0x2c0, BIT(17) },
835 [RST_BUS_TS] = { 0x2c0, BIT(18) },
836 [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
837 [RST_BUS_SPI0] = { 0x2c0, BIT(20) },
838 [RST_BUS_SPI1] = { 0x2c0, BIT(21) },
839 [RST_BUS_OTG] = { 0x2c0, BIT(23) },
840 [RST_BUS_EHCI0] = { 0x2c0, BIT(24) },
841 [RST_BUS_EHCI1] = { 0x2c0, BIT(25) },
842 [RST_BUS_OHCI0] = { 0x2c0, BIT(28) },
843 [RST_BUS_OHCI1] = { 0x2c0, BIT(29) },
845 [RST_BUS_VE] = { 0x2c4, BIT(0) },
846 [RST_BUS_TCON0] = { 0x2c4, BIT(3) },
847 [RST_BUS_TCON1] = { 0x2c4, BIT(4) },
848 [RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) },
849 [RST_BUS_CSI] = { 0x2c4, BIT(8) },
850 [RST_BUS_HDMI0] = { 0x2c4, BIT(10) },
851 [RST_BUS_HDMI1] = { 0x2c4, BIT(11) },
852 [RST_BUS_DE] = { 0x2c4, BIT(12) },
853 [RST_BUS_GPU] = { 0x2c4, BIT(20) },
854 [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) },
855 [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) },
856 [RST_BUS_DBG] = { 0x2c4, BIT(31) },
858 [RST_BUS_LVDS] = { 0x2c8, BIT(0) },
860 [RST_BUS_CODEC] = { 0x2d0, BIT(0) },
861 [RST_BUS_SPDIF] = { 0x2d0, BIT(1) },
862 [RST_BUS_THS] = { 0x2d0, BIT(8) },
863 [RST_BUS_I2S0] = { 0x2d0, BIT(12) },
864 [RST_BUS_I2S1] = { 0x2d0, BIT(13) },
865 [RST_BUS_I2S2] = { 0x2d0, BIT(14) },
867 [RST_BUS_I2C0] = { 0x2d8, BIT(0) },
868 [RST_BUS_I2C1] = { 0x2d8, BIT(1) },
869 [RST_BUS_I2C2] = { 0x2d8, BIT(2) },
870 [RST_BUS_SCR] = { 0x2d8, BIT(5) },
871 [RST_BUS_UART0] = { 0x2d8, BIT(16) },
872 [RST_BUS_UART1] = { 0x2d8, BIT(17) },
873 [RST_BUS_UART2] = { 0x2d8, BIT(18) },
874 [RST_BUS_UART3] = { 0x2d8, BIT(19) },
875 [RST_BUS_UART4] = { 0x2d8, BIT(20) },
878 static const struct sunxi_ccu_desc sun50i_a64_ccu_desc = {
879 .ccu_clks = sun50i_a64_ccu_clks,
880 .num_ccu_clks = ARRAY_SIZE(sun50i_a64_ccu_clks),
882 .hw_clks = &sun50i_a64_hw_clks,
884 .resets = sun50i_a64_ccu_resets,
885 .num_resets = ARRAY_SIZE(sun50i_a64_ccu_resets),
888 static struct ccu_pll_nb sun50i_a64_pll_cpu_nb = {
889 .common = &pll_cpux_clk.common,
890 /* copy from pll_cpux_clk */
895 static struct ccu_mux_nb sun50i_a64_cpu_nb = {
896 .common = &cpux_clk.common,
898 .delay_us = 1, /* > 8 clock cycles at 24 MHz */
899 .bypass_index = 1, /* index of 24 MHz oscillator */
902 static int sun50i_a64_ccu_probe(struct platform_device *pdev)
904 struct resource *res;
909 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
910 reg = devm_ioremap_resource(&pdev->dev, res);
914 /* Force the PLL-Audio-1x divider to 4 */
915 val = readl(reg + SUN50I_A64_PLL_AUDIO_REG);
916 val &= ~GENMASK(19, 16);
917 writel(val | (3 << 16), reg + SUN50I_A64_PLL_AUDIO_REG);
919 writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);
921 ret = sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_a64_ccu_desc);
925 /* Gate then ungate PLL CPU after any rate changes */
926 ccu_pll_notifier_register(&sun50i_a64_pll_cpu_nb);
928 /* Reparent CPU during PLL CPU rate changes */
929 ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
935 static const struct of_device_id sun50i_a64_ccu_ids[] = {
936 { .compatible = "allwinner,sun50i-a64-ccu" },
940 static struct platform_driver sun50i_a64_ccu_driver = {
941 .probe = sun50i_a64_ccu_probe,
943 .name = "sun50i-a64-ccu",
944 .of_match_table = sun50i_a64_ccu_ids,
947 builtin_platform_driver(sun50i_a64_ccu_driver);