2 * Copyright (c) 2016 Maxime Ripard. All rights reserved.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/clk-provider.h>
15 #include <linux/of_address.h>
16 #include <linux/platform_device.h>
18 #include "ccu_common.h"
19 #include "ccu_reset.h"
29 #include "ccu_phase.h"
31 #include "ccu-sun50i-a64.h"
33 static struct ccu_nkmp pll_cpux_clk = {
36 .n = _SUNXI_CCU_MULT(8, 5),
37 .k = _SUNXI_CCU_MULT(4, 2),
38 .m = _SUNXI_CCU_DIV(0, 2),
39 .p = _SUNXI_CCU_DIV_MAX(16, 2, 4),
42 .hw.init = CLK_HW_INIT("pll-cpux",
50 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
51 * the base (2x, 4x and 8x), and one variable divider (the one true
54 * We don't have any need for the variable divider for now, so we just
55 * hardcode it to match with the clock names
57 #define SUN50I_A64_PLL_AUDIO_REG 0x008
59 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
67 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0",
71 BIT(24), /* frac enable */
72 BIT(25), /* frac select */
73 270000000, /* frac rate 0 */
74 297000000, /* frac rate 1 */
79 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
83 BIT(24), /* frac enable */
84 BIT(25), /* frac select */
85 270000000, /* frac rate 0 */
86 297000000, /* frac rate 1 */
91 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
100 static struct ccu_nk pll_periph0_clk = {
103 .n = _SUNXI_CCU_MULT(8, 5),
104 .k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
108 .features = CCU_FEATURE_FIXED_POSTDIV,
109 .hw.init = CLK_HW_INIT("pll-periph0", "osc24M",
110 &ccu_nk_ops, CLK_SET_RATE_UNGATE),
114 static struct ccu_nk pll_periph1_clk = {
117 .n = _SUNXI_CCU_MULT(8, 5),
118 .k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
122 .features = CCU_FEATURE_FIXED_POSTDIV,
123 .hw.init = CLK_HW_INIT("pll-periph1", "osc24M",
124 &ccu_nk_ops, CLK_SET_RATE_UNGATE),
128 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1",
132 BIT(24), /* frac enable */
133 BIT(25), /* frac select */
134 270000000, /* frac rate 0 */
135 297000000, /* frac rate 1 */
138 CLK_SET_RATE_UNGATE);
140 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
144 BIT(24), /* frac enable */
145 BIT(25), /* frac select */
146 270000000, /* frac rate 0 */
147 297000000, /* frac rate 1 */
150 CLK_SET_RATE_UNGATE);
153 * The output function can be changed to something more complex that
154 * we do not handle yet.
156 * Hardcode the mode so that we don't fall in that case.
158 #define SUN50I_A64_PLL_MIPI_REG 0x040
160 static struct ccu_nkm pll_mipi_clk = {
162 * The bit 23 and 22 are called "LDO{1,2}_EN" on the SoC's
163 * user manual, and by experiments the PLL doesn't work without
164 * these bits toggled.
166 .enable = BIT(31) | BIT(23) | BIT(22),
168 .n = _SUNXI_CCU_MULT(8, 4),
169 .k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
170 .m = _SUNXI_CCU_DIV(0, 4),
173 .hw.init = CLK_HW_INIT("pll-mipi", "pll-video0",
174 &ccu_nkm_ops, CLK_SET_RATE_UNGATE),
178 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_hsic_clk, "pll-hsic",
182 BIT(24), /* frac enable */
183 BIT(25), /* frac select */
184 270000000, /* frac rate 0 */
185 297000000, /* frac rate 1 */
188 CLK_SET_RATE_UNGATE);
190 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
194 BIT(24), /* frac enable */
195 BIT(25), /* frac select */
196 270000000, /* frac rate 0 */
197 297000000, /* frac rate 1 */
200 CLK_SET_RATE_UNGATE);
202 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1",
208 CLK_SET_RATE_UNGATE);
210 static const char * const cpux_parents[] = { "osc32k", "osc24M",
211 "pll-cpux", "pll-cpux" };
212 static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
213 0x050, 16, 2, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
215 static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
217 static const char * const ahb1_parents[] = { "osc32k", "osc24M",
218 "axi", "pll-periph0" };
219 static const struct ccu_mux_var_prediv ahb1_predivs[] = {
220 { .index = 3, .shift = 6, .width = 2 },
222 static struct ccu_div ahb1_clk = {
223 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
229 .var_predivs = ahb1_predivs,
230 .n_var_predivs = ARRAY_SIZE(ahb1_predivs),
235 .features = CCU_FEATURE_VARIABLE_PREDIV,
236 .hw.init = CLK_HW_INIT_PARENTS("ahb1",
243 static struct clk_div_table apb1_div_table[] = {
244 { .val = 0, .div = 2 },
245 { .val = 1, .div = 2 },
246 { .val = 2, .div = 4 },
247 { .val = 3, .div = 8 },
250 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
251 0x054, 8, 2, apb1_div_table, 0);
253 static const char * const apb2_parents[] = { "osc32k", "osc24M",
256 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
262 static const char * const ahb2_parents[] = { "ahb1", "pll-periph0" };
263 static const struct ccu_mux_fixed_prediv ahb2_fixed_predivs[] = {
264 { .index = 1, .div = 2 },
266 static struct ccu_mux ahb2_clk = {
270 .fixed_predivs = ahb2_fixed_predivs,
271 .n_predivs = ARRAY_SIZE(ahb2_fixed_predivs),
276 .features = CCU_FEATURE_FIXED_PREDIV,
277 .hw.init = CLK_HW_INIT_PARENTS("ahb2",
284 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
286 static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1",
288 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
290 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
292 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
294 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
296 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
298 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
300 static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb2",
302 static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb1",
304 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
306 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1",
308 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1",
310 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",
312 static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb1",
314 static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb2",
316 static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb1",
318 static SUNXI_CCU_GATE(bus_ohci1_clk, "bus-ohci1", "ahb2",
321 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1",
323 static SUNXI_CCU_GATE(bus_tcon0_clk, "bus-tcon0", "ahb1",
325 static SUNXI_CCU_GATE(bus_tcon1_clk, "bus-tcon1", "ahb1",
327 static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "ahb1",
329 static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1",
331 static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb1",
333 static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb1",
335 static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1",
337 static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1",
339 static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",
342 static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1",
344 static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1",
346 static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1",
348 static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1",
350 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1",
352 static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1",
354 static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1",
357 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
359 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
361 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",
363 static SUNXI_CCU_GATE(bus_scr_clk, "bus-scr", "apb2",
365 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",
367 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",
369 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
371 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2",
373 static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2",
376 static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "ahb1",
379 static struct clk_div_table ths_div_table[] = {
380 { .val = 0, .div = 1 },
381 { .val = 1, .div = 2 },
382 { .val = 2, .div = 4 },
383 { .val = 3, .div = 6 },
386 static const char * const ths_parents[] = { "osc24M" };
387 static struct ccu_div ths_clk = {
389 .div = _SUNXI_CCU_DIV_TABLE(0, 2, ths_div_table),
390 .mux = _SUNXI_CCU_MUX(24, 2),
393 .hw.init = CLK_HW_INIT_PARENTS("ths",
400 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0",
402 static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
410 * MMC clocks are the new timing mode (see A83T & H3) variety, but without
411 * the mode switch. This means they have a 2x post divider between the clock
412 * and the MMC module. This is not documented in the manual, but is taken
413 * into consideration when setting the mmc module clocks in the BSP kernel.
414 * Without it, MMC performance is degraded.
416 * We model it here to be consistent with other SoCs supporting this mode.
417 * The alternative would be to add the 2x multiplier when setting the MMC
418 * module clock in the MMC driver, just for the A64.
420 static const char * const mmc_default_parents[] = { "osc24M", "pll-periph0-2x",
422 static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc0_clk, "mmc0",
423 mmc_default_parents, 0x088,
431 static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1",
432 mmc_default_parents, 0x08c,
440 static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc2_clk, "mmc2",
441 mmc_default_parents, 0x090,
449 static const char * const ts_parents[] = { "osc24M", "pll-periph0", };
450 static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x098,
457 static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", mmc_default_parents, 0x09c,
464 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
471 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
478 static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
479 "pll-audio-2x", "pll-audio" };
480 static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents,
481 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
483 static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents,
484 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
486 static SUNXI_CCU_MUX_WITH_GATE(i2s2_clk, "i2s2", i2s_parents,
487 0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
489 static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio",
490 0x0c0, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
492 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
494 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
496 static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic",
498 static SUNXI_CCU_GATE(usb_hsic_12m_clk, "usb-hsic-12M", "osc12M",
500 static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M",
502 static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "usb-ohci0",
505 static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1" };
506 static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents,
507 0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL);
509 static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram",
511 static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "dram",
513 static SUNXI_CCU_GATE(dram_deinterlace_clk, "dram-deinterlace", "dram",
515 static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "dram",
518 static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };
519 static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
520 0x104, 0, 4, 24, 3, BIT(31), 0);
522 static const char * const tcon0_parents[] = { "pll-mipi", "pll-video0-2x" };
523 static const u8 tcon0_table[] = { 0, 2, };
524 static SUNXI_CCU_MUX_TABLE_WITH_GATE(tcon0_clk, "tcon0", tcon0_parents,
525 tcon0_table, 0x118, 24, 3, BIT(31),
526 CLK_SET_RATE_PARENT);
528 static const char * const tcon1_parents[] = { "pll-video0", "pll-video1" };
529 static const u8 tcon1_table[] = { 0, 2, };
530 static struct ccu_div tcon1_clk = {
532 .div = _SUNXI_CCU_DIV(0, 4),
533 .mux = _SUNXI_CCU_MUX_TABLE(24, 2, tcon1_table),
536 .hw.init = CLK_HW_INIT_PARENTS("tcon1",
539 CLK_SET_RATE_PARENT),
543 static const char * const deinterlace_parents[] = { "pll-periph0", "pll-periph1" };
544 static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace", deinterlace_parents,
545 0x124, 0, 4, 24, 3, BIT(31), 0);
547 static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M",
550 static const char * const csi_sclk_parents[] = { "pll-periph0", "pll-periph1" };
551 static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents,
552 0x134, 16, 4, 24, 3, BIT(31), 0);
554 static const char * const csi_mclk_parents[] = { "osc24M", "pll-video1", "pll-periph1" };
555 static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents,
556 0x134, 0, 5, 8, 3, BIT(15), 0);
558 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
559 0x13c, 16, 3, BIT(31), 0);
561 static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio",
562 0x140, BIT(31), CLK_SET_RATE_PARENT);
564 static SUNXI_CCU_GATE(ac_dig_4x_clk, "ac-dig-4x", "pll-audio-4x",
565 0x140, BIT(30), CLK_SET_RATE_PARENT);
567 static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",
570 static const char * const hdmi_parents[] = { "pll-video0", "pll-video1" };
571 static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
572 0x150, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
574 static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M",
577 static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x",
578 "pll-ddr0", "pll-ddr1" };
579 static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
580 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
582 static const char * const dsi_dphy_parents[] = { "pll-video0", "pll-periph0" };
583 static const u8 dsi_dphy_table[] = { 0, 2, };
584 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy",
585 dsi_dphy_parents, dsi_dphy_table,
586 0x168, 0, 4, 8, 2, BIT(15), CLK_SET_RATE_PARENT);
588 static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
589 0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
591 /* Fixed Factor clocks */
592 static CLK_FIXED_FACTOR(osc12M_clk, "osc12M", "osc24M", 2, 1, 0);
594 /* We hardcode the divider to 4 for now */
595 static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
596 "pll-audio-base", 4, 1, CLK_SET_RATE_PARENT);
597 static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
598 "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
599 static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
600 "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
601 static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
602 "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
603 static CLK_FIXED_FACTOR(pll_periph0_2x_clk, "pll-periph0-2x",
604 "pll-periph0", 1, 2, 0);
605 static CLK_FIXED_FACTOR(pll_periph1_2x_clk, "pll-periph1-2x",
606 "pll-periph1", 1, 2, 0);
607 static CLK_FIXED_FACTOR(pll_video0_2x_clk, "pll-video0-2x",
608 "pll-video0", 1, 2, CLK_SET_RATE_PARENT);
610 static struct ccu_common *sun50i_a64_ccu_clks[] = {
611 &pll_cpux_clk.common,
612 &pll_audio_base_clk.common,
613 &pll_video0_clk.common,
615 &pll_ddr0_clk.common,
616 &pll_periph0_clk.common,
617 &pll_periph1_clk.common,
618 &pll_video1_clk.common,
620 &pll_mipi_clk.common,
621 &pll_hsic_clk.common,
623 &pll_ddr1_clk.common,
630 &bus_mipi_dsi_clk.common,
633 &bus_mmc0_clk.common,
634 &bus_mmc1_clk.common,
635 &bus_mmc2_clk.common,
636 &bus_nand_clk.common,
637 &bus_dram_clk.common,
638 &bus_emac_clk.common,
640 &bus_hstimer_clk.common,
641 &bus_spi0_clk.common,
642 &bus_spi1_clk.common,
644 &bus_ehci0_clk.common,
645 &bus_ehci1_clk.common,
646 &bus_ohci0_clk.common,
647 &bus_ohci1_clk.common,
649 &bus_tcon0_clk.common,
650 &bus_tcon1_clk.common,
651 &bus_deinterlace_clk.common,
653 &bus_hdmi_clk.common,
656 &bus_msgbox_clk.common,
657 &bus_spinlock_clk.common,
658 &bus_codec_clk.common,
659 &bus_spdif_clk.common,
662 &bus_i2s0_clk.common,
663 &bus_i2s1_clk.common,
664 &bus_i2s2_clk.common,
665 &bus_i2c0_clk.common,
666 &bus_i2c1_clk.common,
667 &bus_i2c2_clk.common,
669 &bus_uart0_clk.common,
670 &bus_uart1_clk.common,
671 &bus_uart2_clk.common,
672 &bus_uart3_clk.common,
673 &bus_uart4_clk.common,
688 &usb_phy0_clk.common,
689 &usb_phy1_clk.common,
690 &usb_hsic_clk.common,
691 &usb_hsic_12m_clk.common,
692 &usb_ohci0_clk.common,
693 &usb_ohci1_clk.common,
696 &dram_csi_clk.common,
697 &dram_deinterlace_clk.common,
702 &deinterlace_clk.common,
703 &csi_misc_clk.common,
704 &csi_sclk_clk.common,
705 &csi_mclk_clk.common,
708 &ac_dig_4x_clk.common,
711 &hdmi_ddc_clk.common,
713 &dsi_dphy_clk.common,
717 static struct clk_hw_onecell_data sun50i_a64_hw_clks = {
719 [CLK_OSC_12M] = &osc12M_clk.hw,
720 [CLK_PLL_CPUX] = &pll_cpux_clk.common.hw,
721 [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
722 [CLK_PLL_AUDIO] = &pll_audio_clk.hw,
723 [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
724 [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
725 [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
726 [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw,
727 [CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw,
728 [CLK_PLL_VE] = &pll_ve_clk.common.hw,
729 [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw,
730 [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw,
731 [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw,
732 [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw,
733 [CLK_PLL_PERIPH1_2X] = &pll_periph1_2x_clk.hw,
734 [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw,
735 [CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
736 [CLK_PLL_MIPI] = &pll_mipi_clk.common.hw,
737 [CLK_PLL_HSIC] = &pll_hsic_clk.common.hw,
738 [CLK_PLL_DE] = &pll_de_clk.common.hw,
739 [CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw,
740 [CLK_CPUX] = &cpux_clk.common.hw,
741 [CLK_AXI] = &axi_clk.common.hw,
742 [CLK_AHB1] = &ahb1_clk.common.hw,
743 [CLK_APB1] = &apb1_clk.common.hw,
744 [CLK_APB2] = &apb2_clk.common.hw,
745 [CLK_AHB2] = &ahb2_clk.common.hw,
746 [CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw,
747 [CLK_BUS_CE] = &bus_ce_clk.common.hw,
748 [CLK_BUS_DMA] = &bus_dma_clk.common.hw,
749 [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
750 [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
751 [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
752 [CLK_BUS_NAND] = &bus_nand_clk.common.hw,
753 [CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
754 [CLK_BUS_EMAC] = &bus_emac_clk.common.hw,
755 [CLK_BUS_TS] = &bus_ts_clk.common.hw,
756 [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
757 [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
758 [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
759 [CLK_BUS_OTG] = &bus_otg_clk.common.hw,
760 [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw,
761 [CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw,
762 [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw,
763 [CLK_BUS_OHCI1] = &bus_ohci1_clk.common.hw,
764 [CLK_BUS_VE] = &bus_ve_clk.common.hw,
765 [CLK_BUS_TCON0] = &bus_tcon0_clk.common.hw,
766 [CLK_BUS_TCON1] = &bus_tcon1_clk.common.hw,
767 [CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw,
768 [CLK_BUS_CSI] = &bus_csi_clk.common.hw,
769 [CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw,
770 [CLK_BUS_DE] = &bus_de_clk.common.hw,
771 [CLK_BUS_GPU] = &bus_gpu_clk.common.hw,
772 [CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw,
773 [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw,
774 [CLK_BUS_CODEC] = &bus_codec_clk.common.hw,
775 [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw,
776 [CLK_BUS_PIO] = &bus_pio_clk.common.hw,
777 [CLK_BUS_THS] = &bus_ths_clk.common.hw,
778 [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
779 [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw,
780 [CLK_BUS_I2S2] = &bus_i2s2_clk.common.hw,
781 [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
782 [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
783 [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
784 [CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
785 [CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
786 [CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
787 [CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
788 [CLK_BUS_UART4] = &bus_uart4_clk.common.hw,
789 [CLK_BUS_SCR] = &bus_scr_clk.common.hw,
790 [CLK_BUS_DBG] = &bus_dbg_clk.common.hw,
791 [CLK_THS] = &ths_clk.common.hw,
792 [CLK_NAND] = &nand_clk.common.hw,
793 [CLK_MMC0] = &mmc0_clk.common.hw,
794 [CLK_MMC1] = &mmc1_clk.common.hw,
795 [CLK_MMC2] = &mmc2_clk.common.hw,
796 [CLK_TS] = &ts_clk.common.hw,
797 [CLK_CE] = &ce_clk.common.hw,
798 [CLK_SPI0] = &spi0_clk.common.hw,
799 [CLK_SPI1] = &spi1_clk.common.hw,
800 [CLK_I2S0] = &i2s0_clk.common.hw,
801 [CLK_I2S1] = &i2s1_clk.common.hw,
802 [CLK_I2S2] = &i2s2_clk.common.hw,
803 [CLK_SPDIF] = &spdif_clk.common.hw,
804 [CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
805 [CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
806 [CLK_USB_HSIC] = &usb_hsic_clk.common.hw,
807 [CLK_USB_HSIC_12M] = &usb_hsic_12m_clk.common.hw,
808 [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
809 [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,
810 [CLK_DRAM] = &dram_clk.common.hw,
811 [CLK_DRAM_VE] = &dram_ve_clk.common.hw,
812 [CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
813 [CLK_DRAM_DEINTERLACE] = &dram_deinterlace_clk.common.hw,
814 [CLK_DRAM_TS] = &dram_ts_clk.common.hw,
815 [CLK_DE] = &de_clk.common.hw,
816 [CLK_TCON0] = &tcon0_clk.common.hw,
817 [CLK_TCON1] = &tcon1_clk.common.hw,
818 [CLK_DEINTERLACE] = &deinterlace_clk.common.hw,
819 [CLK_CSI_MISC] = &csi_misc_clk.common.hw,
820 [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw,
821 [CLK_CSI_MCLK] = &csi_mclk_clk.common.hw,
822 [CLK_VE] = &ve_clk.common.hw,
823 [CLK_AC_DIG] = &ac_dig_clk.common.hw,
824 [CLK_AC_DIG_4X] = &ac_dig_4x_clk.common.hw,
825 [CLK_AVS] = &avs_clk.common.hw,
826 [CLK_HDMI] = &hdmi_clk.common.hw,
827 [CLK_HDMI_DDC] = &hdmi_ddc_clk.common.hw,
828 [CLK_MBUS] = &mbus_clk.common.hw,
829 [CLK_DSI_DPHY] = &dsi_dphy_clk.common.hw,
830 [CLK_GPU] = &gpu_clk.common.hw,
835 static struct ccu_reset_map sun50i_a64_ccu_resets[] = {
836 [RST_USB_PHY0] = { 0x0cc, BIT(0) },
837 [RST_USB_PHY1] = { 0x0cc, BIT(1) },
838 [RST_USB_HSIC] = { 0x0cc, BIT(2) },
840 [RST_DRAM] = { 0x0f4, BIT(31) },
841 [RST_MBUS] = { 0x0fc, BIT(31) },
843 [RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) },
844 [RST_BUS_CE] = { 0x2c0, BIT(5) },
845 [RST_BUS_DMA] = { 0x2c0, BIT(6) },
846 [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
847 [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
848 [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
849 [RST_BUS_NAND] = { 0x2c0, BIT(13) },
850 [RST_BUS_DRAM] = { 0x2c0, BIT(14) },
851 [RST_BUS_EMAC] = { 0x2c0, BIT(17) },
852 [RST_BUS_TS] = { 0x2c0, BIT(18) },
853 [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
854 [RST_BUS_SPI0] = { 0x2c0, BIT(20) },
855 [RST_BUS_SPI1] = { 0x2c0, BIT(21) },
856 [RST_BUS_OTG] = { 0x2c0, BIT(23) },
857 [RST_BUS_EHCI0] = { 0x2c0, BIT(24) },
858 [RST_BUS_EHCI1] = { 0x2c0, BIT(25) },
859 [RST_BUS_OHCI0] = { 0x2c0, BIT(28) },
860 [RST_BUS_OHCI1] = { 0x2c0, BIT(29) },
862 [RST_BUS_VE] = { 0x2c4, BIT(0) },
863 [RST_BUS_TCON0] = { 0x2c4, BIT(3) },
864 [RST_BUS_TCON1] = { 0x2c4, BIT(4) },
865 [RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) },
866 [RST_BUS_CSI] = { 0x2c4, BIT(8) },
867 [RST_BUS_HDMI0] = { 0x2c4, BIT(10) },
868 [RST_BUS_HDMI1] = { 0x2c4, BIT(11) },
869 [RST_BUS_DE] = { 0x2c4, BIT(12) },
870 [RST_BUS_GPU] = { 0x2c4, BIT(20) },
871 [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) },
872 [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) },
873 [RST_BUS_DBG] = { 0x2c4, BIT(31) },
875 [RST_BUS_LVDS] = { 0x2c8, BIT(0) },
877 [RST_BUS_CODEC] = { 0x2d0, BIT(0) },
878 [RST_BUS_SPDIF] = { 0x2d0, BIT(1) },
879 [RST_BUS_THS] = { 0x2d0, BIT(8) },
880 [RST_BUS_I2S0] = { 0x2d0, BIT(12) },
881 [RST_BUS_I2S1] = { 0x2d0, BIT(13) },
882 [RST_BUS_I2S2] = { 0x2d0, BIT(14) },
884 [RST_BUS_I2C0] = { 0x2d8, BIT(0) },
885 [RST_BUS_I2C1] = { 0x2d8, BIT(1) },
886 [RST_BUS_I2C2] = { 0x2d8, BIT(2) },
887 [RST_BUS_SCR] = { 0x2d8, BIT(5) },
888 [RST_BUS_UART0] = { 0x2d8, BIT(16) },
889 [RST_BUS_UART1] = { 0x2d8, BIT(17) },
890 [RST_BUS_UART2] = { 0x2d8, BIT(18) },
891 [RST_BUS_UART3] = { 0x2d8, BIT(19) },
892 [RST_BUS_UART4] = { 0x2d8, BIT(20) },
895 static const struct sunxi_ccu_desc sun50i_a64_ccu_desc = {
896 .ccu_clks = sun50i_a64_ccu_clks,
897 .num_ccu_clks = ARRAY_SIZE(sun50i_a64_ccu_clks),
899 .hw_clks = &sun50i_a64_hw_clks,
901 .resets = sun50i_a64_ccu_resets,
902 .num_resets = ARRAY_SIZE(sun50i_a64_ccu_resets),
905 static struct ccu_pll_nb sun50i_a64_pll_cpu_nb = {
906 .common = &pll_cpux_clk.common,
907 /* copy from pll_cpux_clk */
912 static struct ccu_mux_nb sun50i_a64_cpu_nb = {
913 .common = &cpux_clk.common,
915 .delay_us = 1, /* > 8 clock cycles at 24 MHz */
916 .bypass_index = 1, /* index of 24 MHz oscillator */
919 static int sun50i_a64_ccu_probe(struct platform_device *pdev)
921 struct resource *res;
926 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
927 reg = devm_ioremap_resource(&pdev->dev, res);
931 /* Force the PLL-Audio-1x divider to 4 */
932 val = readl(reg + SUN50I_A64_PLL_AUDIO_REG);
933 val &= ~GENMASK(19, 16);
934 writel(val | (3 << 16), reg + SUN50I_A64_PLL_AUDIO_REG);
936 writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);
938 ret = sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_a64_ccu_desc);
942 /* Gate then ungate PLL CPU after any rate changes */
943 ccu_pll_notifier_register(&sun50i_a64_pll_cpu_nb);
945 /* Reparent CPU during PLL CPU rate changes */
946 ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
952 static const struct of_device_id sun50i_a64_ccu_ids[] = {
953 { .compatible = "allwinner,sun50i-a64-ccu" },
957 static struct platform_driver sun50i_a64_ccu_driver = {
958 .probe = sun50i_a64_ccu_probe,
960 .name = "sun50i-a64-ccu",
961 .of_match_table = sun50i_a64_ccu_ids,
964 builtin_platform_driver(sun50i_a64_ccu_driver);