1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2020 huangzhenwei@allwinnertech.com
4 * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
7 #include <linux/clk-provider.h>
8 #include <linux/module.h>
9 #include <linux/platform_device.h>
11 #include "ccu_common.h"
12 #include "ccu_reset.h"
17 #include "ccu-sun20i-d1-r.h"
19 static const struct clk_parent_data r_ahb_apb0_parents[] = {
20 { .fw_name = "hosc" },
21 { .fw_name = "losc" },
22 { .fw_name = "iosc" },
23 { .fw_name = "pll-periph" },
25 static SUNXI_CCU_MP_DATA_WITH_MUX(r_ahb_clk, "r-ahb",
26 r_ahb_apb0_parents, 0x000,
31 static const struct clk_hw *r_ahb_hw = &r_ahb_clk.common.hw;
33 static SUNXI_CCU_MP_DATA_WITH_MUX(r_apb0_clk, "r-apb0",
34 r_ahb_apb0_parents, 0x00c,
39 static const struct clk_hw *r_apb0_hw = &r_apb0_clk.common.hw;
41 static SUNXI_CCU_GATE_HWS(bus_r_timer_clk, "bus-r-timer", &r_apb0_hw,
43 static SUNXI_CCU_GATE_HWS(bus_r_twd_clk, "bus-r-twd", &r_apb0_hw,
45 static SUNXI_CCU_GATE_HWS(bus_r_ppu_clk, "bus-r-ppu", &r_apb0_hw,
48 static const struct clk_parent_data r_ir_rx_parents[] = {
49 { .fw_name = "losc" },
50 { .fw_name = "hosc" },
52 static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(r_ir_rx_clk, "r-ir-rx",
53 r_ir_rx_parents, 0x1c0,
60 static SUNXI_CCU_GATE_HWS(bus_r_ir_rx_clk, "bus-r-ir-rx", &r_apb0_hw,
62 static SUNXI_CCU_GATE_HWS(bus_r_rtc_clk, "bus-r-rtc", &r_ahb_hw,
64 static SUNXI_CCU_GATE_HWS(bus_r_cpucfg_clk, "bus-r-cpucfg", &r_apb0_hw,
67 static struct ccu_common *sun20i_d1_r_ccu_clks[] = {
70 &bus_r_timer_clk.common,
71 &bus_r_twd_clk.common,
72 &bus_r_ppu_clk.common,
74 &bus_r_ir_rx_clk.common,
75 &bus_r_rtc_clk.common,
76 &bus_r_cpucfg_clk.common,
79 static struct clk_hw_onecell_data sun20i_d1_r_hw_clks = {
82 [CLK_R_AHB] = &r_ahb_clk.common.hw,
83 [CLK_R_APB0] = &r_apb0_clk.common.hw,
84 [CLK_BUS_R_TIMER] = &bus_r_timer_clk.common.hw,
85 [CLK_BUS_R_TWD] = &bus_r_twd_clk.common.hw,
86 [CLK_BUS_R_PPU] = &bus_r_ppu_clk.common.hw,
87 [CLK_R_IR_RX] = &r_ir_rx_clk.common.hw,
88 [CLK_BUS_R_IR_RX] = &bus_r_ir_rx_clk.common.hw,
89 [CLK_BUS_R_RTC] = &bus_r_rtc_clk.common.hw,
90 [CLK_BUS_R_CPUCFG] = &bus_r_cpucfg_clk.common.hw,
94 static struct ccu_reset_map sun20i_d1_r_ccu_resets[] = {
95 [RST_BUS_R_TIMER] = { 0x11c, BIT(16) },
96 [RST_BUS_R_TWD] = { 0x12c, BIT(16) },
97 [RST_BUS_R_PPU] = { 0x1ac, BIT(16) },
98 [RST_BUS_R_IR_RX] = { 0x1cc, BIT(16) },
99 [RST_BUS_R_RTC] = { 0x20c, BIT(16) },
100 [RST_BUS_R_CPUCFG] = { 0x22c, BIT(16) },
103 static const struct sunxi_ccu_desc sun20i_d1_r_ccu_desc = {
104 .ccu_clks = sun20i_d1_r_ccu_clks,
105 .num_ccu_clks = ARRAY_SIZE(sun20i_d1_r_ccu_clks),
107 .hw_clks = &sun20i_d1_r_hw_clks,
109 .resets = sun20i_d1_r_ccu_resets,
110 .num_resets = ARRAY_SIZE(sun20i_d1_r_ccu_resets),
113 static int sun20i_d1_r_ccu_probe(struct platform_device *pdev)
117 reg = devm_platform_ioremap_resource(pdev, 0);
121 return devm_sunxi_ccu_probe(&pdev->dev, reg, &sun20i_d1_r_ccu_desc);
124 static const struct of_device_id sun20i_d1_r_ccu_ids[] = {
125 { .compatible = "allwinner,sun20i-d1-r-ccu" },
129 static struct platform_driver sun20i_d1_r_ccu_driver = {
130 .probe = sun20i_d1_r_ccu_probe,
132 .name = "sun20i-d1-r-ccu",
133 .suppress_bind_attrs = true,
134 .of_match_table = sun20i_d1_r_ccu_ids,
137 module_platform_driver(sun20i_d1_r_ccu_driver);
139 MODULE_IMPORT_NS(SUNXI_CCU);
140 MODULE_LICENSE("GPL");