2 * Copyright 2013 Emilio López
4 * Emilio López <emilio@elopez.com.ar>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/clk.h>
18 #include <linux/clk-provider.h>
19 #include <linux/clkdev.h>
21 #include <linux/of_address.h>
22 #include <linux/reset-controller.h>
23 #include <linux/slab.h>
24 #include <linux/spinlock.h>
25 #include <linux/log2.h>
27 #include "clk-factors.h"
29 static DEFINE_SPINLOCK(clk_lock);
31 /* Maximum number of parents our clocks have */
32 #define SUNXI_MAX_PARENTS 5
35 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
36 * PLL1 rate is calculated as follows
37 * rate = (parent_rate * n * (k + 1) >> p) / (m + 1);
38 * parent_rate is always 24Mhz
41 static void sun4i_get_pll1_factors(struct factors_request *req)
45 /* Normalize value to a 6M multiple */
46 div = req->rate / 6000000;
47 req->rate = 6000000 * div;
49 /* m is always zero for pll1 */
52 /* k is 1 only on these cases */
53 if (req->rate >= 768000000 || req->rate == 42000000 ||
54 req->rate == 54000000)
59 /* p will be 3 for divs under 10 */
63 /* p will be 2 for divs between 10 - 20 and odd divs under 32 */
64 else if (div < 20 || (div < 32 && (div & 1)))
67 /* p will be 1 for even divs under 32, divs under 40 and odd pairs
68 * of divs between 40-62 */
69 else if (div < 40 || (div < 64 && (div & 2)))
72 /* any other entries have p = 0 */
76 /* calculate a suitable n based on k and p */
83 * sun6i_a31_get_pll1_factors() - calculates n, k and m factors for PLL1
84 * PLL1 rate is calculated as follows
85 * rate = parent_rate * (n + 1) * (k + 1) / (m + 1);
86 * parent_rate should always be 24MHz
88 static void sun6i_a31_get_pll1_factors(struct factors_request *req)
91 * We can operate only on MHz, this will make our life easier
94 u32 freq_mhz = req->rate / 1000000;
95 u32 parent_freq_mhz = req->parent_rate / 1000000;
98 * Round down the frequency to the closest multiple of either
101 u32 round_freq_6 = rounddown(freq_mhz, 6);
102 u32 round_freq_16 = round_down(freq_mhz, 16);
104 if (round_freq_6 > round_freq_16)
105 freq_mhz = round_freq_6;
107 freq_mhz = round_freq_16;
109 req->rate = freq_mhz * 1000000;
111 /* If the frequency is a multiple of 32 MHz, k is always 3 */
112 if (!(freq_mhz % 32))
114 /* If the frequency is a multiple of 9 MHz, k is always 2 */
115 else if (!(freq_mhz % 9))
117 /* If the frequency is a multiple of 8 MHz, k is always 1 */
118 else if (!(freq_mhz % 8))
120 /* Otherwise, we don't use the k factor */
125 * If the frequency is a multiple of 2 but not a multiple of
126 * 3, m is 3. This is the first time we use 6 here, yet we
127 * will use it on several other places.
128 * We use this number because it's the lowest frequency we can
129 * generate (with n = 0, k = 0, m = 3), so every other frequency
130 * somehow relates to this frequency.
132 if ((freq_mhz % 6) == 2 || (freq_mhz % 6) == 4)
135 * If the frequency is a multiple of 6MHz, but the factor is
138 else if ((freq_mhz / 6) & 1)
140 /* Otherwise, we end up with m = 1 */
144 /* Calculate n thanks to the above factors we already got */
145 req->n = freq_mhz * (req->m + 1) / ((req->k + 1) * parent_freq_mhz)
149 * If n end up being outbound, and that we can still decrease
152 if ((req->n + 1) > 31 && (req->m + 1) > 1) {
153 req->n = (req->n + 1) / 2 - 1;
154 req->m = (req->m + 1) / 2 - 1;
159 * sun8i_a23_get_pll1_factors() - calculates n, k, m, p factors for PLL1
160 * PLL1 rate is calculated as follows
161 * rate = (parent_rate * (n + 1) * (k + 1) >> p) / (m + 1);
162 * parent_rate is always 24Mhz
165 static void sun8i_a23_get_pll1_factors(struct factors_request *req)
169 /* Normalize value to a 6M multiple */
170 div = req->rate / 6000000;
171 req->rate = 6000000 * div;
173 /* m is always zero for pll1 */
176 /* k is 1 only on these cases */
177 if (req->rate >= 768000000 || req->rate == 42000000 ||
178 req->rate == 54000000)
183 /* p will be 2 for divs under 20 and odd divs under 32 */
184 if (div < 20 || (div < 32 && (div & 1)))
187 /* p will be 1 for even divs under 32, divs under 40 and odd pairs
188 * of divs between 40-62 */
189 else if (div < 40 || (div < 64 && (div & 2)))
192 /* any other entries have p = 0 */
196 /* calculate a suitable n based on k and p */
199 req->n = div / 4 - 1;
203 * sun4i_get_pll5_factors() - calculates n, k factors for PLL5
204 * PLL5 rate is calculated as follows
205 * rate = parent_rate * n * (k + 1)
206 * parent_rate is always 24Mhz
209 static void sun4i_get_pll5_factors(struct factors_request *req)
213 /* Normalize value to a parent_rate multiple (24M) */
214 div = req->rate / req->parent_rate;
215 req->rate = req->parent_rate * div;
219 else if (div / 2 < 31)
221 else if (div / 3 < 31)
226 req->n = DIV_ROUND_UP(div, (req->k + 1));
230 * sun6i_a31_get_pll6_factors() - calculates n, k factors for A31 PLL6x2
231 * PLL6x2 rate is calculated as follows
232 * rate = parent_rate * (n + 1) * (k + 1)
233 * parent_rate is always 24Mhz
236 static void sun6i_a31_get_pll6_factors(struct factors_request *req)
240 /* Normalize value to a parent_rate multiple (24M) */
241 div = req->rate / req->parent_rate;
242 req->rate = req->parent_rate * div;
248 req->n = DIV_ROUND_UP(div, (req->k + 1)) - 1;
252 * sun5i_a13_get_ahb_factors() - calculates m, p factors for AHB
253 * AHB rate is calculated as follows
254 * rate = parent_rate >> p
257 static void sun5i_a13_get_ahb_factors(struct factors_request *req)
262 if (req->parent_rate < req->rate)
263 req->rate = req->parent_rate;
266 * user manual says valid speed is 8k ~ 276M, but tests show it
267 * can work at speeds up to 300M, just after reparenting to pll6
269 if (req->rate < 8000)
271 if (req->rate > 300000000)
272 req->rate = 300000000;
274 div = order_base_2(DIV_ROUND_UP(req->parent_rate, req->rate));
280 req->rate = req->parent_rate >> div;
285 #define SUN6I_AHB1_PARENT_PLL6 3
288 * sun6i_a31_get_ahb_factors() - calculates m, p factors for AHB
289 * AHB rate is calculated as follows
290 * rate = parent_rate >> p
292 * if parent is pll6, then
293 * parent_rate = pll6 rate / (m + 1)
296 static void sun6i_get_ahb1_factors(struct factors_request *req)
298 u8 div, calcp, calcm = 1;
301 * clock can only divide, so we will never be able to achieve
302 * frequencies higher than the parent frequency
304 if (req->parent_rate && req->rate > req->parent_rate)
305 req->rate = req->parent_rate;
307 div = DIV_ROUND_UP(req->parent_rate, req->rate);
309 /* calculate pre-divider if parent is pll6 */
310 if (req->parent_index == SUN6I_AHB1_PARENT_PLL6) {
313 else if (div / 2 < 4)
315 else if (div / 4 < 4)
320 calcm = DIV_ROUND_UP(div, 1 << calcp);
322 calcp = __roundup_pow_of_two(div);
323 calcp = calcp > 3 ? 3 : calcp;
326 req->rate = (req->parent_rate / calcm) >> calcp;
332 * sun6i_ahb1_recalc() - calculates AHB clock rate from m, p factors and
335 static void sun6i_ahb1_recalc(struct factors_request *req)
337 req->rate = req->parent_rate;
339 /* apply pre-divider first if parent is pll6 */
340 if (req->parent_index == SUN6I_AHB1_PARENT_PLL6)
341 req->rate /= req->m + 1;
344 req->rate >>= req->p;
348 * sun4i_get_apb1_factors() - calculates m, p factors for APB1
349 * APB1 rate is calculated as follows
350 * rate = (parent_rate >> p) / (m + 1);
353 static void sun4i_get_apb1_factors(struct factors_request *req)
358 if (req->parent_rate < req->rate)
359 req->rate = req->parent_rate;
361 div = DIV_ROUND_UP(req->parent_rate, req->rate);
376 calcm = (div >> calcp) - 1;
378 req->rate = (req->parent_rate >> calcp) / (calcm + 1);
387 * sun7i_a20_get_out_factors() - calculates m, p factors for CLK_OUT_A/B
388 * CLK_OUT rate is calculated as follows
389 * rate = (parent_rate >> p) / (m + 1);
392 static void sun7i_a20_get_out_factors(struct factors_request *req)
394 u8 div, calcm, calcp;
396 /* These clocks can only divide, so we will never be able to achieve
397 * frequencies higher than the parent frequency */
398 if (req->rate > req->parent_rate)
399 req->rate = req->parent_rate;
401 div = DIV_ROUND_UP(req->parent_rate, req->rate);
405 else if (div / 2 < 32)
407 else if (div / 4 < 32)
412 calcm = DIV_ROUND_UP(div, 1 << calcp);
414 req->rate = (req->parent_rate >> calcp) / calcm;
420 * sunxi_factors_clk_setup() - Setup function for factor clocks
423 static const struct clk_factors_config sun4i_pll1_config = {
434 static const struct clk_factors_config sun6i_a31_pll1_config = {
444 static const struct clk_factors_config sun8i_a23_pll1_config = {
456 static const struct clk_factors_config sun4i_pll5_config = {
463 static const struct clk_factors_config sun6i_a31_pll6_config = {
471 static const struct clk_factors_config sun5i_a13_ahb_config = {
476 static const struct clk_factors_config sun6i_ahb1_config = {
483 static const struct clk_factors_config sun4i_apb1_config = {
490 /* user manual says "n" but it's really "p" */
491 static const struct clk_factors_config sun7i_a20_out_config = {
498 static const struct factors_data sun4i_pll1_data __initconst = {
500 .table = &sun4i_pll1_config,
501 .getter = sun4i_get_pll1_factors,
504 static const struct factors_data sun6i_a31_pll1_data __initconst = {
506 .table = &sun6i_a31_pll1_config,
507 .getter = sun6i_a31_get_pll1_factors,
510 static const struct factors_data sun8i_a23_pll1_data __initconst = {
512 .table = &sun8i_a23_pll1_config,
513 .getter = sun8i_a23_get_pll1_factors,
516 static const struct factors_data sun7i_a20_pll4_data __initconst = {
518 .table = &sun4i_pll5_config,
519 .getter = sun4i_get_pll5_factors,
522 static const struct factors_data sun4i_pll5_data __initconst = {
524 .table = &sun4i_pll5_config,
525 .getter = sun4i_get_pll5_factors,
528 static const struct factors_data sun6i_a31_pll6_data __initconst = {
530 .table = &sun6i_a31_pll6_config,
531 .getter = sun6i_a31_get_pll6_factors,
534 static const struct factors_data sun5i_a13_ahb_data __initconst = {
536 .muxmask = BIT(1) | BIT(0),
537 .table = &sun5i_a13_ahb_config,
538 .getter = sun5i_a13_get_ahb_factors,
541 static const struct factors_data sun6i_ahb1_data __initconst = {
543 .muxmask = BIT(1) | BIT(0),
544 .table = &sun6i_ahb1_config,
545 .getter = sun6i_get_ahb1_factors,
546 .recalc = sun6i_ahb1_recalc,
549 static const struct factors_data sun4i_apb1_data __initconst = {
551 .muxmask = BIT(1) | BIT(0),
552 .table = &sun4i_apb1_config,
553 .getter = sun4i_get_apb1_factors,
556 static const struct factors_data sun7i_a20_out_data __initconst = {
559 .muxmask = BIT(1) | BIT(0),
560 .table = &sun7i_a20_out_config,
561 .getter = sun7i_a20_get_out_factors,
564 static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
565 const struct factors_data *data)
569 reg = of_iomap(node, 0);
571 pr_err("Could not get registers for factors-clk: %s\n",
576 return sunxi_factors_register(node, data, &clk_lock, reg);
579 static void __init sun4i_pll1_clk_setup(struct device_node *node)
581 sunxi_factors_clk_setup(node, &sun4i_pll1_data);
583 CLK_OF_DECLARE(sun4i_pll1, "allwinner,sun4i-a10-pll1-clk",
584 sun4i_pll1_clk_setup);
586 static void __init sun6i_pll1_clk_setup(struct device_node *node)
588 sunxi_factors_clk_setup(node, &sun6i_a31_pll1_data);
590 CLK_OF_DECLARE(sun6i_pll1, "allwinner,sun6i-a31-pll1-clk",
591 sun6i_pll1_clk_setup);
593 static void __init sun8i_pll1_clk_setup(struct device_node *node)
595 sunxi_factors_clk_setup(node, &sun8i_a23_pll1_data);
597 CLK_OF_DECLARE(sun8i_pll1, "allwinner,sun8i-a23-pll1-clk",
598 sun8i_pll1_clk_setup);
600 static void __init sun7i_pll4_clk_setup(struct device_node *node)
602 sunxi_factors_clk_setup(node, &sun7i_a20_pll4_data);
604 CLK_OF_DECLARE(sun7i_pll4, "allwinner,sun7i-a20-pll4-clk",
605 sun7i_pll4_clk_setup);
607 static void __init sun5i_ahb_clk_setup(struct device_node *node)
609 sunxi_factors_clk_setup(node, &sun5i_a13_ahb_data);
611 CLK_OF_DECLARE(sun5i_ahb, "allwinner,sun5i-a13-ahb-clk",
612 sun5i_ahb_clk_setup);
614 static void __init sun6i_ahb1_clk_setup(struct device_node *node)
616 sunxi_factors_clk_setup(node, &sun6i_ahb1_data);
618 CLK_OF_DECLARE(sun6i_a31_ahb1, "allwinner,sun6i-a31-ahb1-clk",
619 sun6i_ahb1_clk_setup);
621 static void __init sun4i_apb1_clk_setup(struct device_node *node)
623 sunxi_factors_clk_setup(node, &sun4i_apb1_data);
625 CLK_OF_DECLARE(sun4i_apb1, "allwinner,sun4i-a10-apb1-clk",
626 sun4i_apb1_clk_setup);
628 static void __init sun7i_out_clk_setup(struct device_node *node)
630 sunxi_factors_clk_setup(node, &sun7i_a20_out_data);
632 CLK_OF_DECLARE(sun7i_out, "allwinner,sun7i-a20-out-clk",
633 sun7i_out_clk_setup);
637 * sunxi_mux_clk_setup() - Setup function for muxes
640 #define SUNXI_MUX_GATE_WIDTH 2
646 static const struct mux_data sun4i_cpu_mux_data __initconst = {
650 static const struct mux_data sun6i_a31_ahb1_mux_data __initconst = {
654 static const struct mux_data sun8i_h3_ahb2_mux_data __initconst = {
658 static struct clk * __init sunxi_mux_clk_setup(struct device_node *node,
659 const struct mux_data *data)
662 const char *clk_name = node->name;
663 const char *parents[SUNXI_MAX_PARENTS];
667 reg = of_iomap(node, 0);
669 pr_err("Could not map registers for mux-clk: %pOF\n", node);
673 i = of_clk_parent_fill(node, parents, SUNXI_MAX_PARENTS);
674 if (of_property_read_string(node, "clock-output-names", &clk_name)) {
675 pr_err("%s: could not read clock-output-names from \"%pOF\"\n",
680 clk = clk_register_mux(NULL, clk_name, parents, i,
681 CLK_SET_RATE_PARENT, reg,
682 data->shift, SUNXI_MUX_GATE_WIDTH,
686 pr_err("%s: failed to register mux clock %s: %ld\n", __func__,
687 clk_name, PTR_ERR(clk));
691 if (of_clk_add_provider(node, of_clk_src_simple_get, clk)) {
692 pr_err("%s: failed to add clock provider for %s\n",
694 clk_unregister_divider(clk);
704 static void __init sun4i_cpu_clk_setup(struct device_node *node)
708 clk = sunxi_mux_clk_setup(node, &sun4i_cpu_mux_data);
712 /* Protect CPU clock */
714 clk_prepare_enable(clk);
716 CLK_OF_DECLARE(sun4i_cpu, "allwinner,sun4i-a10-cpu-clk",
717 sun4i_cpu_clk_setup);
719 static void __init sun6i_ahb1_mux_clk_setup(struct device_node *node)
721 sunxi_mux_clk_setup(node, &sun6i_a31_ahb1_mux_data);
723 CLK_OF_DECLARE(sun6i_ahb1_mux, "allwinner,sun6i-a31-ahb1-mux-clk",
724 sun6i_ahb1_mux_clk_setup);
726 static void __init sun8i_ahb2_clk_setup(struct device_node *node)
728 sunxi_mux_clk_setup(node, &sun8i_h3_ahb2_mux_data);
730 CLK_OF_DECLARE(sun8i_ahb2, "allwinner,sun8i-h3-ahb2-clk",
731 sun8i_ahb2_clk_setup);
735 * sunxi_divider_clk_setup() - Setup function for simple divider clocks
742 const struct clk_div_table *table;
745 static const struct div_data sun4i_axi_data __initconst = {
751 static const struct clk_div_table sun8i_a23_axi_table[] __initconst = {
752 { .val = 0, .div = 1 },
753 { .val = 1, .div = 2 },
754 { .val = 2, .div = 3 },
755 { .val = 3, .div = 4 },
756 { .val = 4, .div = 4 },
757 { .val = 5, .div = 4 },
758 { .val = 6, .div = 4 },
759 { .val = 7, .div = 4 },
763 static const struct div_data sun8i_a23_axi_data __initconst = {
765 .table = sun8i_a23_axi_table,
768 static const struct div_data sun4i_ahb_data __initconst = {
774 static const struct clk_div_table sun4i_apb0_table[] __initconst = {
775 { .val = 0, .div = 2 },
776 { .val = 1, .div = 2 },
777 { .val = 2, .div = 4 },
778 { .val = 3, .div = 8 },
782 static const struct div_data sun4i_apb0_data __initconst = {
786 .table = sun4i_apb0_table,
789 static void __init sunxi_divider_clk_setup(struct device_node *node,
790 const struct div_data *data)
793 const char *clk_name = node->name;
794 const char *clk_parent;
797 reg = of_iomap(node, 0);
799 pr_err("Could not map registers for mux-clk: %pOF\n", node);
803 clk_parent = of_clk_get_parent_name(node, 0);
805 if (of_property_read_string(node, "clock-output-names", &clk_name)) {
806 pr_err("%s: could not read clock-output-names from \"%pOF\"\n",
811 clk = clk_register_divider_table(NULL, clk_name, clk_parent, 0,
812 reg, data->shift, data->width,
813 data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0,
814 data->table, &clk_lock);
816 pr_err("%s: failed to register divider clock %s: %ld\n",
817 __func__, clk_name, PTR_ERR(clk));
821 if (of_clk_add_provider(node, of_clk_src_simple_get, clk)) {
822 pr_err("%s: failed to add clock provider for %s\n",
827 if (clk_register_clkdev(clk, clk_name, NULL)) {
828 of_clk_del_provider(node);
834 clk_unregister_divider(clk);
840 static void __init sun4i_ahb_clk_setup(struct device_node *node)
842 sunxi_divider_clk_setup(node, &sun4i_ahb_data);
844 CLK_OF_DECLARE(sun4i_ahb, "allwinner,sun4i-a10-ahb-clk",
845 sun4i_ahb_clk_setup);
847 static void __init sun4i_apb0_clk_setup(struct device_node *node)
849 sunxi_divider_clk_setup(node, &sun4i_apb0_data);
851 CLK_OF_DECLARE(sun4i_apb0, "allwinner,sun4i-a10-apb0-clk",
852 sun4i_apb0_clk_setup);
854 static void __init sun4i_axi_clk_setup(struct device_node *node)
856 sunxi_divider_clk_setup(node, &sun4i_axi_data);
858 CLK_OF_DECLARE(sun4i_axi, "allwinner,sun4i-a10-axi-clk",
859 sun4i_axi_clk_setup);
861 static void __init sun8i_axi_clk_setup(struct device_node *node)
863 sunxi_divider_clk_setup(node, &sun8i_a23_axi_data);
865 CLK_OF_DECLARE(sun8i_axi, "allwinner,sun8i-a23-axi-clk",
866 sun8i_axi_clk_setup);
871 * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
874 #define SUNXI_GATES_MAX_SIZE 64
877 DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
881 * sunxi_divs_clk_setup() helper data
884 #define SUNXI_DIVS_MAX_QTY 4
885 #define SUNXI_DIVISOR_WIDTH 2
888 const struct factors_data *factors; /* data for the factor clock */
889 int ndivs; /* number of outputs */
891 * List of outputs. Refer to the diagram for sunxi_divs_clk_setup():
892 * self or base factor clock refers to the output from the pll
893 * itself. The remaining refer to fixed or configurable divider
897 u8 self; /* is it the base factor clock? (only one) */
898 u8 fixed; /* is it a fixed divisor? if not... */
899 struct clk_div_table *table; /* is it a table based divisor? */
900 u8 shift; /* otherwise it's a normal divisor with this shift */
901 u8 pow; /* is it power-of-two based? */
902 u8 gate; /* is it independently gateable? */
903 } div[SUNXI_DIVS_MAX_QTY];
906 static struct clk_div_table pll6_sata_tbl[] = {
907 { .val = 0, .div = 6, },
908 { .val = 1, .div = 12, },
909 { .val = 2, .div = 18, },
910 { .val = 3, .div = 24, },
914 static const struct divs_data pll5_divs_data __initconst = {
915 .factors = &sun4i_pll5_data,
918 { .shift = 0, .pow = 0, }, /* M, DDR */
919 { .shift = 16, .pow = 1, }, /* P, other */
920 /* No output for the base factor clock */
924 static const struct divs_data pll6_divs_data __initconst = {
925 .factors = &sun4i_pll5_data,
928 { .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */
929 { .fixed = 2 }, /* P, other */
930 { .self = 1 }, /* base factor clock, 2x */
931 { .fixed = 4 }, /* pll6 / 4, used as ahb input */
935 static const struct divs_data sun6i_a31_pll6_divs_data __initconst = {
936 .factors = &sun6i_a31_pll6_data,
939 { .fixed = 2 }, /* normal output */
940 { .self = 1 }, /* base factor clock, 2x */
945 * sunxi_divs_clk_setup() - Setup function for leaf divisors on clocks
947 * These clocks look something like this
948 * ________________________
949 * | ___divisor 1---|----> to consumer
950 * parent >--| pll___/___divisor 2---|----> to consumer
951 * | \_______________|____> to consumer
952 * |________________________|
955 static struct clk ** __init sunxi_divs_clk_setup(struct device_node *node,
956 const struct divs_data *data)
958 struct clk_onecell_data *clk_data;
960 const char *clk_name;
961 struct clk **clks, *pclk;
962 struct clk_hw *gate_hw, *rate_hw;
963 const struct clk_ops *rate_ops;
964 struct clk_gate *gate = NULL;
965 struct clk_fixed_factor *fix_factor;
966 struct clk_divider *divider;
967 struct factors_data factors = *data->factors;
968 char *derived_name = NULL;
970 int ndivs = SUNXI_DIVS_MAX_QTY, i = 0;
973 /* if number of children known, use it */
977 /* Try to find a name for base factor clock */
978 for (i = 0; i < ndivs; i++) {
979 if (data->div[i].self) {
980 of_property_read_string_index(node, "clock-output-names",
985 /* If we don't have a .self clk use the first output-name up to '_' */
986 if (factors.name == NULL) {
989 of_property_read_string_index(node, "clock-output-names",
991 endp = strchr(clk_name, '_');
993 derived_name = kstrndup(clk_name, endp - clk_name,
995 factors.name = derived_name;
997 factors.name = clk_name;
1001 /* Set up factor clock that we will be dividing */
1002 pclk = sunxi_factors_clk_setup(node, &factors);
1006 parent = __clk_get_name(pclk);
1007 kfree(derived_name);
1009 reg = of_iomap(node, 0);
1011 pr_err("Could not map registers for divs-clk: %pOF\n", node);
1015 clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
1019 clks = kcalloc(ndivs, sizeof(*clks), GFP_KERNEL);
1023 clk_data->clks = clks;
1025 /* It's not a good idea to have automatic reparenting changing
1027 clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT;
1029 for (i = 0; i < ndivs; i++) {
1030 if (of_property_read_string_index(node, "clock-output-names",
1034 /* If this is the base factor clock, only update clks */
1035 if (data->div[i].self) {
1036 clk_data->clks[i] = pclk;
1044 /* If this leaf clock can be gated, create a gate */
1045 if (data->div[i].gate) {
1046 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
1051 gate->bit_idx = data->div[i].gate;
1052 gate->lock = &clk_lock;
1054 gate_hw = &gate->hw;
1057 /* Leaves can be fixed or configurable divisors */
1058 if (data->div[i].fixed) {
1059 fix_factor = kzalloc(sizeof(*fix_factor), GFP_KERNEL);
1063 fix_factor->mult = 1;
1064 fix_factor->div = data->div[i].fixed;
1066 rate_hw = &fix_factor->hw;
1067 rate_ops = &clk_fixed_factor_ops;
1069 divider = kzalloc(sizeof(*divider), GFP_KERNEL);
1073 flags = data->div[i].pow ? CLK_DIVIDER_POWER_OF_TWO : 0;
1076 divider->shift = data->div[i].shift;
1077 divider->width = SUNXI_DIVISOR_WIDTH;
1078 divider->flags = flags;
1079 divider->lock = &clk_lock;
1080 divider->table = data->div[i].table;
1082 rate_hw = ÷r->hw;
1083 rate_ops = &clk_divider_ops;
1086 /* Wrap the (potential) gate and the divisor on a composite
1087 * clock to unify them */
1088 clks[i] = clk_register_composite(NULL, clk_name, &parent, 1,
1091 gate_hw, &clk_gate_ops,
1094 WARN_ON(IS_ERR(clk_data->clks[i]));
1097 /* Adjust to the real max */
1098 clk_data->clk_num = i;
1100 if (of_clk_add_provider(node, of_clk_src_onecell_get, clk_data)) {
1101 pr_err("%s: failed to add clock provider for %s\n",
1102 __func__, clk_name);
1118 static void __init sun4i_pll5_clk_setup(struct device_node *node)
1122 clks = sunxi_divs_clk_setup(node, &pll5_divs_data);
1126 /* Protect PLL5_DDR */
1128 clk_prepare_enable(clks[0]);
1130 CLK_OF_DECLARE(sun4i_pll5, "allwinner,sun4i-a10-pll5-clk",
1131 sun4i_pll5_clk_setup);
1133 static void __init sun4i_pll6_clk_setup(struct device_node *node)
1135 sunxi_divs_clk_setup(node, &pll6_divs_data);
1137 CLK_OF_DECLARE(sun4i_pll6, "allwinner,sun4i-a10-pll6-clk",
1138 sun4i_pll6_clk_setup);
1140 static void __init sun6i_pll6_clk_setup(struct device_node *node)
1142 sunxi_divs_clk_setup(node, &sun6i_a31_pll6_divs_data);
1144 CLK_OF_DECLARE(sun6i_pll6, "allwinner,sun6i-a31-pll6-clk",
1145 sun6i_pll6_clk_setup);
1150 * rate = parent_rate / (m + 1);
1152 static void sun6i_display_factors(struct factors_request *req)
1156 if (req->rate > req->parent_rate)
1157 req->rate = req->parent_rate;
1159 m = DIV_ROUND_UP(req->parent_rate, req->rate);
1161 req->rate = req->parent_rate / m;
1165 static const struct clk_factors_config sun6i_display_config = {
1170 static const struct factors_data sun6i_display_data __initconst = {
1173 .muxmask = BIT(2) | BIT(1) | BIT(0),
1174 .table = &sun6i_display_config,
1175 .getter = sun6i_display_factors,
1178 static void __init sun6i_display_setup(struct device_node *node)
1180 sunxi_factors_clk_setup(node, &sun6i_display_data);
1182 CLK_OF_DECLARE(sun6i_display, "allwinner,sun6i-a31-display-clk",
1183 sun6i_display_setup);