drivers/clk/sunxi/clk-sun9i-mmc.c

   1 /*
   2  * Copyright 2015 Chen-Yu Tsai
   3  *
   4  * Chen-Yu Tsai <wens@csie.org>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/clk.h>
  18 #include <linux/clk-provider.h>
  19 #include <linux/delay.h>
  20 #include <linux/init.h>
  21 #include <linux/of.h>
  22 #include <linux/of_device.h>
  23 #include <linux/reset.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/reset-controller.h>
  26 #include <linux/slab.h>
  27 #include <linux/spinlock.h>
  28
  29 #define SUN9I_MMC_WIDTH         4
  30
  31 #define SUN9I_MMC_GATE_BIT      16
  32 #define SUN9I_MMC_RESET_BIT     18
  33
  34 struct sun9i_mmc_clk_data {
  35         spinlock_t                      lock;
  36         void __iomem                    *membase;
  37         struct clk                      *clk;
  38         struct reset_control            *reset;
  39         struct clk_onecell_data         clk_data;
  40         struct reset_controller_dev     rcdev;
  41 };
  42
  43 static int sun9i_mmc_reset_assert(struct reset_controller_dev *rcdev,
  44                               unsigned long id)
  45 {
  46         struct sun9i_mmc_clk_data *data = container_of(rcdev,
  47                                                        struct sun9i_mmc_clk_data,
  48                                                        rcdev);
  49         unsigned long flags;
  50         void __iomem *reg = data->membase + SUN9I_MMC_WIDTH * id;
  51         u32 val;
  52
  53         clk_prepare_enable(data->clk);
  54         spin_lock_irqsave(&data->lock, flags);
  55
  56         val = readl(reg);
  57         writel(val & ~BIT(SUN9I_MMC_RESET_BIT), reg);
  58
  59         spin_unlock_irqrestore(&data->lock, flags);
  60         clk_disable_unprepare(data->clk);
  61
  62         return 0;
  63 }
  64
  65 static int sun9i_mmc_reset_deassert(struct reset_controller_dev *rcdev,
  66                                 unsigned long id)
  67 {
  68         struct sun9i_mmc_clk_data *data = container_of(rcdev,
  69                                                        struct sun9i_mmc_clk_data,
  70                                                        rcdev);
  71         unsigned long flags;
  72         void __iomem *reg = data->membase + SUN9I_MMC_WIDTH * id;
  73         u32 val;
  74
  75         clk_prepare_enable(data->clk);
  76         spin_lock_irqsave(&data->lock, flags);
  77
  78         val = readl(reg);
  79         writel(val | BIT(SUN9I_MMC_RESET_BIT), reg);
  80
  81         spin_unlock_irqrestore(&data->lock, flags);
  82         clk_disable_unprepare(data->clk);
  83
  84         return 0;
  85 }
  86
  87 static int sun9i_mmc_reset_reset(struct reset_controller_dev *rcdev,
  88                                  unsigned long id)
  89 {
  90         sun9i_mmc_reset_assert(rcdev, id);
  91         udelay(10);
  92         sun9i_mmc_reset_deassert(rcdev, id);
  93
  94         return 0;
  95 }
  96
  97 static const struct reset_control_ops sun9i_mmc_reset_ops = {
  98         .assert         = sun9i_mmc_reset_assert,
  99         .deassert       = sun9i_mmc_reset_deassert,
 100         .reset          = sun9i_mmc_reset_reset,
 101 };
 102
 103 static int sun9i_a80_mmc_config_clk_probe(struct platform_device *pdev)
 104 {
 105         struct device_node *np = pdev->dev.of_node;
 106         struct sun9i_mmc_clk_data *data;
 107         struct clk_onecell_data *clk_data;
 108         const char *clk_name = np->name;
 109         const char *clk_parent;
 110         struct resource *r;
 111         int count, i, ret;
 112
 113         data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
 114         if (!data)
 115                 return -ENOMEM;
 116
 117         spin_lock_init(&data->lock);
 118
 119         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 120         if (!r)
 121                 return -EINVAL;
 122         /* one clock/reset pair per word */
 123         count = DIV_ROUND_UP((resource_size(r)), SUN9I_MMC_WIDTH);
 124         data->membase = devm_ioremap_resource(&pdev->dev, r);
 125         if (IS_ERR(data->membase))
 126                 return PTR_ERR(data->membase);
 127
 128         clk_data = &data->clk_data;
 129         clk_data->clk_num = count;
 130         clk_data->clks = devm_kcalloc(&pdev->dev, count, sizeof(struct clk *),
 131                                       GFP_KERNEL);
 132         if (!clk_data->clks)
 133                 return -ENOMEM;
 134
 135         data->clk = devm_clk_get(&pdev->dev, NULL);
 136         if (IS_ERR(data->clk)) {
 137                 dev_err(&pdev->dev, "Could not get clock\n");
 138                 return PTR_ERR(data->clk);
 139         }
 140
 141         data->reset = devm_reset_control_get(&pdev->dev, NULL);
 142         if (IS_ERR(data->reset)) {
 143                 dev_err(&pdev->dev, "Could not get reset control\n");
 144                 return PTR_ERR(data->reset);
 145         }
 146
 147         ret = reset_control_deassert(data->reset);
 148         if (ret) {
 149                 dev_err(&pdev->dev, "Reset deassert err %d\n", ret);
 150                 return ret;
 151         }
 152
 153         clk_parent = __clk_get_name(data->clk);
 154         for (i = 0; i < count; i++) {
 155                 of_property_read_string_index(np, "clock-output-names",
 156                                               i, &clk_name);
 157
 158                 clk_data->clks[i] = clk_register_gate(&pdev->dev, clk_name,
 159                                                       clk_parent, 0,
 160                                                       data->membase + SUN9I_MMC_WIDTH * i,
 161                                                       SUN9I_MMC_GATE_BIT, 0,
 162                                                       &data->lock);
 163
 164                 if (IS_ERR(clk_data->clks[i])) {
 165                         ret = PTR_ERR(clk_data->clks[i]);
 166                         goto err_clk_register;
 167                 }
 168         }
 169
 170         ret = of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
 171         if (ret)
 172                 goto err_clk_provider;
 173
 174         data->rcdev.owner = THIS_MODULE;
 175         data->rcdev.nr_resets = count;
 176         data->rcdev.ops = &sun9i_mmc_reset_ops;
 177         data->rcdev.of_node = pdev->dev.of_node;
 178
 179         ret = reset_controller_register(&data->rcdev);
 180         if (ret)
 181                 goto err_rc_reg;
 182
 183         platform_set_drvdata(pdev, data);
 184
 185         return 0;
 186
 187 err_rc_reg:
 188         of_clk_del_provider(np);
 189
 190 err_clk_provider:
 191         for (i = 0; i < count; i++)
 192                 clk_unregister(clk_data->clks[i]);
 193
 194 err_clk_register:
 195         reset_control_assert(data->reset);
 196
 197         return ret;
 198 }
 199
 200 static const struct of_device_id sun9i_a80_mmc_config_clk_dt_ids[] = {
 201         { .compatible = "allwinner,sun9i-a80-mmc-config-clk" },
 202         { /* sentinel */ }
 203 };
 204
 205 static struct platform_driver sun9i_a80_mmc_config_clk_driver = {
 206         .driver = {
 207                 .name = "sun9i-a80-mmc-config-clk",
 208                 .suppress_bind_attrs = true,
 209                 .of_match_table = sun9i_a80_mmc_config_clk_dt_ids,
 210         },
 211         .probe = sun9i_a80_mmc_config_clk_probe,
 212 };
 213 builtin_platform_driver(sun9i_a80_mmc_config_clk_driver);