1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2015 Maxime Ripard
5 * Maxime Ripard <maxime.ripard@free-electrons.com>
8 #include <linux/clk-provider.h>
11 #include <linux/of_address.h>
12 #include <linux/slab.h>
13 #include <linux/spinlock.h>
15 #define TCON_CH1_SCLK2_PARENTS 4
17 #define TCON_CH1_SCLK2_GATE_BIT BIT(31)
18 #define TCON_CH1_SCLK2_MUX_MASK 3
19 #define TCON_CH1_SCLK2_MUX_SHIFT 24
20 #define TCON_CH1_SCLK2_DIV_MASK 0xf
21 #define TCON_CH1_SCLK2_DIV_SHIFT 0
23 #define TCON_CH1_SCLK1_GATE_BIT BIT(15)
24 #define TCON_CH1_SCLK1_HALF_BIT BIT(11)
32 #define hw_to_tclk(hw) container_of(hw, struct tcon_ch1_clk, hw)
34 static void tcon_ch1_disable(struct clk_hw *hw)
36 struct tcon_ch1_clk *tclk = hw_to_tclk(hw);
40 spin_lock_irqsave(&tclk->lock, flags);
41 reg = readl(tclk->reg);
42 reg &= ~(TCON_CH1_SCLK2_GATE_BIT | TCON_CH1_SCLK1_GATE_BIT);
43 writel(reg, tclk->reg);
44 spin_unlock_irqrestore(&tclk->lock, flags);
47 static int tcon_ch1_enable(struct clk_hw *hw)
49 struct tcon_ch1_clk *tclk = hw_to_tclk(hw);
53 spin_lock_irqsave(&tclk->lock, flags);
54 reg = readl(tclk->reg);
55 reg |= TCON_CH1_SCLK2_GATE_BIT | TCON_CH1_SCLK1_GATE_BIT;
56 writel(reg, tclk->reg);
57 spin_unlock_irqrestore(&tclk->lock, flags);
62 static int tcon_ch1_is_enabled(struct clk_hw *hw)
64 struct tcon_ch1_clk *tclk = hw_to_tclk(hw);
67 reg = readl(tclk->reg);
68 return reg & (TCON_CH1_SCLK2_GATE_BIT | TCON_CH1_SCLK1_GATE_BIT);
71 static u8 tcon_ch1_get_parent(struct clk_hw *hw)
73 struct tcon_ch1_clk *tclk = hw_to_tclk(hw);
76 reg = readl(tclk->reg) >> TCON_CH1_SCLK2_MUX_SHIFT;
77 reg &= reg >> TCON_CH1_SCLK2_MUX_MASK;
82 static int tcon_ch1_set_parent(struct clk_hw *hw, u8 index)
84 struct tcon_ch1_clk *tclk = hw_to_tclk(hw);
88 spin_lock_irqsave(&tclk->lock, flags);
89 reg = readl(tclk->reg);
90 reg &= ~(TCON_CH1_SCLK2_MUX_MASK << TCON_CH1_SCLK2_MUX_SHIFT);
91 reg |= index << TCON_CH1_SCLK2_MUX_SHIFT;
92 writel(reg, tclk->reg);
93 spin_unlock_irqrestore(&tclk->lock, flags);
98 static unsigned long tcon_ch1_calc_divider(unsigned long rate,
99 unsigned long parent_rate,
103 unsigned long best_rate = 0;
107 for (m = 1; m < 16; m++) {
110 for (d = 1; d < 3; d++) {
111 unsigned long tmp_rate;
113 tmp_rate = parent_rate / m / d;
119 (rate - tmp_rate) < (rate - best_rate)) {
120 best_rate = tmp_rate;
135 static int tcon_ch1_determine_rate(struct clk_hw *hw,
136 struct clk_rate_request *req)
138 long best_rate = -EINVAL;
141 for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
142 unsigned long parent_rate;
143 unsigned long tmp_rate;
144 struct clk_hw *parent;
146 parent = clk_hw_get_parent_by_index(hw, i);
150 parent_rate = clk_hw_get_rate(parent);
152 tmp_rate = tcon_ch1_calc_divider(req->rate, parent_rate,
156 (req->rate - tmp_rate) < (req->rate - best_rate)) {
157 best_rate = tmp_rate;
158 req->best_parent_rate = parent_rate;
159 req->best_parent_hw = parent;
166 req->rate = best_rate;
170 static unsigned long tcon_ch1_recalc_rate(struct clk_hw *hw,
171 unsigned long parent_rate)
173 struct tcon_ch1_clk *tclk = hw_to_tclk(hw);
176 reg = readl(tclk->reg);
178 parent_rate /= (reg & TCON_CH1_SCLK2_DIV_MASK) + 1;
180 if (reg & TCON_CH1_SCLK1_HALF_BIT)
186 static int tcon_ch1_set_rate(struct clk_hw *hw, unsigned long rate,
187 unsigned long parent_rate)
189 struct tcon_ch1_clk *tclk = hw_to_tclk(hw);
195 tcon_ch1_calc_divider(rate, parent_rate, &div_m, &half);
197 spin_lock_irqsave(&tclk->lock, flags);
198 reg = readl(tclk->reg);
199 reg &= ~(TCON_CH1_SCLK2_DIV_MASK | TCON_CH1_SCLK1_HALF_BIT);
200 reg |= (div_m - 1) & TCON_CH1_SCLK2_DIV_MASK;
203 reg |= TCON_CH1_SCLK1_HALF_BIT;
205 writel(reg, tclk->reg);
206 spin_unlock_irqrestore(&tclk->lock, flags);
211 static const struct clk_ops tcon_ch1_ops = {
212 .disable = tcon_ch1_disable,
213 .enable = tcon_ch1_enable,
214 .is_enabled = tcon_ch1_is_enabled,
216 .get_parent = tcon_ch1_get_parent,
217 .set_parent = tcon_ch1_set_parent,
219 .determine_rate = tcon_ch1_determine_rate,
220 .recalc_rate = tcon_ch1_recalc_rate,
221 .set_rate = tcon_ch1_set_rate,
224 static void __init tcon_ch1_setup(struct device_node *node)
226 const char *parents[TCON_CH1_SCLK2_PARENTS];
227 const char *clk_name = node->name;
228 struct clk_init_data init;
229 struct tcon_ch1_clk *tclk;
235 of_property_read_string(node, "clock-output-names", &clk_name);
237 reg = of_io_request_and_map(node, 0, of_node_full_name(node));
239 pr_err("%s: Could not map the clock registers\n", clk_name);
243 ret = of_clk_parent_fill(node, parents, TCON_CH1_SCLK2_PARENTS);
244 if (ret != TCON_CH1_SCLK2_PARENTS) {
245 pr_err("%s Could not retrieve the parents\n", clk_name);
249 tclk = kzalloc(sizeof(*tclk), GFP_KERNEL);
253 init.name = clk_name;
254 init.ops = &tcon_ch1_ops;
255 init.parent_names = parents;
256 init.num_parents = TCON_CH1_SCLK2_PARENTS;
257 init.flags = CLK_SET_RATE_PARENT;
260 tclk->hw.init = &init;
261 spin_lock_init(&tclk->lock);
263 clk = clk_register(NULL, &tclk->hw);
265 pr_err("%s: Couldn't register the clock\n", clk_name);
269 ret = of_clk_add_provider(node, of_clk_src_simple_get, clk);
271 pr_err("%s: Couldn't register our clock provider\n", clk_name);
272 goto err_unregister_clk;
283 of_address_to_resource(node, 0, &res);
284 release_mem_region(res.start, resource_size(&res));
287 CLK_OF_DECLARE(tcon_ch1, "allwinner,sun4i-a10-tcon-ch1-clk",