2 * Copyright 2015 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/clk-provider.h>
19 #include <linux/of_address.h>
20 #include <linux/slab.h>
21 #include <linux/spinlock.h>
23 #define TCON_CH1_SCLK2_PARENTS 4
25 #define TCON_CH1_SCLK2_GATE_BIT BIT(31)
26 #define TCON_CH1_SCLK2_MUX_MASK 3
27 #define TCON_CH1_SCLK2_MUX_SHIFT 24
28 #define TCON_CH1_SCLK2_DIV_MASK 0xf
29 #define TCON_CH1_SCLK2_DIV_SHIFT 0
31 #define TCON_CH1_SCLK1_GATE_BIT BIT(15)
32 #define TCON_CH1_SCLK1_HALF_BIT BIT(11)
40 #define hw_to_tclk(hw) container_of(hw, struct tcon_ch1_clk, hw)
42 static void tcon_ch1_disable(struct clk_hw *hw)
44 struct tcon_ch1_clk *tclk = hw_to_tclk(hw);
48 spin_lock_irqsave(&tclk->lock, flags);
49 reg = readl(tclk->reg);
50 reg &= ~(TCON_CH1_SCLK2_GATE_BIT | TCON_CH1_SCLK1_GATE_BIT);
51 writel(reg, tclk->reg);
52 spin_unlock_irqrestore(&tclk->lock, flags);
55 static int tcon_ch1_enable(struct clk_hw *hw)
57 struct tcon_ch1_clk *tclk = hw_to_tclk(hw);
61 spin_lock_irqsave(&tclk->lock, flags);
62 reg = readl(tclk->reg);
63 reg |= TCON_CH1_SCLK2_GATE_BIT | TCON_CH1_SCLK1_GATE_BIT;
64 writel(reg, tclk->reg);
65 spin_unlock_irqrestore(&tclk->lock, flags);
70 static int tcon_ch1_is_enabled(struct clk_hw *hw)
72 struct tcon_ch1_clk *tclk = hw_to_tclk(hw);
75 reg = readl(tclk->reg);
76 return reg & (TCON_CH1_SCLK2_GATE_BIT | TCON_CH1_SCLK1_GATE_BIT);
79 static u8 tcon_ch1_get_parent(struct clk_hw *hw)
81 struct tcon_ch1_clk *tclk = hw_to_tclk(hw);
84 reg = readl(tclk->reg) >> TCON_CH1_SCLK2_MUX_SHIFT;
85 reg &= reg >> TCON_CH1_SCLK2_MUX_MASK;
90 static int tcon_ch1_set_parent(struct clk_hw *hw, u8 index)
92 struct tcon_ch1_clk *tclk = hw_to_tclk(hw);
96 spin_lock_irqsave(&tclk->lock, flags);
97 reg = readl(tclk->reg);
98 reg &= ~(TCON_CH1_SCLK2_MUX_MASK << TCON_CH1_SCLK2_MUX_SHIFT);
99 reg |= index << TCON_CH1_SCLK2_MUX_SHIFT;
100 writel(reg, tclk->reg);
101 spin_unlock_irqrestore(&tclk->lock, flags);
106 static unsigned long tcon_ch1_calc_divider(unsigned long rate,
107 unsigned long parent_rate,
111 unsigned long best_rate = 0;
115 for (m = 1; m < 16; m++) {
118 for (d = 1; d < 3; d++) {
119 unsigned long tmp_rate;
121 tmp_rate = parent_rate / m / d;
127 (rate - tmp_rate) < (rate - best_rate)) {
128 best_rate = tmp_rate;
143 static int tcon_ch1_determine_rate(struct clk_hw *hw,
144 struct clk_rate_request *req)
146 long best_rate = -EINVAL;
149 for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
150 unsigned long parent_rate;
151 unsigned long tmp_rate;
152 struct clk_hw *parent;
154 parent = clk_hw_get_parent_by_index(hw, i);
158 parent_rate = clk_hw_get_rate(parent);
160 tmp_rate = tcon_ch1_calc_divider(req->rate, parent_rate,
164 (req->rate - tmp_rate) < (req->rate - best_rate)) {
165 best_rate = tmp_rate;
166 req->best_parent_rate = parent_rate;
167 req->best_parent_hw = parent;
174 req->rate = best_rate;
178 static unsigned long tcon_ch1_recalc_rate(struct clk_hw *hw,
179 unsigned long parent_rate)
181 struct tcon_ch1_clk *tclk = hw_to_tclk(hw);
184 reg = readl(tclk->reg);
186 parent_rate /= (reg & TCON_CH1_SCLK2_DIV_MASK) + 1;
188 if (reg & TCON_CH1_SCLK1_HALF_BIT)
194 static int tcon_ch1_set_rate(struct clk_hw *hw, unsigned long rate,
195 unsigned long parent_rate)
197 struct tcon_ch1_clk *tclk = hw_to_tclk(hw);
203 tcon_ch1_calc_divider(rate, parent_rate, &div_m, &half);
205 spin_lock_irqsave(&tclk->lock, flags);
206 reg = readl(tclk->reg);
207 reg &= ~(TCON_CH1_SCLK2_DIV_MASK | TCON_CH1_SCLK1_HALF_BIT);
208 reg |= (div_m - 1) & TCON_CH1_SCLK2_DIV_MASK;
211 reg |= TCON_CH1_SCLK1_HALF_BIT;
213 writel(reg, tclk->reg);
214 spin_unlock_irqrestore(&tclk->lock, flags);
219 static const struct clk_ops tcon_ch1_ops = {
220 .disable = tcon_ch1_disable,
221 .enable = tcon_ch1_enable,
222 .is_enabled = tcon_ch1_is_enabled,
224 .get_parent = tcon_ch1_get_parent,
225 .set_parent = tcon_ch1_set_parent,
227 .determine_rate = tcon_ch1_determine_rate,
228 .recalc_rate = tcon_ch1_recalc_rate,
229 .set_rate = tcon_ch1_set_rate,
232 static void __init tcon_ch1_setup(struct device_node *node)
234 const char *parents[TCON_CH1_SCLK2_PARENTS];
235 const char *clk_name = node->name;
236 struct clk_init_data init;
237 struct tcon_ch1_clk *tclk;
243 of_property_read_string(node, "clock-output-names", &clk_name);
245 reg = of_io_request_and_map(node, 0, of_node_full_name(node));
247 pr_err("%s: Could not map the clock registers\n", clk_name);
251 ret = of_clk_parent_fill(node, parents, TCON_CH1_SCLK2_PARENTS);
252 if (ret != TCON_CH1_SCLK2_PARENTS) {
253 pr_err("%s Could not retrieve the parents\n", clk_name);
257 tclk = kzalloc(sizeof(*tclk), GFP_KERNEL);
261 init.name = clk_name;
262 init.ops = &tcon_ch1_ops;
263 init.parent_names = parents;
264 init.num_parents = TCON_CH1_SCLK2_PARENTS;
265 init.flags = CLK_SET_RATE_PARENT;
268 tclk->hw.init = &init;
269 spin_lock_init(&tclk->lock);
271 clk = clk_register(NULL, &tclk->hw);
273 pr_err("%s: Couldn't register the clock\n", clk_name);
277 ret = of_clk_add_provider(node, of_clk_src_simple_get, clk);
279 pr_err("%s: Couldn't register our clock provider\n", clk_name);
280 goto err_unregister_clk;
291 of_address_to_resource(node, 0, &res);
292 release_mem_region(res.start, resource_size(&res));
295 CLK_OF_DECLARE(tcon_ch1, "allwinner,sun4i-a10-tcon-ch1-clk",