1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2013 Emilio López
4 * Emilio López <emilio@elopez.com.ar>
6 * Copyright 2015 Maxime Ripard
7 * Maxime Ripard <maxime.ripard@free-electrons.com>
10 #include <linux/clk-provider.h>
13 #include <linux/of_address.h>
14 #include <linux/slab.h>
16 #include <dt-bindings/clock/sun4i-a10-pll2.h>
18 #define SUN4I_PLL2_ENABLE 31
20 #define SUN4I_PLL2_PRE_DIV_SHIFT 0
21 #define SUN4I_PLL2_PRE_DIV_WIDTH 5
22 #define SUN4I_PLL2_PRE_DIV_MASK GENMASK(SUN4I_PLL2_PRE_DIV_WIDTH - 1, 0)
24 #define SUN4I_PLL2_N_SHIFT 8
25 #define SUN4I_PLL2_N_WIDTH 7
26 #define SUN4I_PLL2_N_MASK GENMASK(SUN4I_PLL2_N_WIDTH - 1, 0)
28 #define SUN4I_PLL2_POST_DIV_SHIFT 26
29 #define SUN4I_PLL2_POST_DIV_WIDTH 4
30 #define SUN4I_PLL2_POST_DIV_MASK GENMASK(SUN4I_PLL2_POST_DIV_WIDTH - 1, 0)
32 #define SUN4I_PLL2_POST_DIV_VALUE 4
34 #define SUN4I_PLL2_OUTPUTS 4
36 static DEFINE_SPINLOCK(sun4i_a10_pll2_lock);
38 static void __init sun4i_pll2_setup(struct device_node *node,
41 const char *clk_name = node->name, *parent;
42 struct clk **clks, *base_clk, *prediv_clk;
43 struct clk_onecell_data *clk_data;
44 struct clk_multiplier *mult;
45 struct clk_gate *gate;
49 reg = of_io_request_and_map(node, 0, of_node_full_name(node));
53 clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
57 clks = kcalloc(SUN4I_PLL2_OUTPUTS, sizeof(struct clk *), GFP_KERNEL);
61 parent = of_clk_get_parent_name(node, 0);
62 prediv_clk = clk_register_divider(NULL, "pll2-prediv",
64 SUN4I_PLL2_PRE_DIV_SHIFT,
65 SUN4I_PLL2_PRE_DIV_WIDTH,
66 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
67 &sun4i_a10_pll2_lock);
68 if (IS_ERR(prediv_clk)) {
69 pr_err("Couldn't register the prediv clock\n");
73 /* Setup the gate part of the PLL2 */
74 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
76 goto err_unregister_prediv;
79 gate->bit_idx = SUN4I_PLL2_ENABLE;
80 gate->lock = &sun4i_a10_pll2_lock;
82 /* Setup the multiplier part of the PLL2 */
83 mult = kzalloc(sizeof(struct clk_multiplier), GFP_KERNEL);
88 mult->shift = SUN4I_PLL2_N_SHIFT;
90 mult->flags = CLK_MULTIPLIER_ZERO_BYPASS |
91 CLK_MULTIPLIER_ROUND_CLOSEST;
92 mult->lock = &sun4i_a10_pll2_lock;
94 parent = __clk_get_name(prediv_clk);
95 base_clk = clk_register_composite(NULL, "pll2-base",
98 &mult->hw, &clk_multiplier_ops,
99 &gate->hw, &clk_gate_ops,
100 CLK_SET_RATE_PARENT);
101 if (IS_ERR(base_clk)) {
102 pr_err("Couldn't register the base multiplier clock\n");
103 goto err_free_multiplier;
106 parent = __clk_get_name(base_clk);
111 * This is supposed to have a post divider, but we won't need
112 * to use it, we just need to initialise it to 4, and use a
116 val &= ~(SUN4I_PLL2_POST_DIV_MASK << SUN4I_PLL2_POST_DIV_SHIFT);
117 val |= (SUN4I_PLL2_POST_DIV_VALUE - post_div_offset) << SUN4I_PLL2_POST_DIV_SHIFT;
120 of_property_read_string_index(node, "clock-output-names",
121 SUN4I_A10_PLL2_1X, &clk_name);
122 clks[SUN4I_A10_PLL2_1X] = clk_register_fixed_factor(NULL, clk_name,
126 SUN4I_PLL2_POST_DIV_VALUE);
127 WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_1X]));
132 * This clock doesn't use the post divider, and really is just
133 * a fixed divider from the PLL2 base clock.
135 of_property_read_string_index(node, "clock-output-names",
136 SUN4I_A10_PLL2_2X, &clk_name);
137 clks[SUN4I_A10_PLL2_2X] = clk_register_fixed_factor(NULL, clk_name,
141 WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_2X]));
144 of_property_read_string_index(node, "clock-output-names",
145 SUN4I_A10_PLL2_4X, &clk_name);
146 clks[SUN4I_A10_PLL2_4X] = clk_register_fixed_factor(NULL, clk_name,
150 WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_4X]));
153 of_property_read_string_index(node, "clock-output-names",
154 SUN4I_A10_PLL2_8X, &clk_name);
155 clks[SUN4I_A10_PLL2_8X] = clk_register_fixed_factor(NULL, clk_name,
159 WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_8X]));
161 clk_data->clks = clks;
162 clk_data->clk_num = SUN4I_PLL2_OUTPUTS;
163 of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
171 err_unregister_prediv:
172 clk_unregister_divider(prediv_clk);
181 static void __init sun4i_a10_pll2_setup(struct device_node *node)
183 sun4i_pll2_setup(node, 0);
186 CLK_OF_DECLARE(sun4i_a10_pll2, "allwinner,sun4i-a10-pll2-clk",
187 sun4i_a10_pll2_setup);
189 static void __init sun5i_a13_pll2_setup(struct device_node *node)
191 sun4i_pll2_setup(node, 1);
194 CLK_OF_DECLARE(sun5i_a13_pll2, "allwinner,sun5i-a13-pll2-clk",
195 sun5i_a13_pll2_setup);