drivers/clk/stm32/clk-stm32mp13.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
   4  * Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.
   5  */
   6
   7 #include <linux/clk.h>
   8 #include <linux/module.h>
   9 #include <linux/of_address.h>
  10 #include <linux/platform_device.h>
  11 #include <dt-bindings/clock/stm32mp13-clks.h>
  12 #include "clk-stm32-core.h"
  13 #include "stm32mp13_rcc.h"
  14
  15 #define RCC_CLR_OFFSET          0x4
  16
  17 /* STM32 Gates definition */
  18 enum enum_gate_cfg {
  19         GATE_MCO1,
  20         GATE_MCO2,
  21         GATE_DBGCK,
  22         GATE_TRACECK,
  23         GATE_DDRC1,
  24         GATE_DDRC1LP,
  25         GATE_DDRPHYC,
  26         GATE_DDRPHYCLP,
  27         GATE_DDRCAPB,
  28         GATE_DDRCAPBLP,
  29         GATE_AXIDCG,
  30         GATE_DDRPHYCAPB,
  31         GATE_DDRPHYCAPBLP,
  32         GATE_TIM2,
  33         GATE_TIM3,
  34         GATE_TIM4,
  35         GATE_TIM5,
  36         GATE_TIM6,
  37         GATE_TIM7,
  38         GATE_LPTIM1,
  39         GATE_SPI2,
  40         GATE_SPI3,
  41         GATE_USART3,
  42         GATE_UART4,
  43         GATE_UART5,
  44         GATE_UART7,
  45         GATE_UART8,
  46         GATE_I2C1,
  47         GATE_I2C2,
  48         GATE_SPDIF,
  49         GATE_TIM1,
  50         GATE_TIM8,
  51         GATE_SPI1,
  52         GATE_USART6,
  53         GATE_SAI1,
  54         GATE_SAI2,
  55         GATE_DFSDM,
  56         GATE_ADFSDM,
  57         GATE_FDCAN,
  58         GATE_LPTIM2,
  59         GATE_LPTIM3,
  60         GATE_LPTIM4,
  61         GATE_LPTIM5,
  62         GATE_VREF,
  63         GATE_DTS,
  64         GATE_PMBCTRL,
  65         GATE_HDP,
  66         GATE_SYSCFG,
  67         GATE_DCMIPP,
  68         GATE_DDRPERFM,
  69         GATE_IWDG2APB,
  70         GATE_USBPHY,
  71         GATE_STGENRO,
  72         GATE_LTDC,
  73         GATE_RTCAPB,
  74         GATE_TZC,
  75         GATE_ETZPC,
  76         GATE_IWDG1APB,
  77         GATE_BSEC,
  78         GATE_STGENC,
  79         GATE_USART1,
  80         GATE_USART2,
  81         GATE_SPI4,
  82         GATE_SPI5,
  83         GATE_I2C3,
  84         GATE_I2C4,
  85         GATE_I2C5,
  86         GATE_TIM12,
  87         GATE_TIM13,
  88         GATE_TIM14,
  89         GATE_TIM15,
  90         GATE_TIM16,
  91         GATE_TIM17,
  92         GATE_DMA1,
  93         GATE_DMA2,
  94         GATE_DMAMUX1,
  95         GATE_DMA3,
  96         GATE_DMAMUX2,
  97         GATE_ADC1,
  98         GATE_ADC2,
  99         GATE_USBO,
 100         GATE_TSC,
 101         GATE_GPIOA,
 102         GATE_GPIOB,
 103         GATE_GPIOC,
 104         GATE_GPIOD,
 105         GATE_GPIOE,
 106         GATE_GPIOF,
 107         GATE_GPIOG,
 108         GATE_GPIOH,
 109         GATE_GPIOI,
 110         GATE_PKA,
 111         GATE_SAES,
 112         GATE_CRYP1,
 113         GATE_HASH1,
 114         GATE_RNG1,
 115         GATE_BKPSRAM,
 116         GATE_AXIMC,
 117         GATE_MCE,
 118         GATE_ETH1CK,
 119         GATE_ETH1TX,
 120         GATE_ETH1RX,
 121         GATE_ETH1MAC,
 122         GATE_FMC,
 123         GATE_QSPI,
 124         GATE_SDMMC1,
 125         GATE_SDMMC2,
 126         GATE_CRC1,
 127         GATE_USBH,
 128         GATE_ETH2CK,
 129         GATE_ETH2TX,
 130         GATE_ETH2RX,
 131         GATE_ETH2MAC,
 132         GATE_ETH1STP,
 133         GATE_ETH2STP,
 134         GATE_MDMA,
 135         GATE_NB
 136 };
 137
 138 #define _CFG_GATE(_id, _offset, _bit_idx, _offset_clr)\
 139         [(_id)] = {\
 140                 .offset         = (_offset),\
 141                 .bit_idx        = (_bit_idx),\
 142                 .set_clr        = (_offset_clr),\
 143         }
 144
 145 #define CFG_GATE(_id, _offset, _bit_idx)\
 146         _CFG_GATE(_id, _offset, _bit_idx, 0)
 147
 148 #define CFG_GATE_SETCLR(_id, _offset, _bit_idx)\
 149         _CFG_GATE(_id, _offset, _bit_idx, RCC_CLR_OFFSET)
 150
 151 static struct stm32_gate_cfg stm32mp13_gates[] = {
 152         CFG_GATE(GATE_MCO1,             RCC_MCO1CFGR,           12),
 153         CFG_GATE(GATE_MCO2,             RCC_MCO2CFGR,           12),
 154         CFG_GATE(GATE_DBGCK,            RCC_DBGCFGR,            8),
 155         CFG_GATE(GATE_TRACECK,          RCC_DBGCFGR,            9),
 156         CFG_GATE(GATE_DDRC1,            RCC_DDRITFCR,           0),
 157         CFG_GATE(GATE_DDRC1LP,          RCC_DDRITFCR,           1),
 158         CFG_GATE(GATE_DDRPHYC,          RCC_DDRITFCR,           4),
 159         CFG_GATE(GATE_DDRPHYCLP,        RCC_DDRITFCR,           5),
 160         CFG_GATE(GATE_DDRCAPB,          RCC_DDRITFCR,           6),
 161         CFG_GATE(GATE_DDRCAPBLP,        RCC_DDRITFCR,           7),
 162         CFG_GATE(GATE_AXIDCG,           RCC_DDRITFCR,           8),
 163         CFG_GATE(GATE_DDRPHYCAPB,       RCC_DDRITFCR,           9),
 164         CFG_GATE(GATE_DDRPHYCAPBLP,     RCC_DDRITFCR,           10),
 165         CFG_GATE_SETCLR(GATE_TIM2,      RCC_MP_APB1ENSETR,      0),
 166         CFG_GATE_SETCLR(GATE_TIM3,      RCC_MP_APB1ENSETR,      1),
 167         CFG_GATE_SETCLR(GATE_TIM4,      RCC_MP_APB1ENSETR,      2),
 168         CFG_GATE_SETCLR(GATE_TIM5,      RCC_MP_APB1ENSETR,      3),
 169         CFG_GATE_SETCLR(GATE_TIM6,      RCC_MP_APB1ENSETR,      4),
 170         CFG_GATE_SETCLR(GATE_TIM7,      RCC_MP_APB1ENSETR,      5),
 171         CFG_GATE_SETCLR(GATE_LPTIM1,    RCC_MP_APB1ENSETR,      9),
 172         CFG_GATE_SETCLR(GATE_SPI2,      RCC_MP_APB1ENSETR,      11),
 173         CFG_GATE_SETCLR(GATE_SPI3,      RCC_MP_APB1ENSETR,      12),
 174         CFG_GATE_SETCLR(GATE_USART3,    RCC_MP_APB1ENSETR,      15),
 175         CFG_GATE_SETCLR(GATE_UART4,     RCC_MP_APB1ENSETR,      16),
 176         CFG_GATE_SETCLR(GATE_UART5,     RCC_MP_APB1ENSETR,      17),
 177         CFG_GATE_SETCLR(GATE_UART7,     RCC_MP_APB1ENSETR,      18),
 178         CFG_GATE_SETCLR(GATE_UART8,     RCC_MP_APB1ENSETR,      19),
 179         CFG_GATE_SETCLR(GATE_I2C1,      RCC_MP_APB1ENSETR,      21),
 180         CFG_GATE_SETCLR(GATE_I2C2,      RCC_MP_APB1ENSETR,      22),
 181         CFG_GATE_SETCLR(GATE_SPDIF,     RCC_MP_APB1ENSETR,      26),
 182         CFG_GATE_SETCLR(GATE_TIM1,      RCC_MP_APB2ENSETR,      0),
 183         CFG_GATE_SETCLR(GATE_TIM8,      RCC_MP_APB2ENSETR,      1),
 184         CFG_GATE_SETCLR(GATE_SPI1,      RCC_MP_APB2ENSETR,      8),
 185         CFG_GATE_SETCLR(GATE_USART6,    RCC_MP_APB2ENSETR,      13),
 186         CFG_GATE_SETCLR(GATE_SAI1,      RCC_MP_APB2ENSETR,      16),
 187         CFG_GATE_SETCLR(GATE_SAI2,      RCC_MP_APB2ENSETR,      17),
 188         CFG_GATE_SETCLR(GATE_DFSDM,     RCC_MP_APB2ENSETR,      20),
 189         CFG_GATE_SETCLR(GATE_ADFSDM,    RCC_MP_APB2ENSETR,      21),
 190         CFG_GATE_SETCLR(GATE_FDCAN,     RCC_MP_APB2ENSETR,      24),
 191         CFG_GATE_SETCLR(GATE_LPTIM2,    RCC_MP_APB3ENSETR,      0),
 192         CFG_GATE_SETCLR(GATE_LPTIM3,    RCC_MP_APB3ENSETR,      1),
 193         CFG_GATE_SETCLR(GATE_LPTIM4,    RCC_MP_APB3ENSETR,      2),
 194         CFG_GATE_SETCLR(GATE_LPTIM5,    RCC_MP_APB3ENSETR,      3),
 195         CFG_GATE_SETCLR(GATE_VREF,      RCC_MP_APB3ENSETR,      13),
 196         CFG_GATE_SETCLR(GATE_DTS,       RCC_MP_APB3ENSETR,      16),
 197         CFG_GATE_SETCLR(GATE_PMBCTRL,   RCC_MP_APB3ENSETR,      17),
 198         CFG_GATE_SETCLR(GATE_HDP,       RCC_MP_APB3ENSETR,      20),
 199         CFG_GATE_SETCLR(GATE_SYSCFG,    RCC_MP_NS_APB3ENSETR,   0),
 200         CFG_GATE_SETCLR(GATE_DCMIPP,    RCC_MP_APB4ENSETR,      1),
 201         CFG_GATE_SETCLR(GATE_DDRPERFM,  RCC_MP_APB4ENSETR,      8),
 202         CFG_GATE_SETCLR(GATE_IWDG2APB,  RCC_MP_APB4ENSETR,      15),
 203         CFG_GATE_SETCLR(GATE_USBPHY,    RCC_MP_APB4ENSETR,      16),
 204         CFG_GATE_SETCLR(GATE_STGENRO,   RCC_MP_APB4ENSETR,      20),
 205         CFG_GATE_SETCLR(GATE_LTDC,      RCC_MP_NS_APB4ENSETR,   0),
 206         CFG_GATE_SETCLR(GATE_RTCAPB,    RCC_MP_APB5ENSETR,      8),
 207         CFG_GATE_SETCLR(GATE_TZC,       RCC_MP_APB5ENSETR,      11),
 208         CFG_GATE_SETCLR(GATE_ETZPC,     RCC_MP_APB5ENSETR,      13),
 209         CFG_GATE_SETCLR(GATE_IWDG1APB,  RCC_MP_APB5ENSETR,      15),
 210         CFG_GATE_SETCLR(GATE_BSEC,      RCC_MP_APB5ENSETR,      16),
 211         CFG_GATE_SETCLR(GATE_STGENC,    RCC_MP_APB5ENSETR,      20),
 212         CFG_GATE_SETCLR(GATE_USART1,    RCC_MP_APB6ENSETR,      0),
 213         CFG_GATE_SETCLR(GATE_USART2,    RCC_MP_APB6ENSETR,      1),
 214         CFG_GATE_SETCLR(GATE_SPI4,      RCC_MP_APB6ENSETR,      2),
 215         CFG_GATE_SETCLR(GATE_SPI5,      RCC_MP_APB6ENSETR,      3),
 216         CFG_GATE_SETCLR(GATE_I2C3,      RCC_MP_APB6ENSETR,      4),
 217         CFG_GATE_SETCLR(GATE_I2C4,      RCC_MP_APB6ENSETR,      5),
 218         CFG_GATE_SETCLR(GATE_I2C5,      RCC_MP_APB6ENSETR,      6),
 219         CFG_GATE_SETCLR(GATE_TIM12,     RCC_MP_APB6ENSETR,      7),
 220         CFG_GATE_SETCLR(GATE_TIM13,     RCC_MP_APB6ENSETR,      8),
 221         CFG_GATE_SETCLR(GATE_TIM14,     RCC_MP_APB6ENSETR,      9),
 222         CFG_GATE_SETCLR(GATE_TIM15,     RCC_MP_APB6ENSETR,      10),
 223         CFG_GATE_SETCLR(GATE_TIM16,     RCC_MP_APB6ENSETR,      11),
 224         CFG_GATE_SETCLR(GATE_TIM17,     RCC_MP_APB6ENSETR,      12),
 225         CFG_GATE_SETCLR(GATE_DMA1,      RCC_MP_AHB2ENSETR,      0),
 226         CFG_GATE_SETCLR(GATE_DMA2,      RCC_MP_AHB2ENSETR,      1),
 227         CFG_GATE_SETCLR(GATE_DMAMUX1,   RCC_MP_AHB2ENSETR,      2),
 228         CFG_GATE_SETCLR(GATE_DMA3,      RCC_MP_AHB2ENSETR,      3),
 229         CFG_GATE_SETCLR(GATE_DMAMUX2,   RCC_MP_AHB2ENSETR,      4),
 230         CFG_GATE_SETCLR(GATE_ADC1,      RCC_MP_AHB2ENSETR,      5),
 231         CFG_GATE_SETCLR(GATE_ADC2,      RCC_MP_AHB2ENSETR,      6),
 232         CFG_GATE_SETCLR(GATE_USBO,      RCC_MP_AHB2ENSETR,      8),
 233         CFG_GATE_SETCLR(GATE_TSC,       RCC_MP_AHB4ENSETR,      15),
 234         CFG_GATE_SETCLR(GATE_GPIOA,     RCC_MP_NS_AHB4ENSETR,   0),
 235         CFG_GATE_SETCLR(GATE_GPIOB,     RCC_MP_NS_AHB4ENSETR,   1),
 236         CFG_GATE_SETCLR(GATE_GPIOC,     RCC_MP_NS_AHB4ENSETR,   2),
 237         CFG_GATE_SETCLR(GATE_GPIOD,     RCC_MP_NS_AHB4ENSETR,   3),
 238         CFG_GATE_SETCLR(GATE_GPIOE,     RCC_MP_NS_AHB4ENSETR,   4),
 239         CFG_GATE_SETCLR(GATE_GPIOF,     RCC_MP_NS_AHB4ENSETR,   5),
 240         CFG_GATE_SETCLR(GATE_GPIOG,     RCC_MP_NS_AHB4ENSETR,   6),
 241         CFG_GATE_SETCLR(GATE_GPIOH,     RCC_MP_NS_AHB4ENSETR,   7),
 242         CFG_GATE_SETCLR(GATE_GPIOI,     RCC_MP_NS_AHB4ENSETR,   8),
 243         CFG_GATE_SETCLR(GATE_PKA,       RCC_MP_AHB5ENSETR,      2),
 244         CFG_GATE_SETCLR(GATE_SAES,      RCC_MP_AHB5ENSETR,      3),
 245         CFG_GATE_SETCLR(GATE_CRYP1,     RCC_MP_AHB5ENSETR,      4),
 246         CFG_GATE_SETCLR(GATE_HASH1,     RCC_MP_AHB5ENSETR,      5),
 247         CFG_GATE_SETCLR(GATE_RNG1,      RCC_MP_AHB5ENSETR,      6),
 248         CFG_GATE_SETCLR(GATE_BKPSRAM,   RCC_MP_AHB5ENSETR,      8),
 249         CFG_GATE_SETCLR(GATE_AXIMC,     RCC_MP_AHB5ENSETR,      16),
 250         CFG_GATE_SETCLR(GATE_MCE,       RCC_MP_AHB6ENSETR,      1),
 251         CFG_GATE_SETCLR(GATE_ETH1CK,    RCC_MP_AHB6ENSETR,      7),
 252         CFG_GATE_SETCLR(GATE_ETH1TX,    RCC_MP_AHB6ENSETR,      8),
 253         CFG_GATE_SETCLR(GATE_ETH1RX,    RCC_MP_AHB6ENSETR,      9),
 254         CFG_GATE_SETCLR(GATE_ETH1MAC,   RCC_MP_AHB6ENSETR,      10),
 255         CFG_GATE_SETCLR(GATE_FMC,       RCC_MP_AHB6ENSETR,      12),
 256         CFG_GATE_SETCLR(GATE_QSPI,      RCC_MP_AHB6ENSETR,      14),
 257         CFG_GATE_SETCLR(GATE_SDMMC1,    RCC_MP_AHB6ENSETR,      16),
 258         CFG_GATE_SETCLR(GATE_SDMMC2,    RCC_MP_AHB6ENSETR,      17),
 259         CFG_GATE_SETCLR(GATE_CRC1,      RCC_MP_AHB6ENSETR,      20),
 260         CFG_GATE_SETCLR(GATE_USBH,      RCC_MP_AHB6ENSETR,      24),
 261         CFG_GATE_SETCLR(GATE_ETH2CK,    RCC_MP_AHB6ENSETR,      27),
 262         CFG_GATE_SETCLR(GATE_ETH2TX,    RCC_MP_AHB6ENSETR,      28),
 263         CFG_GATE_SETCLR(GATE_ETH2RX,    RCC_MP_AHB6ENSETR,      29),
 264         CFG_GATE_SETCLR(GATE_ETH2MAC,   RCC_MP_AHB6ENSETR,      30),
 265         CFG_GATE_SETCLR(GATE_ETH1STP,   RCC_MP_AHB6LPENSETR,    11),
 266         CFG_GATE_SETCLR(GATE_ETH2STP,   RCC_MP_AHB6LPENSETR,    31),
 267         CFG_GATE_SETCLR(GATE_MDMA,      RCC_MP_NS_AHB6ENSETR,   0),
 268 };
 269
 270 /* STM32 Divivers definition */
 271 enum enum_div_cfg {
 272         DIV_RTC,
 273         DIV_HSI,
 274         DIV_MCO1,
 275         DIV_MCO2,
 276         DIV_TRACE,
 277         DIV_ETH1PTP,
 278         DIV_ETH2PTP,
 279         DIV_NB
 280 };
 281
 282 static const struct clk_div_table ck_trace_div_table[] = {
 283         { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 },
 284         { 4, 16 }, { 5, 16 }, { 6, 16 }, { 7, 16 },
 285         { 0 },
 286 };
 287
 288 #define CFG_DIV(_id, _offset, _shift, _width, _flags, _table, _ready)\
 289         [(_id)] = {\
 290                 .offset = (_offset),\
 291                 .shift  = (_shift),\
 292                 .width  = (_width),\
 293                 .flags  = (_flags),\
 294                 .table  = (_table),\
 295                 .ready  = (_ready),\
 296         }
 297
 298 static const struct stm32_div_cfg stm32mp13_dividers[DIV_NB] = {
 299         CFG_DIV(DIV_RTC, RCC_RTCDIVR, 0, 6, 0, NULL, DIV_NO_RDY),
 300         CFG_DIV(DIV_MCO1, RCC_MCO1CFGR, 4, 4, 0, NULL, DIV_NO_RDY),
 301         CFG_DIV(DIV_MCO2, RCC_MCO2CFGR, 4, 4, 0, NULL, DIV_NO_RDY),
 302         CFG_DIV(DIV_TRACE, RCC_DBGCFGR, 0, 3, 0, ck_trace_div_table, DIV_NO_RDY),
 303         CFG_DIV(DIV_ETH1PTP, RCC_ETH12CKSELR, 4, 4, 0, NULL, DIV_NO_RDY),
 304         CFG_DIV(DIV_ETH2PTP, RCC_ETH12CKSELR, 12, 4, 0, NULL, DIV_NO_RDY),
 305 };
 306
 307 /* STM32 Muxes definition */
 308 enum enum_mux_cfg {
 309         MUX_ADC1,
 310         MUX_ADC2,
 311         MUX_DCMIPP,
 312         MUX_ETH1,
 313         MUX_ETH2,
 314         MUX_FDCAN,
 315         MUX_FMC,
 316         MUX_I2C12,
 317         MUX_I2C3,
 318         MUX_I2C4,
 319         MUX_I2C5,
 320         MUX_LPTIM1,
 321         MUX_LPTIM2,
 322         MUX_LPTIM3,
 323         MUX_LPTIM45,
 324         MUX_MCO1,
 325         MUX_MCO2,
 326         MUX_QSPI,
 327         MUX_RNG1,
 328         MUX_SAES,
 329         MUX_SAI1,
 330         MUX_SAI2,
 331         MUX_SDMMC1,
 332         MUX_SDMMC2,
 333         MUX_SPDIF,
 334         MUX_SPI1,
 335         MUX_SPI23,
 336         MUX_SPI4,
 337         MUX_SPI5,
 338         MUX_STGEN,
 339         MUX_UART1,
 340         MUX_UART2,
 341         MUX_UART4,
 342         MUX_UART6,
 343         MUX_UART35,
 344         MUX_UART78,
 345         MUX_USBO,
 346         MUX_USBPHY,
 347         MUX_NB
 348 };
 349
 350 #define _CFG_MUX(_id, _offset, _shift, _witdh, _ready, _flags)\
 351         [_id] = {\
 352                 .offset         = (_offset),\
 353                 .shift          = (_shift),\
 354                 .width          = (_witdh),\
 355                 .ready          = (_ready),\
 356                 .flags          = (_flags),\
 357         }
 358
 359 #define CFG_MUX(_id, _offset, _shift, _witdh)\
 360         _CFG_MUX(_id, _offset, _shift, _witdh, MUX_NO_RDY, 0)
 361
 362 #define CFG_MUX_SAFE(_id, _offset, _shift, _witdh)\
 363         _CFG_MUX(_id, _offset, _shift, _witdh, MUX_NO_RDY, MUX_SAFE)
 364
 365 static const struct stm32_mux_cfg stm32mp13_muxes[] = {
 366         CFG_MUX(MUX_I2C12,      RCC_I2C12CKSELR,        0, 3),
 367         CFG_MUX(MUX_LPTIM45,    RCC_LPTIM45CKSELR,      0, 3),
 368         CFG_MUX(MUX_SPI23,      RCC_SPI2S23CKSELR,      0, 3),
 369         CFG_MUX(MUX_UART35,     RCC_UART35CKSELR,       0, 3),
 370         CFG_MUX(MUX_UART78,     RCC_UART78CKSELR,       0, 3),
 371         CFG_MUX(MUX_ADC1,       RCC_ADC12CKSELR,        0, 2),
 372         CFG_MUX(MUX_ADC2,       RCC_ADC12CKSELR,        2, 2),
 373         CFG_MUX(MUX_DCMIPP,     RCC_DCMIPPCKSELR,       0, 2),
 374         CFG_MUX(MUX_ETH1,       RCC_ETH12CKSELR,        0, 2),
 375         CFG_MUX(MUX_ETH2,       RCC_ETH12CKSELR,        8, 2),
 376         CFG_MUX(MUX_FDCAN,      RCC_FDCANCKSELR,        0, 2),
 377         CFG_MUX(MUX_I2C3,       RCC_I2C345CKSELR,       0, 3),
 378         CFG_MUX(MUX_I2C4,       RCC_I2C345CKSELR,       3, 3),
 379         CFG_MUX(MUX_I2C5,       RCC_I2C345CKSELR,       6, 3),
 380         CFG_MUX(MUX_LPTIM1,     RCC_LPTIM1CKSELR,       0, 3),
 381         CFG_MUX(MUX_LPTIM2,     RCC_LPTIM23CKSELR,      0, 3),
 382         CFG_MUX(MUX_LPTIM3,     RCC_LPTIM23CKSELR,      3, 3),
 383         CFG_MUX(MUX_MCO1,       RCC_MCO1CFGR,           0, 3),
 384         CFG_MUX(MUX_MCO2,       RCC_MCO2CFGR,           0, 3),
 385         CFG_MUX(MUX_RNG1,       RCC_RNG1CKSELR,         0, 2),
 386         CFG_MUX(MUX_SAES,       RCC_SAESCKSELR,         0, 2),
 387         CFG_MUX(MUX_SAI1,       RCC_SAI1CKSELR,         0, 3),
 388         CFG_MUX(MUX_SAI2,       RCC_SAI2CKSELR,         0, 3),
 389         CFG_MUX(MUX_SPDIF,      RCC_SPDIFCKSELR,        0, 2),
 390         CFG_MUX(MUX_SPI1,       RCC_SPI2S1CKSELR,       0, 3),
 391         CFG_MUX(MUX_SPI4,       RCC_SPI45CKSELR,        0, 3),
 392         CFG_MUX(MUX_SPI5,       RCC_SPI45CKSELR,        3, 3),
 393         CFG_MUX(MUX_STGEN,      RCC_STGENCKSELR,        0, 2),
 394         CFG_MUX(MUX_UART1,      RCC_UART12CKSELR,       0, 3),
 395         CFG_MUX(MUX_UART2,      RCC_UART12CKSELR,       3, 3),
 396         CFG_MUX(MUX_UART4,      RCC_UART4CKSELR,        0, 3),
 397         CFG_MUX(MUX_UART6,      RCC_UART6CKSELR,        0, 3),
 398         CFG_MUX(MUX_USBO,       RCC_USBCKSELR,          4, 1),
 399         CFG_MUX(MUX_USBPHY,     RCC_USBCKSELR,          0, 2),
 400         CFG_MUX_SAFE(MUX_FMC,   RCC_FMCCKSELR,          0, 2),
 401         CFG_MUX_SAFE(MUX_QSPI,  RCC_QSPICKSELR,         0, 2),
 402         CFG_MUX_SAFE(MUX_SDMMC1, RCC_SDMMC12CKSELR,     0, 3),
 403         CFG_MUX_SAFE(MUX_SDMMC2, RCC_SDMMC12CKSELR,     3, 3),
 404 };
 405
 406 struct clk_stm32_securiy {
 407         u32     offset;
 408         u8      bit_idx;
 409         unsigned long scmi_id;
 410 };
 411
 412 enum security_clk {
 413         SECF_NONE,
 414         SECF_LPTIM2,
 415         SECF_LPTIM3,
 416         SECF_VREF,
 417         SECF_DCMIPP,
 418         SECF_USBPHY,
 419         SECF_TZC,
 420         SECF_ETZPC,
 421         SECF_IWDG1,
 422         SECF_BSEC,
 423         SECF_STGENC,
 424         SECF_STGENRO,
 425         SECF_USART1,
 426         SECF_USART2,
 427         SECF_SPI4,
 428         SECF_SPI5,
 429         SECF_I2C3,
 430         SECF_I2C4,
 431         SECF_I2C5,
 432         SECF_TIM12,
 433         SECF_TIM13,
 434         SECF_TIM14,
 435         SECF_TIM15,
 436         SECF_TIM16,
 437         SECF_TIM17,
 438         SECF_DMA3,
 439         SECF_DMAMUX2,
 440         SECF_ADC1,
 441         SECF_ADC2,
 442         SECF_USBO,
 443         SECF_TSC,
 444         SECF_PKA,
 445         SECF_SAES,
 446         SECF_CRYP1,
 447         SECF_HASH1,
 448         SECF_RNG1,
 449         SECF_BKPSRAM,
 450         SECF_MCE,
 451         SECF_FMC,
 452         SECF_QSPI,
 453         SECF_SDMMC1,
 454         SECF_SDMMC2,
 455         SECF_ETH1CK,
 456         SECF_ETH1TX,
 457         SECF_ETH1RX,
 458         SECF_ETH1MAC,
 459         SECF_ETH1STP,
 460         SECF_ETH2CK,
 461         SECF_ETH2TX,
 462         SECF_ETH2RX,
 463         SECF_ETH2MAC,
 464         SECF_ETH2STP,
 465         SECF_MCO1,
 466         SECF_MCO2
 467 };
 468
 469 #define SECF(_sec_id, _offset, _bit_idx)[_sec_id] = {\
 470         .offset = _offset,\
 471         .bit_idx        = _bit_idx,\
 472         .scmi_id        = -1,\
 473 }
 474
 475 static const struct clk_stm32_securiy stm32mp13_security[] = {
 476         SECF(SECF_LPTIM2, RCC_APB3SECSR, RCC_APB3SECSR_LPTIM2SECF),
 477         SECF(SECF_LPTIM3, RCC_APB3SECSR, RCC_APB3SECSR_LPTIM3SECF),
 478         SECF(SECF_VREF, RCC_APB3SECSR, RCC_APB3SECSR_VREFSECF),
 479         SECF(SECF_DCMIPP, RCC_APB4SECSR, RCC_APB4SECSR_DCMIPPSECF),
 480         SECF(SECF_USBPHY, RCC_APB4SECSR, RCC_APB4SECSR_USBPHYSECF),
 481         SECF(SECF_TZC, RCC_APB5SECSR, RCC_APB5SECSR_TZCSECF),
 482         SECF(SECF_ETZPC, RCC_APB5SECSR, RCC_APB5SECSR_ETZPCSECF),
 483         SECF(SECF_IWDG1, RCC_APB5SECSR, RCC_APB5SECSR_IWDG1SECF),
 484         SECF(SECF_BSEC, RCC_APB5SECSR, RCC_APB5SECSR_BSECSECF),
 485         SECF(SECF_STGENC, RCC_APB5SECSR, RCC_APB5SECSR_STGENCSECF),
 486         SECF(SECF_STGENRO, RCC_APB5SECSR, RCC_APB5SECSR_STGENROSECF),
 487         SECF(SECF_USART1, RCC_APB6SECSR, RCC_APB6SECSR_USART1SECF),
 488         SECF(SECF_USART2, RCC_APB6SECSR, RCC_APB6SECSR_USART2SECF),
 489         SECF(SECF_SPI4, RCC_APB6SECSR, RCC_APB6SECSR_SPI4SECF),
 490         SECF(SECF_SPI5, RCC_APB6SECSR, RCC_APB6SECSR_SPI5SECF),
 491         SECF(SECF_I2C3, RCC_APB6SECSR, RCC_APB6SECSR_I2C3SECF),
 492         SECF(SECF_I2C4, RCC_APB6SECSR, RCC_APB6SECSR_I2C4SECF),
 493         SECF(SECF_I2C5, RCC_APB6SECSR, RCC_APB6SECSR_I2C5SECF),
 494         SECF(SECF_TIM12, RCC_APB6SECSR, RCC_APB6SECSR_TIM12SECF),
 495         SECF(SECF_TIM13, RCC_APB6SECSR, RCC_APB6SECSR_TIM13SECF),
 496         SECF(SECF_TIM14, RCC_APB6SECSR, RCC_APB6SECSR_TIM14SECF),
 497         SECF(SECF_TIM15, RCC_APB6SECSR, RCC_APB6SECSR_TIM15SECF),
 498         SECF(SECF_TIM16, RCC_APB6SECSR, RCC_APB6SECSR_TIM16SECF),
 499         SECF(SECF_TIM17, RCC_APB6SECSR, RCC_APB6SECSR_TIM17SECF),
 500         SECF(SECF_DMA3, RCC_AHB2SECSR, RCC_AHB2SECSR_DMA3SECF),
 501         SECF(SECF_DMAMUX2, RCC_AHB2SECSR, RCC_AHB2SECSR_DMAMUX2SECF),
 502         SECF(SECF_ADC1, RCC_AHB2SECSR, RCC_AHB2SECSR_ADC1SECF),
 503         SECF(SECF_ADC2, RCC_AHB2SECSR, RCC_AHB2SECSR_ADC2SECF),
 504         SECF(SECF_USBO, RCC_AHB2SECSR, RCC_AHB2SECSR_USBOSECF),
 505         SECF(SECF_TSC, RCC_AHB4SECSR, RCC_AHB4SECSR_TSCSECF),
 506         SECF(SECF_PKA, RCC_AHB5SECSR, RCC_AHB5SECSR_PKASECF),
 507         SECF(SECF_SAES, RCC_AHB5SECSR, RCC_AHB5SECSR_SAESSECF),
 508         SECF(SECF_CRYP1, RCC_AHB5SECSR, RCC_AHB5SECSR_CRYP1SECF),
 509         SECF(SECF_HASH1, RCC_AHB5SECSR, RCC_AHB5SECSR_HASH1SECF),
 510         SECF(SECF_RNG1, RCC_AHB5SECSR, RCC_AHB5SECSR_RNG1SECF),
 511         SECF(SECF_BKPSRAM, RCC_AHB5SECSR, RCC_AHB5SECSR_BKPSRAMSECF),
 512         SECF(SECF_MCE, RCC_AHB6SECSR, RCC_AHB6SECSR_MCESECF),
 513         SECF(SECF_FMC, RCC_AHB6SECSR, RCC_AHB6SECSR_FMCSECF),
 514         SECF(SECF_QSPI, RCC_AHB6SECSR, RCC_AHB6SECSR_QSPISECF),
 515         SECF(SECF_SDMMC1, RCC_AHB6SECSR, RCC_AHB6SECSR_SDMMC1SECF),
 516         SECF(SECF_SDMMC2, RCC_AHB6SECSR, RCC_AHB6SECSR_SDMMC2SECF),
 517         SECF(SECF_ETH1CK, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH1CKSECF),
 518         SECF(SECF_ETH1TX, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH1TXSECF),
 519         SECF(SECF_ETH1RX, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH1RXSECF),
 520         SECF(SECF_ETH1MAC, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH1MACSECF),
 521         SECF(SECF_ETH1STP, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH1STPSECF),
 522         SECF(SECF_ETH2CK, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH2CKSECF),
 523         SECF(SECF_ETH2TX, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH2TXSECF),
 524         SECF(SECF_ETH2RX, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH2RXSECF),
 525         SECF(SECF_ETH2MAC, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH2MACSECF),
 526         SECF(SECF_ETH2STP, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH2STPSECF),
 527         SECF(SECF_MCO1, RCC_SECCFGR, RCC_SECCFGR_MCO1SEC),
 528         SECF(SECF_MCO2, RCC_SECCFGR, RCC_SECCFGR_MCO2SEC),
 529 };
 530
 531 static const char * const adc12_src[] = {
 532         "pll4_r", "ck_per", "pll3_q"
 533 };
 534
 535 static const char * const dcmipp_src[] = {
 536         "ck_axi", "pll2_q", "pll4_p", "ck_per",
 537 };
 538
 539 static const char * const eth12_src[] = {
 540         "pll4_p", "pll3_q"
 541 };
 542
 543 static const char * const fdcan_src[] = {
 544         "ck_hse", "pll3_q", "pll4_q", "pll4_r"
 545 };
 546
 547 static const char * const fmc_src[] = {
 548         "ck_axi", "pll3_r", "pll4_p", "ck_per"
 549 };
 550
 551 static const char * const i2c12_src[] = {
 552         "pclk1", "pll4_r", "ck_hsi", "ck_csi"
 553 };
 554
 555 static const char * const i2c345_src[] = {
 556         "pclk6", "pll4_r", "ck_hsi", "ck_csi"
 557 };
 558
 559 static const char * const lptim1_src[] = {
 560         "pclk1", "pll4_p", "pll3_q", "ck_lse", "ck_lsi", "ck_per"
 561 };
 562
 563 static const char * const lptim23_src[] = {
 564         "pclk3", "pll4_q", "ck_per", "ck_lse", "ck_lsi"
 565 };
 566
 567 static const char * const lptim45_src[] = {
 568         "pclk3", "pll4_p", "pll3_q", "ck_lse", "ck_lsi", "ck_per"
 569 };
 570
 571 static const char * const mco1_src[] = {
 572         "ck_hsi", "ck_hse", "ck_csi", "ck_lsi", "ck_lse"
 573 };
 574
 575 static const char * const mco2_src[] = {
 576         "ck_mpu", "ck_axi", "ck_mlahb", "pll4_p", "ck_hse", "ck_hsi"
 577 };
 578
 579 static const char * const qspi_src[] = {
 580         "ck_axi", "pll3_r", "pll4_p", "ck_per"
 581 };
 582
 583 static const char * const rng1_src[] = {
 584         "ck_csi", "pll4_r", "ck_lse", "ck_lsi"
 585 };
 586
 587 static const char * const saes_src[] = {
 588         "ck_axi", "ck_per", "pll4_r", "ck_lsi"
 589 };
 590
 591 static const char * const sai1_src[] = {
 592         "pll4_q", "pll3_q", "i2s_ckin", "ck_per", "pll3_r"
 593 };
 594
 595 static const char * const sai2_src[] = {
 596         "pll4_q", "pll3_q", "i2s_ckin", "ck_per", "spdif_ck_symb", "pll3_r"
 597 };
 598
 599 static const char * const sdmmc12_src[] = {
 600         "ck_axi", "pll3_r", "pll4_p", "ck_hsi"
 601 };
 602
 603 static const char * const spdif_src[] = {
 604         "pll4_p", "pll3_q", "ck_hsi"
 605 };
 606
 607 static const char * const spi123_src[] = {
 608         "pll4_p", "pll3_q", "i2s_ckin", "ck_per", "pll3_r"
 609 };
 610
 611 static const char * const spi4_src[] = {
 612         "pclk6", "pll4_q", "ck_hsi", "ck_csi", "ck_hse", "i2s_ckin"
 613 };
 614
 615 static const char * const spi5_src[] = {
 616         "pclk6", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
 617 };
 618
 619 static const char * const stgen_src[] = {
 620         "ck_hsi", "ck_hse"
 621 };
 622
 623 static const char * const usart12_src[] = {
 624         "pclk6", "pll3_q", "ck_hsi", "ck_csi", "pll4_q", "ck_hse"
 625 };
 626
 627 static const char * const usart34578_src[] = {
 628         "pclk1", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
 629 };
 630
 631 static const char * const usart6_src[] = {
 632         "pclk2", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
 633 };
 634
 635 static const char * const usbo_src[] = {
 636         "pll4_r", "ck_usbo_48m"
 637 };
 638
 639 static const char * const usbphy_src[] = {
 640         "ck_hse", "pll4_r", "clk-hse-div2"
 641 };
 642
 643 /* Timer clocks */
 644 static struct clk_stm32_gate tim2_k = {
 645         .gate_id = GATE_TIM2,
 646         .hw.init = CLK_HW_INIT("tim2_k", "timg1_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
 647 };
 648
 649 static struct clk_stm32_gate tim3_k = {
 650         .gate_id = GATE_TIM3,
 651         .hw.init = CLK_HW_INIT("tim3_k", "timg1_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
 652 };
 653
 654 static struct clk_stm32_gate tim4_k = {
 655         .gate_id = GATE_TIM4,
 656         .hw.init = CLK_HW_INIT("tim4_k", "timg1_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
 657 };
 658
 659 static struct clk_stm32_gate tim5_k = {
 660         .gate_id = GATE_TIM5,
 661         .hw.init = CLK_HW_INIT("tim5_k", "timg1_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
 662 };
 663
 664 static struct clk_stm32_gate tim6_k = {
 665         .gate_id = GATE_TIM6,
 666         .hw.init = CLK_HW_INIT("tim6_k", "timg1_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
 667 };
 668
 669 static struct clk_stm32_gate tim7_k = {
 670         .gate_id = GATE_TIM7,
 671         .hw.init = CLK_HW_INIT("tim7_k", "timg1_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
 672 };
 673
 674 static struct clk_stm32_gate tim1_k = {
 675         .gate_id = GATE_TIM1,
 676         .hw.init = CLK_HW_INIT("tim1_k", "timg2_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
 677 };
 678
 679 static struct clk_stm32_gate tim8_k = {
 680         .gate_id = GATE_TIM8,
 681         .hw.init = CLK_HW_INIT("tim8_k", "timg2_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
 682 };
 683
 684 static struct clk_stm32_gate tim12_k = {
 685         .gate_id = GATE_TIM12,
 686         .hw.init = CLK_HW_INIT("tim12_k", "timg3_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
 687 };
 688
 689 static struct clk_stm32_gate tim13_k = {
 690         .gate_id = GATE_TIM13,
 691         .hw.init = CLK_HW_INIT("tim13_k", "timg3_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
 692 };
 693
 694 static struct clk_stm32_gate tim14_k = {
 695         .gate_id = GATE_TIM14,
 696         .hw.init = CLK_HW_INIT("tim14_k", "timg3_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
 697 };
 698
 699 static struct clk_stm32_gate tim15_k = {
 700         .gate_id = GATE_TIM15,
 701         .hw.init = CLK_HW_INIT("tim15_k", "timg3_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
 702 };
 703
 704 static struct clk_stm32_gate tim16_k = {
 705         .gate_id = GATE_TIM16,
 706         .hw.init = CLK_HW_INIT("tim16_k", "timg3_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
 707 };
 708
 709 static struct clk_stm32_gate tim17_k = {
 710         .gate_id = GATE_TIM17,
 711         .hw.init = CLK_HW_INIT("tim17_k", "timg3_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
 712 };
 713
 714 /* Peripheral clocks */
 715 static struct clk_stm32_gate sai1 = {
 716         .gate_id = GATE_SAI1,
 717         .hw.init = CLK_HW_INIT("sai1", "pclk2", &clk_stm32_gate_ops, 0),
 718 };
 719
 720 static struct clk_stm32_gate sai2 = {
 721         .gate_id = GATE_SAI2,
 722         .hw.init = CLK_HW_INIT("sai2", "pclk2", &clk_stm32_gate_ops, 0),
 723 };
 724
 725 static struct clk_stm32_gate syscfg = {
 726         .gate_id = GATE_SYSCFG,
 727         .hw.init = CLK_HW_INIT("syscfg", "pclk3", &clk_stm32_gate_ops, 0),
 728 };
 729
 730 static struct clk_stm32_gate vref = {
 731         .gate_id = GATE_VREF,
 732         .hw.init = CLK_HW_INIT("vref", "pclk3", &clk_stm32_gate_ops, 0),
 733 };
 734
 735 static struct clk_stm32_gate dts = {
 736         .gate_id = GATE_DTS,
 737         .hw.init = CLK_HW_INIT("dts", "pclk3", &clk_stm32_gate_ops, 0),
 738 };
 739
 740 static struct clk_stm32_gate pmbctrl = {
 741         .gate_id = GATE_PMBCTRL,
 742         .hw.init = CLK_HW_INIT("pmbctrl", "pclk3", &clk_stm32_gate_ops, 0),
 743 };
 744
 745 static struct clk_stm32_gate hdp = {
 746         .gate_id = GATE_HDP,
 747         .hw.init = CLK_HW_INIT("hdp", "pclk3", &clk_stm32_gate_ops, 0),
 748 };
 749
 750 static struct clk_stm32_gate iwdg2 = {
 751         .gate_id = GATE_IWDG2APB,
 752         .hw.init = CLK_HW_INIT("iwdg2", "pclk4", &clk_stm32_gate_ops, 0),
 753 };
 754
 755 static struct clk_stm32_gate stgenro = {
 756         .gate_id = GATE_STGENRO,
 757         .hw.init = CLK_HW_INIT("stgenro", "pclk4", &clk_stm32_gate_ops, 0),
 758 };
 759
 760 static struct clk_stm32_gate gpioa = {
 761         .gate_id = GATE_GPIOA,
 762         .hw.init = CLK_HW_INIT("gpioa", "pclk4", &clk_stm32_gate_ops, 0),
 763 };
 764
 765 static struct clk_stm32_gate gpiob = {
 766         .gate_id = GATE_GPIOB,
 767         .hw.init = CLK_HW_INIT("gpiob", "pclk4", &clk_stm32_gate_ops, 0),
 768 };
 769
 770 static struct clk_stm32_gate gpioc = {
 771         .gate_id = GATE_GPIOC,
 772         .hw.init = CLK_HW_INIT("gpioc", "pclk4", &clk_stm32_gate_ops, 0),
 773 };
 774
 775 static struct clk_stm32_gate gpiod = {
 776         .gate_id = GATE_GPIOD,
 777         .hw.init = CLK_HW_INIT("gpiod", "pclk4", &clk_stm32_gate_ops, 0),
 778 };
 779
 780 static struct clk_stm32_gate gpioe = {
 781         .gate_id = GATE_GPIOE,
 782         .hw.init = CLK_HW_INIT("gpioe", "pclk4", &clk_stm32_gate_ops, 0),
 783 };
 784
 785 static struct clk_stm32_gate gpiof = {
 786         .gate_id = GATE_GPIOF,
 787         .hw.init = CLK_HW_INIT("gpiof", "pclk4", &clk_stm32_gate_ops, 0),
 788 };
 789
 790 static struct clk_stm32_gate gpiog = {
 791         .gate_id = GATE_GPIOG,
 792         .hw.init = CLK_HW_INIT("gpiog", "pclk4", &clk_stm32_gate_ops, 0),
 793 };
 794
 795 static struct clk_stm32_gate gpioh = {
 796         .gate_id = GATE_GPIOH,
 797         .hw.init = CLK_HW_INIT("gpioh", "pclk4", &clk_stm32_gate_ops, 0),
 798 };
 799
 800 static struct clk_stm32_gate gpioi = {
 801         .gate_id = GATE_GPIOI,
 802         .hw.init = CLK_HW_INIT("gpioi", "pclk4", &clk_stm32_gate_ops, 0),
 803 };
 804
 805 static struct clk_stm32_gate tsc = {
 806         .gate_id = GATE_TSC,
 807         .hw.init = CLK_HW_INIT("tsc", "pclk4", &clk_stm32_gate_ops, 0),
 808 };
 809
 810 static struct clk_stm32_gate ddrperfm = {
 811         .gate_id = GATE_DDRPERFM,
 812         .hw.init = CLK_HW_INIT("ddrperfm", "pclk4", &clk_stm32_gate_ops, 0),
 813 };
 814
 815 static struct clk_stm32_gate tzpc = {
 816         .gate_id = GATE_TZC,
 817         .hw.init = CLK_HW_INIT("tzpc", "pclk5", &clk_stm32_gate_ops, 0),
 818 };
 819
 820 static struct clk_stm32_gate iwdg1 = {
 821         .gate_id = GATE_IWDG1APB,
 822         .hw.init = CLK_HW_INIT("iwdg1", "pclk5", &clk_stm32_gate_ops, 0),
 823 };
 824
 825 static struct clk_stm32_gate bsec = {
 826         .gate_id = GATE_BSEC,
 827         .hw.init = CLK_HW_INIT("bsec", "pclk5", &clk_stm32_gate_ops, 0),
 828 };
 829
 830 static struct clk_stm32_gate dma1 = {
 831         .gate_id = GATE_DMA1,
 832         .hw.init = CLK_HW_INIT("dma1", "ck_mlahb", &clk_stm32_gate_ops, 0),
 833 };
 834
 835 static struct clk_stm32_gate dma2 = {
 836         .gate_id = GATE_DMA2,
 837         .hw.init = CLK_HW_INIT("dma2", "ck_mlahb", &clk_stm32_gate_ops, 0),
 838 };
 839
 840 static struct clk_stm32_gate dmamux1 = {
 841         .gate_id = GATE_DMAMUX1,
 842         .hw.init = CLK_HW_INIT("dmamux1", "ck_mlahb", &clk_stm32_gate_ops, 0),
 843 };
 844
 845 static struct clk_stm32_gate dma3 = {
 846         .gate_id = GATE_DMA3,
 847         .hw.init = CLK_HW_INIT("dma3", "ck_mlahb", &clk_stm32_gate_ops, 0),
 848 };
 849
 850 static struct clk_stm32_gate dmamux2 = {
 851         .gate_id = GATE_DMAMUX2,
 852         .hw.init = CLK_HW_INIT("dmamux2", "ck_mlahb", &clk_stm32_gate_ops, 0),
 853 };
 854
 855 static struct clk_stm32_gate adc1 = {
 856         .gate_id = GATE_ADC1,
 857         .hw.init = CLK_HW_INIT("adc1", "ck_mlahb", &clk_stm32_gate_ops, 0),
 858 };
 859
 860 static struct clk_stm32_gate adc2 = {
 861         .gate_id = GATE_ADC2,
 862         .hw.init = CLK_HW_INIT("adc2", "ck_mlahb", &clk_stm32_gate_ops, 0),
 863 };
 864
 865 static struct clk_stm32_gate pka = {
 866         .gate_id = GATE_PKA,
 867         .hw.init = CLK_HW_INIT("pka", "ck_axi", &clk_stm32_gate_ops, 0),
 868 };
 869
 870 static struct clk_stm32_gate cryp1 = {
 871         .gate_id = GATE_CRYP1,
 872         .hw.init = CLK_HW_INIT("cryp1", "ck_axi", &clk_stm32_gate_ops, 0),
 873 };
 874
 875 static struct clk_stm32_gate hash1 = {
 876         .gate_id = GATE_HASH1,
 877         .hw.init = CLK_HW_INIT("hash1", "ck_axi", &clk_stm32_gate_ops, 0),
 878 };
 879
 880 static struct clk_stm32_gate bkpsram = {
 881         .gate_id = GATE_BKPSRAM,
 882         .hw.init = CLK_HW_INIT("bkpsram", "ck_axi", &clk_stm32_gate_ops, 0),
 883 };
 884
 885 static struct clk_stm32_gate mdma = {
 886         .gate_id = GATE_MDMA,
 887         .hw.init = CLK_HW_INIT("mdma", "ck_axi", &clk_stm32_gate_ops, 0),
 888 };
 889
 890 static struct clk_stm32_gate eth1tx = {
 891         .gate_id = GATE_ETH1TX,
 892         .hw.init = CLK_HW_INIT("eth1tx", "ck_axi", &clk_stm32_gate_ops, 0),
 893 };
 894
 895 static struct clk_stm32_gate eth1rx = {
 896         .gate_id = GATE_ETH1RX,
 897         .hw.init = CLK_HW_INIT("eth1rx", "ck_axi", &clk_stm32_gate_ops, 0),
 898 };
 899
 900 static struct clk_stm32_gate eth1mac = {
 901         .gate_id = GATE_ETH1MAC,
 902         .hw.init = CLK_HW_INIT("eth1mac", "ck_axi", &clk_stm32_gate_ops, 0),
 903 };
 904
 905 static struct clk_stm32_gate eth2tx = {
 906         .gate_id = GATE_ETH2TX,
 907         .hw.init = CLK_HW_INIT("eth2tx", "ck_axi", &clk_stm32_gate_ops, 0),
 908 };
 909
 910 static struct clk_stm32_gate eth2rx = {
 911         .gate_id = GATE_ETH2RX,
 912         .hw.init = CLK_HW_INIT("eth2rx", "ck_axi", &clk_stm32_gate_ops, 0),
 913 };
 914
 915 static struct clk_stm32_gate eth2mac = {
 916         .gate_id = GATE_ETH2MAC,
 917         .hw.init = CLK_HW_INIT("eth2mac", "ck_axi", &clk_stm32_gate_ops, 0),
 918 };
 919
 920 static struct clk_stm32_gate crc1 = {
 921         .gate_id = GATE_CRC1,
 922         .hw.init = CLK_HW_INIT("crc1", "ck_axi", &clk_stm32_gate_ops, 0),
 923 };
 924
 925 static struct clk_stm32_gate usbh = {
 926         .gate_id = GATE_USBH,
 927         .hw.init = CLK_HW_INIT("usbh", "ck_axi", &clk_stm32_gate_ops, 0),
 928 };
 929
 930 static struct clk_stm32_gate eth1stp = {
 931         .gate_id = GATE_ETH1STP,
 932         .hw.init = CLK_HW_INIT("eth1stp", "ck_axi", &clk_stm32_gate_ops, 0),
 933 };
 934
 935 static struct clk_stm32_gate eth2stp = {
 936         .gate_id = GATE_ETH2STP,
 937         .hw.init = CLK_HW_INIT("eth2stp", "ck_axi", &clk_stm32_gate_ops, 0),
 938 };
 939
 940 /* Kernel clocks */
 941 static struct clk_stm32_composite sdmmc1_k = {
 942         .gate_id = GATE_SDMMC1,
 943         .mux_id = MUX_SDMMC1,
 944         .div_id = NO_STM32_DIV,
 945         .hw.init = CLK_HW_INIT_PARENTS("sdmmc1_k", sdmmc12_src, &clk_stm32_composite_ops,
 946                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
 947 };
 948
 949 static struct clk_stm32_composite sdmmc2_k = {
 950         .gate_id = GATE_SDMMC2,
 951         .mux_id = MUX_SDMMC2,
 952         .div_id = NO_STM32_DIV,
 953         .hw.init = CLK_HW_INIT_PARENTS("sdmmc2_k", sdmmc12_src, &clk_stm32_composite_ops,
 954                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
 955 };
 956
 957 static struct clk_stm32_composite fmc_k = {
 958         .gate_id = GATE_FMC,
 959         .mux_id = MUX_FMC,
 960         .div_id = NO_STM32_DIV,
 961         .hw.init = CLK_HW_INIT_PARENTS("fmc_k", fmc_src, &clk_stm32_composite_ops,
 962                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
 963 };
 964
 965 static struct clk_stm32_composite qspi_k = {
 966         .gate_id = GATE_QSPI,
 967         .mux_id = MUX_QSPI,
 968         .div_id = NO_STM32_DIV,
 969         .hw.init = CLK_HW_INIT_PARENTS("qspi_k", qspi_src, &clk_stm32_composite_ops,
 970                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
 971 };
 972
 973 static struct clk_stm32_composite spi2_k = {
 974         .gate_id = GATE_SPI2,
 975         .mux_id = MUX_SPI23,
 976         .div_id = NO_STM32_DIV,
 977         .hw.init = CLK_HW_INIT_PARENTS("spi2_k", spi123_src, &clk_stm32_composite_ops,
 978                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
 979 };
 980
 981 static struct clk_stm32_composite spi3_k = {
 982         .gate_id = GATE_SPI3,
 983         .mux_id = MUX_SPI23,
 984         .div_id = NO_STM32_DIV,
 985         .hw.init = CLK_HW_INIT_PARENTS("spi3_k", spi123_src, &clk_stm32_composite_ops,
 986                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
 987 };
 988
 989 static struct clk_stm32_composite i2c1_k = {
 990         .gate_id = GATE_I2C1,
 991         .mux_id = MUX_I2C12,
 992         .div_id = NO_STM32_DIV,
 993         .hw.init = CLK_HW_INIT_PARENTS("i2c1_k", i2c12_src, &clk_stm32_composite_ops,
 994                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
 995 };
 996
 997 static struct clk_stm32_composite i2c2_k = {
 998         .gate_id = GATE_I2C2,
 999         .mux_id = MUX_I2C12,
1000         .div_id = NO_STM32_DIV,
1001         .hw.init = CLK_HW_INIT_PARENTS("i2c2_k", i2c12_src, &clk_stm32_composite_ops,
1002                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1003 };
1004
1005 static struct clk_stm32_composite lptim4_k = {
1006         .gate_id = GATE_LPTIM4,
1007         .mux_id = MUX_LPTIM45,
1008         .div_id = NO_STM32_DIV,
1009         .hw.init = CLK_HW_INIT_PARENTS("lptim4_k", lptim45_src, &clk_stm32_composite_ops,
1010                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1011 };
1012
1013 static struct clk_stm32_composite lptim5_k = {
1014         .gate_id = GATE_LPTIM5,
1015         .mux_id = MUX_LPTIM45,
1016         .div_id = NO_STM32_DIV,
1017         .hw.init = CLK_HW_INIT_PARENTS("lptim5_k", lptim45_src, &clk_stm32_composite_ops,
1018                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1019 };
1020
1021 static struct clk_stm32_composite usart3_k = {
1022         .gate_id = GATE_USART3,
1023         .mux_id = MUX_UART35,
1024         .div_id = NO_STM32_DIV,
1025         .hw.init = CLK_HW_INIT_PARENTS("usart3_k", usart34578_src, &clk_stm32_composite_ops,
1026                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1027 };
1028
1029 static struct clk_stm32_composite uart5_k = {
1030         .gate_id = GATE_UART5,
1031         .mux_id = MUX_UART35,
1032         .div_id = NO_STM32_DIV,
1033         .hw.init = CLK_HW_INIT_PARENTS("uart5_k", usart34578_src, &clk_stm32_composite_ops,
1034                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1035 };
1036
1037 static struct clk_stm32_composite uart7_k = {
1038         .gate_id = GATE_UART7,
1039         .mux_id = MUX_UART78,
1040         .div_id = NO_STM32_DIV,
1041         .hw.init = CLK_HW_INIT_PARENTS("uart7_k", usart34578_src, &clk_stm32_composite_ops,
1042                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1043 };
1044
1045 static struct clk_stm32_composite uart8_k = {
1046         .gate_id = GATE_UART8,
1047         .mux_id = MUX_UART78,
1048         .div_id = NO_STM32_DIV,
1049         .hw.init = CLK_HW_INIT_PARENTS("uart8_k", usart34578_src, &clk_stm32_composite_ops,
1050                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1051 };
1052
1053 static struct clk_stm32_composite sai1_k = {
1054         .gate_id = GATE_SAI1,
1055         .mux_id = MUX_SAI1,
1056         .div_id = NO_STM32_DIV,
1057         .hw.init = CLK_HW_INIT_PARENTS("sai1_k", sai1_src, &clk_stm32_composite_ops,
1058                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1059 };
1060
1061 static struct clk_stm32_composite adfsdm_k = {
1062         .gate_id = GATE_ADFSDM,
1063         .mux_id = MUX_SAI1,
1064         .div_id = NO_STM32_DIV,
1065         .hw.init = CLK_HW_INIT_PARENTS("adfsdm_k", sai1_src, &clk_stm32_composite_ops,
1066                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1067 };
1068
1069 static struct clk_stm32_composite sai2_k = {
1070         .gate_id = GATE_SAI2,
1071         .mux_id = MUX_SAI2,
1072         .div_id = NO_STM32_DIV,
1073         .hw.init = CLK_HW_INIT_PARENTS("sai2_k", sai2_src, &clk_stm32_composite_ops,
1074                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1075 };
1076
1077 static struct clk_stm32_composite adc1_k = {
1078         .gate_id = GATE_ADC1,
1079         .mux_id = MUX_ADC1,
1080         .div_id = NO_STM32_DIV,
1081         .hw.init = CLK_HW_INIT_PARENTS("adc1_k", adc12_src, &clk_stm32_composite_ops,
1082                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1083 };
1084
1085 static struct clk_stm32_composite adc2_k = {
1086         .gate_id = GATE_ADC2,
1087         .mux_id = MUX_ADC2,
1088         .div_id = NO_STM32_DIV,
1089         .hw.init = CLK_HW_INIT_PARENTS("adc2_k", adc12_src, &clk_stm32_composite_ops,
1090                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1091 };
1092
1093 static struct clk_stm32_composite rng1_k = {
1094         .gate_id = GATE_RNG1,
1095         .mux_id = MUX_RNG1,
1096         .div_id = NO_STM32_DIV,
1097         .hw.init = CLK_HW_INIT_PARENTS("rng1_k", rng1_src, &clk_stm32_composite_ops,
1098                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1099 };
1100
1101 static struct clk_stm32_composite usbphy_k = {
1102         .gate_id = GATE_USBPHY,
1103         .mux_id = MUX_USBPHY,
1104         .div_id = NO_STM32_DIV,
1105         .hw.init = CLK_HW_INIT_PARENTS("usbphy_k", usbphy_src, &clk_stm32_composite_ops,
1106                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1107 };
1108
1109 static struct clk_stm32_composite stgen_k = {
1110         .gate_id = GATE_STGENC,
1111         .mux_id = MUX_STGEN,
1112         .div_id = NO_STM32_DIV,
1113         .hw.init = CLK_HW_INIT_PARENTS("stgen_k", stgen_src, &clk_stm32_composite_ops,
1114                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1115 };
1116
1117 static struct clk_stm32_composite spdif_k = {
1118         .gate_id = GATE_SPDIF,
1119         .mux_id = MUX_SPDIF,
1120         .div_id = NO_STM32_DIV,
1121         .hw.init = CLK_HW_INIT_PARENTS("spdif_k", spdif_src, &clk_stm32_composite_ops,
1122                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1123 };
1124
1125 static struct clk_stm32_composite spi1_k = {
1126         .gate_id = GATE_SPI1,
1127         .mux_id = MUX_SPI1,
1128         .div_id = NO_STM32_DIV,
1129         .hw.init = CLK_HW_INIT_PARENTS("spi1_k", spi123_src, &clk_stm32_composite_ops,
1130                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1131 };
1132
1133 static struct clk_stm32_composite spi4_k = {
1134         .gate_id = GATE_SPI4,
1135         .mux_id = MUX_SPI4,
1136         .div_id = NO_STM32_DIV,
1137         .hw.init = CLK_HW_INIT_PARENTS("spi4_k", spi4_src, &clk_stm32_composite_ops,
1138                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1139 };
1140
1141 static struct clk_stm32_composite spi5_k = {
1142         .gate_id = GATE_SPI5,
1143         .mux_id = MUX_SPI5,
1144         .div_id = NO_STM32_DIV,
1145         .hw.init = CLK_HW_INIT_PARENTS("spi5_k", spi5_src, &clk_stm32_composite_ops,
1146                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1147 };
1148
1149 static struct clk_stm32_composite i2c3_k = {
1150         .gate_id = GATE_I2C3,
1151         .mux_id = MUX_I2C3,
1152         .div_id = NO_STM32_DIV,
1153         .hw.init = CLK_HW_INIT_PARENTS("i2c3_k", i2c345_src, &clk_stm32_composite_ops,
1154                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1155 };
1156
1157 static struct clk_stm32_composite i2c4_k = {
1158         .gate_id = GATE_I2C4,
1159         .mux_id = MUX_I2C4,
1160         .div_id = NO_STM32_DIV,
1161         .hw.init = CLK_HW_INIT_PARENTS("i2c4_k", i2c345_src, &clk_stm32_composite_ops,
1162                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1163 };
1164
1165 static struct clk_stm32_composite i2c5_k = {
1166         .gate_id = GATE_I2C5,
1167         .mux_id = MUX_I2C5,
1168         .div_id = NO_STM32_DIV,
1169         .hw.init = CLK_HW_INIT_PARENTS("i2c5_k", i2c345_src, &clk_stm32_composite_ops,
1170                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1171 };
1172
1173 static struct clk_stm32_composite lptim1_k = {
1174         .gate_id = GATE_LPTIM1,
1175         .mux_id = MUX_LPTIM1,
1176         .div_id = NO_STM32_DIV,
1177         .hw.init = CLK_HW_INIT_PARENTS("lptim1_k", lptim1_src, &clk_stm32_composite_ops,
1178                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1179 };
1180
1181 static struct clk_stm32_composite lptim2_k = {
1182         .gate_id = GATE_LPTIM2,
1183         .mux_id = MUX_LPTIM2,
1184         .div_id = NO_STM32_DIV,
1185         .hw.init = CLK_HW_INIT_PARENTS("lptim2_k", lptim23_src, &clk_stm32_composite_ops,
1186                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1187 };
1188
1189 static struct clk_stm32_composite lptim3_k = {
1190         .gate_id = GATE_LPTIM3,
1191         .mux_id = MUX_LPTIM3,
1192         .div_id = NO_STM32_DIV,
1193         .hw.init = CLK_HW_INIT_PARENTS("lptim3_k", lptim23_src, &clk_stm32_composite_ops,
1194                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1195 };
1196
1197 static struct clk_stm32_composite usart1_k = {
1198         .gate_id = GATE_USART1,
1199         .mux_id = MUX_UART1,
1200         .div_id = NO_STM32_DIV,
1201         .hw.init = CLK_HW_INIT_PARENTS("usart1_k", usart12_src, &clk_stm32_composite_ops,
1202                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1203 };
1204
1205 static struct clk_stm32_composite usart2_k = {
1206         .gate_id = GATE_USART2,
1207         .mux_id = MUX_UART2,
1208         .div_id = NO_STM32_DIV,
1209         .hw.init = CLK_HW_INIT_PARENTS("usart2_k", usart12_src, &clk_stm32_composite_ops,
1210                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1211 };
1212
1213 static struct clk_stm32_composite uart4_k = {
1214         .gate_id = GATE_UART4,
1215         .mux_id = MUX_UART4,
1216         .div_id = NO_STM32_DIV,
1217         .hw.init = CLK_HW_INIT_PARENTS("uart4_k", usart34578_src, &clk_stm32_composite_ops,
1218                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1219 };
1220
1221 static struct clk_stm32_composite uart6_k = {
1222         .gate_id = GATE_USART6,
1223         .mux_id = MUX_UART6,
1224         .div_id = NO_STM32_DIV,
1225         .hw.init = CLK_HW_INIT_PARENTS("uart6_k", usart6_src, &clk_stm32_composite_ops,
1226                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1227 };
1228
1229 static struct clk_stm32_composite fdcan_k = {
1230         .gate_id = GATE_FDCAN,
1231         .mux_id = MUX_FDCAN,
1232         .div_id = NO_STM32_DIV,
1233         .hw.init = CLK_HW_INIT_PARENTS("fdcan_k", fdcan_src, &clk_stm32_composite_ops,
1234                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1235 };
1236
1237 static struct clk_stm32_composite dcmipp_k = {
1238         .gate_id = GATE_DCMIPP,
1239         .mux_id = MUX_DCMIPP,
1240         .div_id = NO_STM32_DIV,
1241         .hw.init = CLK_HW_INIT_PARENTS("dcmipp_k", dcmipp_src, &clk_stm32_composite_ops,
1242                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1243 };
1244
1245 static struct clk_stm32_composite usbo_k = {
1246         .gate_id = GATE_USBO,
1247         .mux_id = MUX_USBO,
1248         .div_id = NO_STM32_DIV,
1249         .hw.init = CLK_HW_INIT_PARENTS("usbo_k", usbo_src, &clk_stm32_composite_ops,
1250                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1251 };
1252
1253 static struct clk_stm32_composite saes_k = {
1254         .gate_id = GATE_SAES,
1255         .mux_id = MUX_SAES,
1256         .div_id = NO_STM32_DIV,
1257         .hw.init = CLK_HW_INIT_PARENTS("saes_k", saes_src, &clk_stm32_composite_ops,
1258                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1259 };
1260
1261 static struct clk_stm32_gate dfsdm_k = {
1262         .gate_id = GATE_DFSDM,
1263         .hw.init = CLK_HW_INIT("dfsdm_k", "ck_mlahb", &clk_stm32_gate_ops, 0),
1264 };
1265
1266 static struct clk_stm32_gate ltdc_px = {
1267         .gate_id = GATE_LTDC,
1268         .hw.init = CLK_HW_INIT("ltdc_px", "pll4_q", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT),
1269 };
1270
1271 static struct clk_stm32_mux ck_ker_eth1 = {
1272         .mux_id = MUX_ETH1,
1273         .hw.init = CLK_HW_INIT_PARENTS("ck_ker_eth1", eth12_src, &clk_stm32_mux_ops,
1274                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1275 };
1276
1277 static struct clk_stm32_gate eth1ck_k = {
1278         .gate_id = GATE_ETH1CK,
1279         .hw.init = CLK_HW_INIT_HW("eth1ck_k", &ck_ker_eth1.hw, &clk_stm32_gate_ops, 0),
1280 };
1281
1282 static struct clk_stm32_div eth1ptp_k = {
1283         .div_id = DIV_ETH1PTP,
1284         .hw.init = CLK_HW_INIT_HW("eth1ptp_k", &ck_ker_eth1.hw, &clk_stm32_divider_ops,
1285                                   CLK_SET_RATE_NO_REPARENT),
1286 };
1287
1288 static struct clk_stm32_mux ck_ker_eth2 = {
1289         .mux_id = MUX_ETH2,
1290         .hw.init = CLK_HW_INIT_PARENTS("ck_ker_eth2", eth12_src, &clk_stm32_mux_ops,
1291                                             CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1292 };
1293
1294 static struct clk_stm32_gate eth2ck_k = {
1295         .gate_id = GATE_ETH2CK,
1296         .hw.init = CLK_HW_INIT_HW("eth2ck_k", &ck_ker_eth2.hw, &clk_stm32_gate_ops, 0),
1297 };
1298
1299 static struct clk_stm32_div eth2ptp_k = {
1300         .div_id = DIV_ETH2PTP,
1301         .hw.init = CLK_HW_INIT_HW("eth2ptp_k", &ck_ker_eth2.hw, &clk_stm32_divider_ops,
1302                                   CLK_SET_RATE_NO_REPARENT),
1303 };
1304
1305 static struct clk_stm32_composite ck_mco1 = {
1306         .gate_id = GATE_MCO1,
1307         .mux_id = MUX_MCO1,
1308         .div_id = DIV_MCO1,
1309         .hw.init = CLK_HW_INIT_PARENTS("ck_mco1", mco1_src, &clk_stm32_composite_ops,
1310                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT |
1311                                        CLK_IGNORE_UNUSED),
1312 };
1313
1314 static struct clk_stm32_composite ck_mco2 = {
1315         .gate_id = GATE_MCO2,
1316         .mux_id = MUX_MCO2,
1317         .div_id = DIV_MCO2,
1318         .hw.init = CLK_HW_INIT_PARENTS("ck_mco2", mco2_src, &clk_stm32_composite_ops,
1319                                        CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT |
1320                                        CLK_IGNORE_UNUSED),
1321 };
1322
1323 /* Debug clocks */
1324 static struct clk_stm32_gate ck_sys_dbg = {
1325         .gate_id = GATE_DBGCK,
1326         .hw.init = CLK_HW_INIT("ck_sys_dbg", "ck_axi", &clk_stm32_gate_ops, CLK_IS_CRITICAL),
1327 };
1328
1329 static struct clk_stm32_composite ck_trace = {
1330         .gate_id = GATE_TRACECK,
1331         .mux_id = NO_STM32_MUX,
1332         .div_id = DIV_TRACE,
1333         .hw.init = CLK_HW_INIT("ck_trace", "ck_axi", &clk_stm32_composite_ops, CLK_IGNORE_UNUSED),
1334 };
1335
1336 static const struct clock_config stm32mp13_clock_cfg[] = {
1337         /* Timer clocks */
1338         STM32_GATE_CFG(TIM2_K, tim2_k, SECF_NONE),
1339         STM32_GATE_CFG(TIM3_K, tim3_k, SECF_NONE),
1340         STM32_GATE_CFG(TIM4_K, tim4_k, SECF_NONE),
1341         STM32_GATE_CFG(TIM5_K, tim5_k, SECF_NONE),
1342         STM32_GATE_CFG(TIM6_K, tim6_k, SECF_NONE),
1343         STM32_GATE_CFG(TIM7_K, tim7_k, SECF_NONE),
1344         STM32_GATE_CFG(TIM1_K, tim1_k, SECF_NONE),
1345         STM32_GATE_CFG(TIM8_K, tim8_k, SECF_NONE),
1346         STM32_GATE_CFG(TIM12_K, tim12_k, SECF_TIM12),
1347         STM32_GATE_CFG(TIM13_K, tim13_k, SECF_TIM13),
1348         STM32_GATE_CFG(TIM14_K, tim14_k, SECF_TIM14),
1349         STM32_GATE_CFG(TIM15_K, tim15_k, SECF_TIM15),
1350         STM32_GATE_CFG(TIM16_K, tim16_k, SECF_TIM16),
1351         STM32_GATE_CFG(TIM17_K, tim17_k, SECF_TIM17),
1352
1353         /* Peripheral clocks */
1354         STM32_GATE_CFG(SAI1, sai1, SECF_NONE),
1355         STM32_GATE_CFG(SAI2, sai2, SECF_NONE),
1356         STM32_GATE_CFG(SYSCFG, syscfg, SECF_NONE),
1357         STM32_GATE_CFG(VREF, vref, SECF_VREF),
1358         STM32_GATE_CFG(DTS, dts, SECF_NONE),
1359         STM32_GATE_CFG(PMBCTRL, pmbctrl, SECF_NONE),
1360         STM32_GATE_CFG(HDP, hdp, SECF_NONE),
1361         STM32_GATE_CFG(IWDG2, iwdg2, SECF_NONE),
1362         STM32_GATE_CFG(STGENRO, stgenro, SECF_STGENRO),
1363         STM32_GATE_CFG(TZPC, tzpc, SECF_TZC),
1364         STM32_GATE_CFG(IWDG1, iwdg1, SECF_IWDG1),
1365         STM32_GATE_CFG(BSEC, bsec, SECF_BSEC),
1366         STM32_GATE_CFG(DMA1, dma1, SECF_NONE),
1367         STM32_GATE_CFG(DMA2, dma2, SECF_NONE),
1368         STM32_GATE_CFG(DMAMUX1, dmamux1, SECF_NONE),
1369         STM32_GATE_CFG(DMA3, dma3, SECF_DMA3),
1370         STM32_GATE_CFG(DMAMUX2, dmamux2, SECF_DMAMUX2),
1371         STM32_GATE_CFG(ADC1, adc1, SECF_ADC1),
1372         STM32_GATE_CFG(ADC2, adc2, SECF_ADC2),
1373         STM32_GATE_CFG(GPIOA, gpioa, SECF_NONE),
1374         STM32_GATE_CFG(GPIOB, gpiob, SECF_NONE),
1375         STM32_GATE_CFG(GPIOC, gpioc, SECF_NONE),
1376         STM32_GATE_CFG(GPIOD, gpiod, SECF_NONE),
1377         STM32_GATE_CFG(GPIOE, gpioe, SECF_NONE),
1378         STM32_GATE_CFG(GPIOF, gpiof, SECF_NONE),
1379         STM32_GATE_CFG(GPIOG, gpiog, SECF_NONE),
1380         STM32_GATE_CFG(GPIOH, gpioh, SECF_NONE),
1381         STM32_GATE_CFG(GPIOI, gpioi, SECF_NONE),
1382         STM32_GATE_CFG(TSC, tsc, SECF_TZC),
1383         STM32_GATE_CFG(PKA, pka, SECF_PKA),
1384         STM32_GATE_CFG(CRYP1, cryp1, SECF_CRYP1),
1385         STM32_GATE_CFG(HASH1, hash1, SECF_HASH1),
1386         STM32_GATE_CFG(BKPSRAM, bkpsram, SECF_BKPSRAM),
1387         STM32_GATE_CFG(MDMA, mdma, SECF_NONE),
1388         STM32_GATE_CFG(ETH1TX, eth1tx, SECF_ETH1TX),
1389         STM32_GATE_CFG(ETH1RX, eth1rx, SECF_ETH1RX),
1390         STM32_GATE_CFG(ETH1MAC, eth1mac, SECF_ETH1MAC),
1391         STM32_GATE_CFG(ETH2TX, eth2tx, SECF_ETH2TX),
1392         STM32_GATE_CFG(ETH2RX, eth2rx, SECF_ETH2RX),
1393         STM32_GATE_CFG(ETH2MAC, eth2mac, SECF_ETH2MAC),
1394         STM32_GATE_CFG(CRC1, crc1, SECF_NONE),
1395         STM32_GATE_CFG(USBH, usbh, SECF_NONE),
1396         STM32_GATE_CFG(DDRPERFM, ddrperfm, SECF_NONE),
1397         STM32_GATE_CFG(ETH1STP, eth1stp, SECF_ETH1STP),
1398         STM32_GATE_CFG(ETH2STP, eth2stp, SECF_ETH2STP),
1399
1400         /* Kernel clocks */
1401         STM32_COMPOSITE_CFG(SDMMC1_K, sdmmc1_k, SECF_SDMMC1),
1402         STM32_COMPOSITE_CFG(SDMMC2_K, sdmmc2_k, SECF_SDMMC2),
1403         STM32_COMPOSITE_CFG(FMC_K, fmc_k, SECF_FMC),
1404         STM32_COMPOSITE_CFG(QSPI_K, qspi_k, SECF_QSPI),
1405         STM32_COMPOSITE_CFG(SPI2_K, spi2_k, SECF_NONE),
1406         STM32_COMPOSITE_CFG(SPI3_K, spi3_k, SECF_NONE),
1407         STM32_COMPOSITE_CFG(I2C1_K, i2c1_k, SECF_NONE),
1408         STM32_COMPOSITE_CFG(I2C2_K, i2c2_k, SECF_NONE),
1409         STM32_COMPOSITE_CFG(LPTIM4_K, lptim4_k, SECF_NONE),
1410         STM32_COMPOSITE_CFG(LPTIM5_K, lptim5_k, SECF_NONE),
1411         STM32_COMPOSITE_CFG(USART3_K, usart3_k, SECF_NONE),
1412         STM32_COMPOSITE_CFG(UART5_K, uart5_k, SECF_NONE),
1413         STM32_COMPOSITE_CFG(UART7_K, uart7_k, SECF_NONE),
1414         STM32_COMPOSITE_CFG(UART8_K, uart8_k, SECF_NONE),
1415         STM32_COMPOSITE_CFG(SAI1_K, sai1_k, SECF_NONE),
1416         STM32_COMPOSITE_CFG(SAI2_K, sai2_k, SECF_NONE),
1417         STM32_COMPOSITE_CFG(ADFSDM_K, adfsdm_k, SECF_NONE),
1418         STM32_COMPOSITE_CFG(ADC1_K, adc1_k, SECF_ADC1),
1419         STM32_COMPOSITE_CFG(ADC2_K, adc2_k, SECF_ADC2),
1420         STM32_COMPOSITE_CFG(RNG1_K, rng1_k, SECF_RNG1),
1421         STM32_COMPOSITE_CFG(USBPHY_K, usbphy_k, SECF_USBPHY),
1422         STM32_COMPOSITE_CFG(STGEN_K, stgen_k, SECF_STGENC),
1423         STM32_COMPOSITE_CFG(SPDIF_K, spdif_k, SECF_NONE),
1424         STM32_COMPOSITE_CFG(SPI1_K, spi1_k, SECF_NONE),
1425         STM32_COMPOSITE_CFG(SPI4_K, spi4_k, SECF_SPI4),
1426         STM32_COMPOSITE_CFG(SPI5_K, spi5_k, SECF_SPI5),
1427         STM32_COMPOSITE_CFG(I2C3_K, i2c3_k, SECF_I2C3),
1428         STM32_COMPOSITE_CFG(I2C4_K, i2c4_k, SECF_I2C4),
1429         STM32_COMPOSITE_CFG(I2C5_K, i2c5_k, SECF_I2C5),
1430         STM32_COMPOSITE_CFG(LPTIM1_K, lptim1_k, SECF_NONE),
1431         STM32_COMPOSITE_CFG(LPTIM2_K, lptim2_k, SECF_LPTIM2),
1432         STM32_COMPOSITE_CFG(LPTIM3_K, lptim3_k, SECF_LPTIM3),
1433         STM32_COMPOSITE_CFG(USART1_K, usart1_k, SECF_USART1),
1434         STM32_COMPOSITE_CFG(USART2_K, usart2_k, SECF_USART2),
1435         STM32_COMPOSITE_CFG(UART4_K, uart4_k, SECF_NONE),
1436         STM32_COMPOSITE_CFG(USART6_K, uart6_k, SECF_NONE),
1437         STM32_COMPOSITE_CFG(FDCAN_K, fdcan_k, SECF_NONE),
1438         STM32_COMPOSITE_CFG(DCMIPP_K, dcmipp_k, SECF_DCMIPP),
1439         STM32_COMPOSITE_CFG(USBO_K, usbo_k, SECF_USBO),
1440         STM32_COMPOSITE_CFG(SAES_K, saes_k, SECF_SAES),
1441         STM32_GATE_CFG(DFSDM_K, dfsdm_k, SECF_NONE),
1442         STM32_GATE_CFG(LTDC_PX, ltdc_px, SECF_NONE),
1443
1444         STM32_MUX_CFG(NO_ID, ck_ker_eth1, SECF_ETH1CK),
1445         STM32_GATE_CFG(ETH1CK_K, eth1ck_k, SECF_ETH1CK),
1446         STM32_DIV_CFG(ETH1PTP_K, eth1ptp_k, SECF_ETH1CK),
1447
1448         STM32_MUX_CFG(NO_ID, ck_ker_eth2, SECF_ETH2CK),
1449         STM32_GATE_CFG(ETH2CK_K, eth2ck_k, SECF_ETH2CK),
1450         STM32_DIV_CFG(ETH2PTP_K, eth2ptp_k, SECF_ETH2CK),
1451
1452         STM32_GATE_CFG(CK_DBG, ck_sys_dbg, SECF_NONE),
1453         STM32_COMPOSITE_CFG(CK_TRACE, ck_trace, SECF_NONE),
1454
1455         STM32_COMPOSITE_CFG(CK_MCO1, ck_mco1, SECF_MCO1),
1456         STM32_COMPOSITE_CFG(CK_MCO2, ck_mco2, SECF_MCO2),
1457 };
1458
1459 static int stm32mp13_clock_is_provided_by_secure(void __iomem *base,
1460                                                  const struct clock_config *cfg)
1461 {
1462         int sec_id = cfg->sec_id;
1463
1464         if (sec_id != SECF_NONE) {
1465                 const struct clk_stm32_securiy *secf;
1466
1467                 secf = &stm32mp13_security[sec_id];
1468
1469                 return !!(readl(base + secf->offset) & BIT(secf->bit_idx));
1470         }
1471
1472         return 0;
1473 }
1474
1475 struct multi_mux {
1476         struct clk_hw *hw1;
1477         struct clk_hw *hw2;
1478 };
1479
1480 static struct multi_mux *stm32_mp13_multi_mux[MUX_NB] = {
1481         [MUX_SPI23]     = &(struct multi_mux){ &spi2_k.hw,      &spi3_k.hw },
1482         [MUX_I2C12]     = &(struct multi_mux){ &i2c1_k.hw,      &i2c2_k.hw },
1483         [MUX_LPTIM45]   = &(struct multi_mux){ &lptim4_k.hw,    &lptim5_k.hw },
1484         [MUX_UART35]    = &(struct multi_mux){ &usart3_k.hw,    &uart5_k.hw },
1485         [MUX_UART78]    = &(struct multi_mux){ &uart7_k.hw,     &uart8_k.hw },
1486         [MUX_SAI1]      = &(struct multi_mux){ &sai1_k.hw,      &adfsdm_k.hw },
1487 };
1488
1489 static struct clk_hw *stm32mp13_is_multi_mux(struct clk_hw *hw)
1490 {
1491         struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
1492         struct multi_mux *mmux = stm32_mp13_multi_mux[composite->mux_id];
1493
1494         if (mmux) {
1495                 if (!(mmux->hw1 == hw))
1496                         return mmux->hw1;
1497                 else
1498                         return mmux->hw2;
1499         }
1500
1501         return NULL;
1502 }
1503
1504 static u16 stm32mp13_cpt_gate[GATE_NB];
1505
1506 static struct clk_stm32_clock_data stm32mp13_clock_data = {
1507         .gate_cpt       = stm32mp13_cpt_gate,
1508         .gates          = stm32mp13_gates,
1509         .muxes          = stm32mp13_muxes,
1510         .dividers       = stm32mp13_dividers,
1511         .is_multi_mux   = stm32mp13_is_multi_mux,
1512 };
1513
1514 static const struct stm32_rcc_match_data stm32mp13_data = {
1515         .tab_clocks     = stm32mp13_clock_cfg,
1516         .num_clocks     = ARRAY_SIZE(stm32mp13_clock_cfg),
1517         .clock_data     = &stm32mp13_clock_data,
1518         .check_security = &stm32mp13_clock_is_provided_by_secure,
1519         .maxbinding     = STM32MP1_LAST_CLK,
1520         .clear_offset   = RCC_CLR_OFFSET,
1521 };
1522
1523 static const struct of_device_id stm32mp13_match_data[] = {
1524         {
1525                 .compatible = "st,stm32mp13-rcc",
1526                 .data = &stm32mp13_data,
1527         },
1528         { }
1529 };
1530 MODULE_DEVICE_TABLE(of, stm32mp13_match_data);
1531
1532 static int stm32mp1_rcc_init(struct device *dev)
1533 {
1534         void __iomem *rcc_base;
1535         int ret = -ENOMEM;
1536
1537         rcc_base = of_iomap(dev_of_node(dev), 0);
1538         if (!rcc_base) {
1539                 dev_err(dev, "%pOFn: unable to map resource", dev_of_node(dev));
1540                 goto out;
1541         }
1542
1543         ret = stm32_rcc_init(dev, stm32mp13_match_data, rcc_base);
1544 out:
1545         if (ret) {
1546                 if (rcc_base)
1547                         iounmap(rcc_base);
1548
1549                 of_node_put(dev_of_node(dev));
1550         }
1551
1552         return ret;
1553 }
1554
1555 static int get_clock_deps(struct device *dev)
1556 {
1557         static const char * const clock_deps_name[] = {
1558                 "hsi", "hse", "csi", "lsi", "lse",
1559         };
1560         size_t deps_size = sizeof(struct clk *) * ARRAY_SIZE(clock_deps_name);
1561         struct clk **clk_deps;
1562         int i;
1563
1564         clk_deps = devm_kzalloc(dev, deps_size, GFP_KERNEL);
1565         if (!clk_deps)
1566                 return -ENOMEM;
1567
1568         for (i = 0; i < ARRAY_SIZE(clock_deps_name); i++) {
1569                 struct clk *clk = of_clk_get_by_name(dev_of_node(dev),
1570                                                      clock_deps_name[i]);
1571
1572                 if (IS_ERR(clk)) {
1573                         if (PTR_ERR(clk) != -EINVAL && PTR_ERR(clk) != -ENOENT)
1574                                 return PTR_ERR(clk);
1575                 } else {
1576                         /* Device gets a reference count on the clock */
1577                         clk_deps[i] = devm_clk_get(dev, __clk_get_name(clk));
1578                         clk_put(clk);
1579                 }
1580         }
1581
1582         return 0;
1583 }
1584
1585 static int stm32mp1_rcc_clocks_probe(struct platform_device *pdev)
1586 {
1587         struct device *dev = &pdev->dev;
1588         int ret = get_clock_deps(dev);
1589
1590         if (!ret)
1591                 ret = stm32mp1_rcc_init(dev);
1592
1593         return ret;
1594 }
1595
1596 static int stm32mp1_rcc_clocks_remove(struct platform_device *pdev)
1597 {
1598         struct device *dev = &pdev->dev;
1599         struct device_node *child, *np = dev_of_node(dev);
1600
1601         for_each_available_child_of_node(np, child)
1602                 of_clk_del_provider(child);
1603
1604         return 0;
1605 }
1606
1607 static struct platform_driver stm32mp13_rcc_clocks_driver = {
1608         .driver = {
1609                 .name = "stm32mp13_rcc",
1610                 .of_match_table = stm32mp13_match_data,
1611         },
1612         .probe = stm32mp1_rcc_clocks_probe,
1613         .remove = stm32mp1_rcc_clocks_remove,
1614 };
1615
1616 static int __init stm32mp13_clocks_init(void)
1617 {
1618         return platform_driver_register(&stm32mp13_rcc_clocks_driver);
1619 }
1620 core_initcall(stm32mp13_clocks_init);