1 // SPDX-License-Identifier: GPL-2.0
3 * StarFive JH7110 PLL Clock Generator Driver
5 * Copyright (C) 2023 StarFive Technology Co., Ltd.
6 * Copyright (C) 2023 Emil Renner Berthing <emil.renner.berthing@canonical.com>
8 * This driver is about to register JH7110 PLL clock generator and support ops.
9 * The JH7110 have three PLL clock, PLL0, PLL1 and PLL2.
10 * Each PLL clocks work in integer mode or fraction mode by some dividers,
11 * and the configuration registers and dividers are set in several syscon registers.
12 * The formula for calculating frequency is:
13 * Fvco = Fref * (NI + NF) / M / Q1
14 * Fref: OSC source clock rate
15 * NI: integer frequency dividing ratio of feedback divider, set by fbdiv[11:0].
16 * NF: fractional frequency dividing ratio, set by frac[23:0]. NF = frac[23:0] / 2^24 = 0 ~ 0.999.
17 * M: frequency dividing ratio of pre-divider, set by prediv[5:0].
18 * Q1: frequency dividing ratio of post divider, set by 2^postdiv1[1:0], eg. 1, 2, 4 or 8.
21 #include <linux/bits.h>
22 #include <linux/clk-provider.h>
23 #include <linux/debugfs.h>
24 #include <linux/device.h>
25 #include <linux/kernel.h>
26 #include <linux/mfd/syscon.h>
27 #include <linux/platform_device.h>
28 #include <linux/regmap.h>
30 #include <dt-bindings/clock/starfive,jh7110-crg.h>
32 /* this driver expects a 24MHz input frequency from the oscillator */
33 #define JH7110_PLL_OSC_RATE 24000000UL
35 #define JH7110_PLL0_PD_OFFSET 0x18
36 #define JH7110_PLL0_DACPD_SHIFT 24
37 #define JH7110_PLL0_DACPD_MASK BIT(24)
38 #define JH7110_PLL0_DSMPD_SHIFT 25
39 #define JH7110_PLL0_DSMPD_MASK BIT(25)
40 #define JH7110_PLL0_FBDIV_OFFSET 0x1c
41 #define JH7110_PLL0_FBDIV_SHIFT 0
42 #define JH7110_PLL0_FBDIV_MASK GENMASK(11, 0)
43 #define JH7110_PLL0_FRAC_OFFSET 0x20
44 #define JH7110_PLL0_PREDIV_OFFSET 0x24
46 #define JH7110_PLL1_PD_OFFSET 0x24
47 #define JH7110_PLL1_DACPD_SHIFT 15
48 #define JH7110_PLL1_DACPD_MASK BIT(15)
49 #define JH7110_PLL1_DSMPD_SHIFT 16
50 #define JH7110_PLL1_DSMPD_MASK BIT(16)
51 #define JH7110_PLL1_FBDIV_OFFSET 0x24
52 #define JH7110_PLL1_FBDIV_SHIFT 17
53 #define JH7110_PLL1_FBDIV_MASK GENMASK(28, 17)
54 #define JH7110_PLL1_FRAC_OFFSET 0x28
55 #define JH7110_PLL1_PREDIV_OFFSET 0x2c
57 #define JH7110_PLL2_PD_OFFSET 0x2c
58 #define JH7110_PLL2_DACPD_SHIFT 15
59 #define JH7110_PLL2_DACPD_MASK BIT(15)
60 #define JH7110_PLL2_DSMPD_SHIFT 16
61 #define JH7110_PLL2_DSMPD_MASK BIT(16)
62 #define JH7110_PLL2_FBDIV_OFFSET 0x2c
63 #define JH7110_PLL2_FBDIV_SHIFT 17
64 #define JH7110_PLL2_FBDIV_MASK GENMASK(28, 17)
65 #define JH7110_PLL2_FRAC_OFFSET 0x30
66 #define JH7110_PLL2_PREDIV_OFFSET 0x34
68 #define JH7110_PLL_FRAC_SHIFT 0
69 #define JH7110_PLL_FRAC_MASK GENMASK(23, 0)
70 #define JH7110_PLL_POSTDIV1_SHIFT 28
71 #define JH7110_PLL_POSTDIV1_MASK GENMASK(29, 28)
72 #define JH7110_PLL_PREDIV_SHIFT 0
73 #define JH7110_PLL_PREDIV_MASK GENMASK(5, 0)
75 enum jh7110_pll_mode {
76 JH7110_PLL_MODE_FRACTION,
77 JH7110_PLL_MODE_INTEGER,
80 struct jh7110_pll_preset {
82 u32 frac; /* frac value should be decimals multiplied by 2^24 */
83 unsigned fbdiv : 12; /* fbdiv value should be 8 to 4095 */
85 unsigned postdiv1 : 2;
89 struct jh7110_pll_info {
91 const struct jh7110_pll_preset *presets;
92 unsigned int npresets;
111 #define _JH7110_PLL(_idx, _name, _presets) \
114 .presets = _presets, \
115 .npresets = ARRAY_SIZE(_presets), \
117 .pd = JH7110_PLL##_idx##_PD_OFFSET, \
118 .fbdiv = JH7110_PLL##_idx##_FBDIV_OFFSET, \
119 .frac = JH7110_PLL##_idx##_FRAC_OFFSET, \
120 .prediv = JH7110_PLL##_idx##_PREDIV_OFFSET, \
123 .dacpd = JH7110_PLL##_idx##_DACPD_MASK, \
124 .dsmpd = JH7110_PLL##_idx##_DSMPD_MASK, \
125 .fbdiv = JH7110_PLL##_idx##_FBDIV_MASK, \
128 .dacpd = JH7110_PLL##_idx##_DACPD_SHIFT, \
129 .dsmpd = JH7110_PLL##_idx##_DSMPD_SHIFT, \
130 .fbdiv = JH7110_PLL##_idx##_FBDIV_SHIFT, \
133 #define JH7110_PLL(idx, name, presets) _JH7110_PLL(idx, name, presets)
135 struct jh7110_pll_data {
140 struct jh7110_pll_priv {
142 struct regmap *regmap;
143 struct jh7110_pll_data pll[JH7110_PLLCLK_END];
146 struct jh7110_pll_regvals {
156 * Because the pll frequency is relatively fixed,
157 * it cannot be set arbitrarily, so it needs a specific configuration.
158 * PLL0 frequency should be multiple of 125MHz (USB frequency).
160 static const struct jh7110_pll_preset jh7110_pll0_presets[] = {
166 .mode = JH7110_PLL_MODE_INTEGER,
172 .mode = JH7110_PLL_MODE_INTEGER,
178 .mode = JH7110_PLL_MODE_INTEGER,
184 .mode = JH7110_PLL_MODE_INTEGER,
190 .mode = JH7110_PLL_MODE_INTEGER,
196 .mode = JH7110_PLL_MODE_INTEGER,
202 .mode = JH7110_PLL_MODE_INTEGER,
208 .mode = JH7110_PLL_MODE_INTEGER,
214 .mode = JH7110_PLL_MODE_INTEGER,
218 static const struct jh7110_pll_preset jh7110_pll1_presets[] = {
224 .mode = JH7110_PLL_MODE_INTEGER,
230 .mode = JH7110_PLL_MODE_INTEGER,
236 .mode = JH7110_PLL_MODE_INTEGER,
242 .mode = JH7110_PLL_MODE_INTEGER,
246 static const struct jh7110_pll_preset jh7110_pll2_presets[] = {
252 .mode = JH7110_PLL_MODE_INTEGER,
258 .mode = JH7110_PLL_MODE_INTEGER,
262 static const struct jh7110_pll_info jh7110_plls[JH7110_PLLCLK_END] = {
263 JH7110_PLL(JH7110_PLLCLK_PLL0_OUT, "pll0_out", jh7110_pll0_presets),
264 JH7110_PLL(JH7110_PLLCLK_PLL1_OUT, "pll1_out", jh7110_pll1_presets),
265 JH7110_PLL(JH7110_PLLCLK_PLL2_OUT, "pll2_out", jh7110_pll2_presets),
268 static struct jh7110_pll_data *jh7110_pll_data_from(struct clk_hw *hw)
270 return container_of(hw, struct jh7110_pll_data, hw);
273 static struct jh7110_pll_priv *jh7110_pll_priv_from(struct jh7110_pll_data *pll)
275 return container_of(pll, struct jh7110_pll_priv, pll[pll->idx]);
278 static void jh7110_pll_regvals_get(struct regmap *regmap,
279 const struct jh7110_pll_info *info,
280 struct jh7110_pll_regvals *ret)
284 regmap_read(regmap, info->offsets.pd, &val);
285 ret->dacpd = (val & info->masks.dacpd) >> info->shifts.dacpd;
286 ret->dsmpd = (val & info->masks.dsmpd) >> info->shifts.dsmpd;
288 regmap_read(regmap, info->offsets.fbdiv, &val);
289 ret->fbdiv = (val & info->masks.fbdiv) >> info->shifts.fbdiv;
291 regmap_read(regmap, info->offsets.frac, &val);
292 ret->frac = (val & JH7110_PLL_FRAC_MASK) >> JH7110_PLL_FRAC_SHIFT;
293 ret->postdiv1 = (val & JH7110_PLL_POSTDIV1_MASK) >> JH7110_PLL_POSTDIV1_SHIFT;
295 regmap_read(regmap, info->offsets.prediv, &val);
296 ret->prediv = (val & JH7110_PLL_PREDIV_MASK) >> JH7110_PLL_PREDIV_SHIFT;
299 static unsigned long jh7110_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
301 struct jh7110_pll_data *pll = jh7110_pll_data_from(hw);
302 struct jh7110_pll_priv *priv = jh7110_pll_priv_from(pll);
303 struct jh7110_pll_regvals val;
306 jh7110_pll_regvals_get(priv->regmap, &jh7110_plls[pll->idx], &val);
309 * dacpd = dsmpd = 0: fraction mode
310 * dacpd = dsmpd = 1: integer mode, frac value ignored
312 * rate = parent * (fbdiv + frac/2^24) / prediv / 2^postdiv1
313 * = (parent * fbdiv + parent * frac / 2^24) / (prediv * 2^postdiv1)
315 if (val.dacpd == 0 && val.dsmpd == 0)
316 rate = parent_rate * val.frac / (1UL << 24);
317 else if (val.dacpd == 1 && val.dsmpd == 1)
322 rate += parent_rate * val.fbdiv;
323 rate /= val.prediv << val.postdiv1;
328 static int jh7110_pll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
330 struct jh7110_pll_data *pll = jh7110_pll_data_from(hw);
331 const struct jh7110_pll_info *info = &jh7110_plls[pll->idx];
332 const struct jh7110_pll_preset *selected = &info->presets[0];
335 /* if the parent rate doesn't match our expectations the presets won't work */
336 if (req->best_parent_rate != JH7110_PLL_OSC_RATE) {
337 req->rate = jh7110_pll_recalc_rate(hw, req->best_parent_rate);
341 /* find highest rate lower or equal to the requested rate */
342 for (idx = 1; idx < info->npresets; idx++) {
343 const struct jh7110_pll_preset *val = &info->presets[idx];
345 if (req->rate < val->freq)
351 req->rate = selected->freq;
355 static int jh7110_pll_set_rate(struct clk_hw *hw, unsigned long rate,
356 unsigned long parent_rate)
358 struct jh7110_pll_data *pll = jh7110_pll_data_from(hw);
359 struct jh7110_pll_priv *priv = jh7110_pll_priv_from(pll);
360 const struct jh7110_pll_info *info = &jh7110_plls[pll->idx];
361 const struct jh7110_pll_preset *val;
364 /* if the parent rate doesn't match our expectations the presets won't work */
365 if (parent_rate != JH7110_PLL_OSC_RATE)
368 for (idx = 0, val = &info->presets[0]; idx < info->npresets; idx++, val++) {
369 if (val->freq == rate)
375 if (val->mode == JH7110_PLL_MODE_FRACTION)
376 regmap_update_bits(priv->regmap, info->offsets.frac, JH7110_PLL_FRAC_MASK,
377 val->frac << JH7110_PLL_FRAC_SHIFT);
379 regmap_update_bits(priv->regmap, info->offsets.pd, info->masks.dacpd,
380 (u32)val->mode << info->shifts.dacpd);
381 regmap_update_bits(priv->regmap, info->offsets.pd, info->masks.dsmpd,
382 (u32)val->mode << info->shifts.dsmpd);
383 regmap_update_bits(priv->regmap, info->offsets.prediv, JH7110_PLL_PREDIV_MASK,
384 (u32)val->prediv << JH7110_PLL_PREDIV_SHIFT);
385 regmap_update_bits(priv->regmap, info->offsets.fbdiv, info->masks.fbdiv,
386 val->fbdiv << info->shifts.fbdiv);
387 regmap_update_bits(priv->regmap, info->offsets.frac, JH7110_PLL_POSTDIV1_MASK,
388 (u32)val->postdiv1 << JH7110_PLL_POSTDIV1_SHIFT);
393 #ifdef CONFIG_DEBUG_FS
394 static int jh7110_pll_registers_read(struct seq_file *s, void *unused)
396 struct jh7110_pll_data *pll = s->private;
397 struct jh7110_pll_priv *priv = jh7110_pll_priv_from(pll);
398 struct jh7110_pll_regvals val;
400 jh7110_pll_regvals_get(priv->regmap, &jh7110_plls[pll->idx], &val);
402 seq_printf(s, "fbdiv=%u\n"
408 val.fbdiv, val.frac, val.prediv, val.postdiv1,
409 val.dacpd, val.dsmpd);
414 static int jh7110_pll_registers_open(struct inode *inode, struct file *f)
416 return single_open(f, jh7110_pll_registers_read, inode->i_private);
419 static const struct file_operations jh7110_pll_registers_ops = {
420 .owner = THIS_MODULE,
421 .open = jh7110_pll_registers_open,
422 .release = single_release,
427 static void jh7110_pll_debug_init(struct clk_hw *hw, struct dentry *dentry)
429 struct jh7110_pll_data *pll = jh7110_pll_data_from(hw);
431 debugfs_create_file("registers", 0400, dentry, pll,
432 &jh7110_pll_registers_ops);
435 #define jh7110_pll_debug_init NULL
438 static const struct clk_ops jh7110_pll_ops = {
439 .recalc_rate = jh7110_pll_recalc_rate,
440 .determine_rate = jh7110_pll_determine_rate,
441 .set_rate = jh7110_pll_set_rate,
442 .debug_init = jh7110_pll_debug_init,
445 static struct clk_hw *jh7110_pll_get(struct of_phandle_args *clkspec, void *data)
447 struct jh7110_pll_priv *priv = data;
448 unsigned int idx = clkspec->args[0];
450 if (idx < JH7110_PLLCLK_END)
451 return &priv->pll[idx].hw;
453 return ERR_PTR(-EINVAL);
456 static int jh7110_pll_probe(struct platform_device *pdev)
458 struct jh7110_pll_priv *priv;
462 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
466 priv->dev = &pdev->dev;
467 priv->regmap = syscon_node_to_regmap(priv->dev->of_node->parent);
468 if (IS_ERR(priv->regmap))
469 return PTR_ERR(priv->regmap);
471 for (idx = 0; idx < JH7110_PLLCLK_END; idx++) {
472 struct clk_parent_data parents = {
475 struct clk_init_data init = {
476 .name = jh7110_plls[idx].name,
477 .ops = &jh7110_pll_ops,
478 .parent_data = &parents,
482 struct jh7110_pll_data *pll = &priv->pll[idx];
484 pll->hw.init = &init;
487 ret = devm_clk_hw_register(&pdev->dev, &pll->hw);
492 return devm_of_clk_add_hw_provider(&pdev->dev, jh7110_pll_get, priv);
495 static const struct of_device_id jh7110_pll_match[] = {
496 { .compatible = "starfive,jh7110-pll" },
499 MODULE_DEVICE_TABLE(of, jh7110_pll_match);
501 static struct platform_driver jh7110_pll_driver = {
503 .name = "clk-starfive-jh7110-pll",
504 .of_match_table = jh7110_pll_match,
507 builtin_platform_driver_probe(jh7110_pll_driver, jh7110_pll_probe);