1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2014 STMicroelectronics (R&D) Limited
8 * Stephen Gallimore <stephen.gallimore@st.com>,
9 * Pankaj Dev <pankaj.dev@st.com>.
12 #include <linux/slab.h>
13 #include <linux/of_address.h>
14 #include <linux/clk.h>
15 #include <linux/clk-provider.h>
16 #include <linux/iopoll.h>
20 static DEFINE_SPINLOCK(clkgena_c32_odf_lock);
21 DEFINE_SPINLOCK(clkgen_a9_lock);
24 * PLL configuration register bits for PLL3200 C32
26 #define C32_NDIV_MASK (0xff)
27 #define C32_IDF_MASK (0x7)
28 #define C32_ODF_MASK (0x3f)
29 #define C32_LDF_MASK (0x7f)
30 #define C32_CP_MASK (0x1f)
32 #define C32_MAX_ODFS (4)
35 * PLL configuration register bits for PLL4600 C28
37 #define C28_NDIV_MASK (0xff)
38 #define C28_IDF_MASK (0x7)
39 #define C28_ODF_MASK (0x3f)
41 struct clkgen_pll_data {
42 struct clkgen_field pdn_status;
43 struct clkgen_field pdn_ctrl;
44 struct clkgen_field locked_status;
45 struct clkgen_field mdiv;
46 struct clkgen_field ndiv;
47 struct clkgen_field pdiv;
48 struct clkgen_field idf;
49 struct clkgen_field ldf;
50 struct clkgen_field cp;
51 unsigned int num_odfs;
52 struct clkgen_field odf[C32_MAX_ODFS];
53 struct clkgen_field odf_gate[C32_MAX_ODFS];
55 struct clkgen_field switch2pll;
57 const struct clk_ops *ops;
60 static const struct clk_ops stm_pll3200c32_ops;
61 static const struct clk_ops stm_pll3200c32_a9_ops;
62 static const struct clk_ops stm_pll4600c28_ops;
64 static const struct clkgen_pll_data st_pll3200c32_cx_0 = {
66 .pdn_status = CLKGEN_FIELD(0x2a0, 0x1, 8),
67 .pdn_ctrl = CLKGEN_FIELD(0x2a0, 0x1, 8),
68 .locked_status = CLKGEN_FIELD(0x2a0, 0x1, 24),
69 .ndiv = CLKGEN_FIELD(0x2a4, C32_NDIV_MASK, 16),
70 .idf = CLKGEN_FIELD(0x2a4, C32_IDF_MASK, 0x0),
72 .odf = { CLKGEN_FIELD(0x2b4, C32_ODF_MASK, 0) },
73 .odf_gate = { CLKGEN_FIELD(0x2b4, 0x1, 6) },
74 .ops = &stm_pll3200c32_ops,
77 static const struct clkgen_pll_data st_pll3200c32_cx_1 = {
79 .pdn_status = CLKGEN_FIELD(0x2c8, 0x1, 8),
80 .pdn_ctrl = CLKGEN_FIELD(0x2c8, 0x1, 8),
81 .locked_status = CLKGEN_FIELD(0x2c8, 0x1, 24),
82 .ndiv = CLKGEN_FIELD(0x2cc, C32_NDIV_MASK, 16),
83 .idf = CLKGEN_FIELD(0x2cc, C32_IDF_MASK, 0x0),
85 .odf = { CLKGEN_FIELD(0x2dc, C32_ODF_MASK, 0) },
86 .odf_gate = { CLKGEN_FIELD(0x2dc, 0x1, 6) },
87 .ops = &stm_pll3200c32_ops,
90 static const struct clkgen_pll_data st_pll3200c32_407_a9 = {
92 .pdn_status = CLKGEN_FIELD(0x1a8, 0x1, 0),
93 .pdn_ctrl = CLKGEN_FIELD(0x1a8, 0x1, 0),
94 .locked_status = CLKGEN_FIELD(0x87c, 0x1, 0),
95 .ndiv = CLKGEN_FIELD(0x1b0, C32_NDIV_MASK, 0),
96 .idf = CLKGEN_FIELD(0x1a8, C32_IDF_MASK, 25),
98 .odf = { CLKGEN_FIELD(0x1b0, C32_ODF_MASK, 8) },
99 .odf_gate = { CLKGEN_FIELD(0x1ac, 0x1, 28) },
100 .switch2pll_en = true,
101 .cp = CLKGEN_FIELD(0x1a8, C32_CP_MASK, 1),
102 .switch2pll = CLKGEN_FIELD(0x1a4, 0x1, 1),
103 .lock = &clkgen_a9_lock,
104 .ops = &stm_pll3200c32_a9_ops,
107 static struct clkgen_pll_data st_pll4600c28_418_a9 = {
109 .pdn_status = CLKGEN_FIELD(0x1a8, 0x1, 0),
110 .pdn_ctrl = CLKGEN_FIELD(0x1a8, 0x1, 0),
111 .locked_status = CLKGEN_FIELD(0x87c, 0x1, 0),
112 .ndiv = CLKGEN_FIELD(0x1b0, C28_NDIV_MASK, 0),
113 .idf = CLKGEN_FIELD(0x1a8, C28_IDF_MASK, 25),
115 .odf = { CLKGEN_FIELD(0x1b0, C28_ODF_MASK, 8) },
116 .odf_gate = { CLKGEN_FIELD(0x1ac, 0x1, 28) },
117 .switch2pll_en = true,
118 .switch2pll = CLKGEN_FIELD(0x1a4, 0x1, 1),
119 .lock = &clkgen_a9_lock,
120 .ops = &stm_pll4600c28_ops,
124 * DOC: Clock Generated by PLL, rate set and enabled by bootloader
126 * Traits of this clock:
127 * prepare - clk_(un)prepare only ensures parent is (un)prepared
128 * enable - clk_enable/disable only ensures parent is enabled
129 * rate - rate is fixed. No clk_set_rate support
130 * parent - fixed parent. No clk_set_parent support
134 * PLL clock that is integrated in the ClockGenA instances on the STiH415
137 * @hw: handle between common and hardware-specific interfaces.
138 * @type: PLL instance type.
139 * @regs_base: base of the PLL configuration register(s).
144 struct clkgen_pll_data *data;
145 void __iomem *regs_base;
154 #define to_clkgen_pll(_hw) container_of(_hw, struct clkgen_pll, hw)
166 static int clkgen_pll_is_locked(struct clk_hw *hw)
168 struct clkgen_pll *pll = to_clkgen_pll(hw);
169 u32 locked = CLKGEN_READ(pll, locked_status);
174 static int clkgen_pll_is_enabled(struct clk_hw *hw)
176 struct clkgen_pll *pll = to_clkgen_pll(hw);
177 u32 poweroff = CLKGEN_READ(pll, pdn_status);
181 static int __clkgen_pll_enable(struct clk_hw *hw)
183 struct clkgen_pll *pll = to_clkgen_pll(hw);
184 void __iomem *base = pll->regs_base;
185 struct clkgen_field *field = &pll->data->locked_status;
189 if (clkgen_pll_is_enabled(hw))
192 CLKGEN_WRITE(pll, pdn_ctrl, 0);
194 ret = readl_relaxed_poll_timeout(base + field->offset, reg,
195 !!((reg >> field->shift) & field->mask), 0, 10000);
198 if (pll->data->switch2pll_en)
199 CLKGEN_WRITE(pll, switch2pll, 0);
201 pr_debug("%s:%s enabled\n", __clk_get_name(hw->clk), __func__);
207 static int clkgen_pll_enable(struct clk_hw *hw)
209 struct clkgen_pll *pll = to_clkgen_pll(hw);
210 unsigned long flags = 0;
214 spin_lock_irqsave(pll->lock, flags);
216 ret = __clkgen_pll_enable(hw);
219 spin_unlock_irqrestore(pll->lock, flags);
224 static void __clkgen_pll_disable(struct clk_hw *hw)
226 struct clkgen_pll *pll = to_clkgen_pll(hw);
228 if (!clkgen_pll_is_enabled(hw))
231 if (pll->data->switch2pll_en)
232 CLKGEN_WRITE(pll, switch2pll, 1);
234 CLKGEN_WRITE(pll, pdn_ctrl, 1);
236 pr_debug("%s:%s disabled\n", __clk_get_name(hw->clk), __func__);
239 static void clkgen_pll_disable(struct clk_hw *hw)
241 struct clkgen_pll *pll = to_clkgen_pll(hw);
242 unsigned long flags = 0;
245 spin_lock_irqsave(pll->lock, flags);
247 __clkgen_pll_disable(hw);
250 spin_unlock_irqrestore(pll->lock, flags);
253 static int clk_pll3200c32_get_params(unsigned long input, unsigned long output,
257 unsigned long deviation = ~0;
258 unsigned long new_freq;
260 /* Charge pump table: highest ndiv value for cp=6 to 25 */
261 static const unsigned char cp_table[] = {
262 48, 56, 64, 72, 80, 88, 96, 104, 112, 120,
263 128, 136, 144, 152, 160, 168, 176, 184, 192
266 /* Output clock range: 800Mhz to 1600Mhz */
267 if (output < 800000000 || output > 1600000000)
273 for (i = 1; i <= 7 && deviation; i++) {
274 n = i * output / (2 * input);
282 new_freq = (input * 2 * n) / i;
284 new_deviation = abs(new_freq - output);
286 if (!new_deviation || new_deviation < deviation) {
289 deviation = new_deviation;
293 if (deviation == ~0) /* No solution found */
296 /* Computing recommended charge pump value */
297 for (pll->cp = 6; pll->ndiv > cp_table[pll->cp-6]; (pll->cp)++)
303 static int clk_pll3200c32_get_rate(unsigned long input, struct stm_pll *pll,
309 *rate = ((2 * (input / 1000) * pll->ndiv) / pll->idf) * 1000;
314 static unsigned long recalc_stm_pll3200c32(struct clk_hw *hw,
315 unsigned long parent_rate)
317 struct clkgen_pll *pll = to_clkgen_pll(hw);
318 unsigned long ndiv, idf;
319 unsigned long rate = 0;
321 if (!clkgen_pll_is_enabled(hw) || !clkgen_pll_is_locked(hw))
324 ndiv = CLKGEN_READ(pll, ndiv);
325 idf = CLKGEN_READ(pll, idf);
328 /* Note: input is divided to avoid overflow */
329 rate = ((2 * (parent_rate/1000) * ndiv) / idf) * 1000;
331 pr_debug("%s:%s rate %lu\n", clk_hw_get_name(hw), __func__, rate);
336 static long round_rate_stm_pll3200c32(struct clk_hw *hw, unsigned long rate,
337 unsigned long *prate)
339 struct stm_pll params;
341 if (!clk_pll3200c32_get_params(*prate, rate, ¶ms))
342 clk_pll3200c32_get_rate(*prate, ¶ms, &rate);
344 pr_debug("%s: %s rate %ld Invalid\n", __func__,
345 __clk_get_name(hw->clk), rate);
349 pr_debug("%s: %s new rate %ld [ndiv=%u] [idf=%u]\n",
350 __func__, __clk_get_name(hw->clk),
351 rate, (unsigned int)params.ndiv,
352 (unsigned int)params.idf);
357 static int set_rate_stm_pll3200c32(struct clk_hw *hw, unsigned long rate,
358 unsigned long parent_rate)
360 struct clkgen_pll *pll = to_clkgen_pll(hw);
361 struct stm_pll params;
363 unsigned long flags = 0;
365 if (!rate || !parent_rate)
368 if (!clk_pll3200c32_get_params(parent_rate, rate, ¶ms))
369 clk_pll3200c32_get_rate(parent_rate, ¶ms, &hwrate);
371 pr_debug("%s: %s new rate %ld [ndiv=0x%x] [idf=0x%x]\n",
372 __func__, __clk_get_name(hw->clk),
373 hwrate, (unsigned int)params.ndiv,
374 (unsigned int)params.idf);
379 pll->ndiv = params.ndiv;
380 pll->idf = params.idf;
383 __clkgen_pll_disable(hw);
386 spin_lock_irqsave(pll->lock, flags);
388 CLKGEN_WRITE(pll, ndiv, pll->ndiv);
389 CLKGEN_WRITE(pll, idf, pll->idf);
390 CLKGEN_WRITE(pll, cp, pll->cp);
393 spin_unlock_irqrestore(pll->lock, flags);
395 __clkgen_pll_enable(hw);
400 /* PLL output structure
401 * FVCO >> /2 >> FVCOBY2 (no output)
402 * |> Divider (ODF) >> PHI
404 * FVCOby2 output = (input * 2 * NDIV) / IDF (assuming FRAC_CONTROL==L)
407 * 4Mhz <= INFF input <= 350Mhz
408 * 4Mhz <= INFIN (INFF / IDF) <= 50Mhz
409 * 19.05Mhz <= FVCOby2 output (PHI w ODF=1) <= 3000Mhz
410 * 1 <= i (register/dec value for IDF) <= 7
411 * 8 <= n (register/dec value for NDIV) <= 246
414 static int clk_pll4600c28_get_params(unsigned long input, unsigned long output,
418 unsigned long i, infin, n;
419 unsigned long deviation = ~0;
420 unsigned long new_freq, new_deviation;
422 /* Output clock range: 19Mhz to 3000Mhz */
423 if (output < 19000000 || output > 3000000000u)
426 /* For better jitter, IDF should be smallest and NDIV must be maximum */
427 for (i = 1; i <= 7 && deviation; i++) {
430 if (infin < 4000000 || infin > 50000000)
431 continue; /* Invalid case */
433 n = output / (infin * 2);
434 if (n < 8 || n > 246)
435 continue; /* Invalid case */
437 n++; /* To work around 'y' when n=x.y */
439 for (; n >= 8 && deviation; n--) {
440 new_freq = infin * 2 * n;
441 if (new_freq < output)
442 break; /* Optimization: shorting loop */
444 new_deviation = new_freq - output;
445 if (!new_deviation || new_deviation < deviation) {
448 deviation = new_deviation;
453 if (deviation == ~0) /* No solution found */
459 static int clk_pll4600c28_get_rate(unsigned long input, struct stm_pll *pll,
465 *rate = (input / pll->idf) * 2 * pll->ndiv;
470 static unsigned long recalc_stm_pll4600c28(struct clk_hw *hw,
471 unsigned long parent_rate)
473 struct clkgen_pll *pll = to_clkgen_pll(hw);
474 struct stm_pll params;
477 if (!clkgen_pll_is_enabled(hw) || !clkgen_pll_is_locked(hw))
480 params.ndiv = CLKGEN_READ(pll, ndiv);
481 params.idf = CLKGEN_READ(pll, idf);
483 clk_pll4600c28_get_rate(parent_rate, ¶ms, &rate);
485 pr_debug("%s:%s rate %lu\n", __clk_get_name(hw->clk), __func__, rate);
490 static long round_rate_stm_pll4600c28(struct clk_hw *hw, unsigned long rate,
491 unsigned long *prate)
493 struct stm_pll params;
495 if (!clk_pll4600c28_get_params(*prate, rate, ¶ms)) {
496 clk_pll4600c28_get_rate(*prate, ¶ms, &rate);
498 pr_debug("%s: %s rate %ld Invalid\n", __func__,
499 __clk_get_name(hw->clk), rate);
503 pr_debug("%s: %s new rate %ld [ndiv=%u] [idf=%u]\n",
504 __func__, __clk_get_name(hw->clk),
505 rate, (unsigned int)params.ndiv,
506 (unsigned int)params.idf);
511 static int set_rate_stm_pll4600c28(struct clk_hw *hw, unsigned long rate,
512 unsigned long parent_rate)
514 struct clkgen_pll *pll = to_clkgen_pll(hw);
515 struct stm_pll params;
517 unsigned long flags = 0;
519 if (!rate || !parent_rate)
522 if (!clk_pll4600c28_get_params(parent_rate, rate, ¶ms)) {
523 clk_pll4600c28_get_rate(parent_rate, ¶ms, &hwrate);
525 pr_debug("%s: %s rate %ld Invalid\n", __func__,
526 __clk_get_name(hw->clk), rate);
530 pr_debug("%s: %s new rate %ld [ndiv=0x%x] [idf=0x%x]\n",
531 __func__, __clk_get_name(hw->clk),
532 hwrate, (unsigned int)params.ndiv,
533 (unsigned int)params.idf);
538 pll->ndiv = params.ndiv;
539 pll->idf = params.idf;
541 __clkgen_pll_disable(hw);
544 spin_lock_irqsave(pll->lock, flags);
546 CLKGEN_WRITE(pll, ndiv, pll->ndiv);
547 CLKGEN_WRITE(pll, idf, pll->idf);
550 spin_unlock_irqrestore(pll->lock, flags);
552 __clkgen_pll_enable(hw);
557 static const struct clk_ops stm_pll3200c32_ops = {
558 .enable = clkgen_pll_enable,
559 .disable = clkgen_pll_disable,
560 .is_enabled = clkgen_pll_is_enabled,
561 .recalc_rate = recalc_stm_pll3200c32,
564 static const struct clk_ops stm_pll3200c32_a9_ops = {
565 .enable = clkgen_pll_enable,
566 .disable = clkgen_pll_disable,
567 .is_enabled = clkgen_pll_is_enabled,
568 .recalc_rate = recalc_stm_pll3200c32,
569 .round_rate = round_rate_stm_pll3200c32,
570 .set_rate = set_rate_stm_pll3200c32,
573 static const struct clk_ops stm_pll4600c28_ops = {
574 .enable = clkgen_pll_enable,
575 .disable = clkgen_pll_disable,
576 .is_enabled = clkgen_pll_is_enabled,
577 .recalc_rate = recalc_stm_pll4600c28,
578 .round_rate = round_rate_stm_pll4600c28,
579 .set_rate = set_rate_stm_pll4600c28,
582 static struct clk * __init clkgen_pll_register(const char *parent_name,
583 struct clkgen_pll_data *pll_data,
584 void __iomem *reg, unsigned long pll_flags,
585 const char *clk_name, spinlock_t *lock)
587 struct clkgen_pll *pll;
589 struct clk_init_data init;
591 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
593 return ERR_PTR(-ENOMEM);
595 init.name = clk_name;
596 init.ops = pll_data->ops;
598 init.flags = pll_flags | CLK_GET_RATE_NOCACHE;
599 init.parent_names = &parent_name;
600 init.num_parents = 1;
602 pll->data = pll_data;
603 pll->regs_base = reg;
604 pll->hw.init = &init;
607 clk = clk_register(NULL, &pll->hw);
613 pr_debug("%s: parent %s rate %lu\n",
615 __clk_get_name(clk_get_parent(clk)),
621 static void __iomem * __init clkgen_get_register_base(
622 struct device_node *np)
624 struct device_node *pnode;
625 void __iomem *reg = NULL;
627 pnode = of_get_parent(np);
631 reg = of_iomap(pnode, 0);
637 static struct clk * __init clkgen_odf_register(const char *parent_name,
639 struct clkgen_pll_data *pll_data,
640 unsigned long pll_flags, int odf,
641 spinlock_t *odf_lock,
642 const char *odf_name)
646 struct clk_gate *gate;
647 struct clk_divider *div;
649 flags = pll_flags | CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT;
651 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
653 return ERR_PTR(-ENOMEM);
655 gate->flags = CLK_GATE_SET_TO_DISABLE;
656 gate->reg = reg + pll_data->odf_gate[odf].offset;
657 gate->bit_idx = pll_data->odf_gate[odf].shift;
658 gate->lock = odf_lock;
660 div = kzalloc(sizeof(*div), GFP_KERNEL);
663 return ERR_PTR(-ENOMEM);
666 div->flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO;
667 div->reg = reg + pll_data->odf[odf].offset;
668 div->shift = pll_data->odf[odf].shift;
669 div->width = fls(pll_data->odf[odf].mask);
670 div->lock = odf_lock;
672 clk = clk_register_composite(NULL, odf_name, &parent_name, 1,
674 &div->hw, &clk_divider_ops,
675 &gate->hw, &clk_gate_ops,
680 pr_debug("%s: parent %s rate %lu\n",
682 __clk_get_name(clk_get_parent(clk)),
688 static void __init clkgen_c32_pll_setup(struct device_node *np,
689 struct clkgen_pll_data *data)
692 const char *parent_name, *pll_name;
693 void __iomem *pll_base;
695 struct clk_onecell_data *clk_data;
696 unsigned long pll_flags = 0;
699 parent_name = of_clk_get_parent_name(np, 0);
703 pll_base = clkgen_get_register_base(np);
707 of_clk_detect_critical(np, 0, &pll_flags);
709 clk = clkgen_pll_register(parent_name, data, pll_base, pll_flags,
710 np->name, data->lock);
714 pll_name = __clk_get_name(clk);
716 num_odfs = data->num_odfs;
718 clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
722 clk_data->clk_num = num_odfs;
723 clk_data->clks = kcalloc(clk_data->clk_num, sizeof(struct clk *),
729 for (odf = 0; odf < num_odfs; odf++) {
731 const char *clk_name;
732 unsigned long odf_flags = 0;
734 if (of_property_read_string_index(np, "clock-output-names",
738 of_clk_detect_critical(np, odf, &odf_flags);
740 clk = clkgen_odf_register(pll_name, pll_base, data, odf_flags,
741 odf, &clkgena_c32_odf_lock, clk_name);
745 clk_data->clks[odf] = clk;
748 of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
753 kfree(clk_data->clks);
756 static void __init clkgen_c32_pll0_setup(struct device_node *np)
758 clkgen_c32_pll_setup(np,
759 (struct clkgen_pll_data *) &st_pll3200c32_cx_0);
761 CLK_OF_DECLARE(c32_pll0, "st,clkgen-pll0", clkgen_c32_pll0_setup);
763 static void __init clkgen_c32_pll1_setup(struct device_node *np)
765 clkgen_c32_pll_setup(np,
766 (struct clkgen_pll_data *) &st_pll3200c32_cx_1);
768 CLK_OF_DECLARE(c32_pll1, "st,clkgen-pll1", clkgen_c32_pll1_setup);
770 static void __init clkgen_c32_plla9_setup(struct device_node *np)
772 clkgen_c32_pll_setup(np,
773 (struct clkgen_pll_data *) &st_pll3200c32_407_a9);
775 CLK_OF_DECLARE(c32_plla9, "st,stih407-clkgen-plla9", clkgen_c32_plla9_setup);
777 static void __init clkgen_c28_plla9_setup(struct device_node *np)
779 clkgen_c32_pll_setup(np,
780 (struct clkgen_pll_data *) &st_pll4600c28_418_a9);
782 CLK_OF_DECLARE(c28_plla9, "st,stih418-clkgen-plla9", clkgen_c28_plla9_setup);