drivers/clk/sprd/ums512-clk.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Unisoc UMS512 clock driver
   4  *
   5  * Copyright (C) 2022 Unisoc, Inc.
   6  * Author: Xiaolong Zhang <xiaolong.zhang@unisoc.com>
   7  */
   8
   9 #include <linux/clk-provider.h>
  10 #include <linux/err.h>
  11 #include <linux/io.h>
  12 #include <linux/mod_devicetable.h>
  13 #include <linux/module.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/slab.h>
  16
  17 #include <dt-bindings/clock/sprd,ums512-clk.h>
  18
  19 #include "common.h"
  20 #include "composite.h"
  21 #include "div.h"
  22 #include "gate.h"
  23 #include "mux.h"
  24 #include "pll.h"
  25
  26 #define UMS512_MUX_FLAG \
  27         (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_NO_REPARENT)
  28
  29 /* pll gate clock */
  30 /* some pll clocks configure CLK_IGNORE_UNUSED because hw dvfs does not call
  31  * clock interface. hw dvfs can not gate the pll clock.
  32  */
  33 static CLK_FIXED_FACTOR_FW_NAME(clk_26m_aud, "clk-26m-aud", "ext-26m", 1, 1, 0);
  34 static CLK_FIXED_FACTOR_FW_NAME(clk_13m, "clk-13m", "ext-26m", 2, 1, 0);
  35 static CLK_FIXED_FACTOR_FW_NAME(clk_6m5, "clk-6m5", "ext-26m", 4, 1, 0);
  36 static CLK_FIXED_FACTOR_FW_NAME(clk_4m3, "clk-4m3", "ext-26m", 6, 1, 0);
  37 static CLK_FIXED_FACTOR_FW_NAME(clk_2m, "clk-2m", "ext-26m", 13, 1, 0);
  38 static CLK_FIXED_FACTOR_FW_NAME(clk_1m, "clk-1m", "ext-26m", 26, 1, 0);
  39 static CLK_FIXED_FACTOR_FW_NAME(clk_250k, "clk-250k", "ext-26m", 104, 1, 0);
  40 static CLK_FIXED_FACTOR_FW_NAME(rco_25m, "rco-25m", "rco-100m", 4, 1, 0);
  41 static CLK_FIXED_FACTOR_FW_NAME(rco_4m, "rco-4m", "rco-100m", 25, 1, 0);
  42 static CLK_FIXED_FACTOR_FW_NAME(rco_2m, "rco-2m", "rco-100m", 50, 1, 0);
  43 static SPRD_PLL_SC_GATE_CLK_FW_NAME(isppll_gate, "isppll-gate", "ext-26m", 0x8c,
  44                                     0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240);
  45 static SPRD_PLL_SC_GATE_CLK_FW_NAME(dpll0_gate, "dpll0-gate", "ext-26m", 0x98,
  46                                     0x1000, BIT(0), 0, 0, 240);
  47 static SPRD_PLL_SC_GATE_CLK_FW_NAME(dpll1_gate, "dpll1-gate", "ext-26m", 0x9c,
  48                                     0x1000, BIT(0), 0, 0, 240);
  49 static SPRD_PLL_SC_GATE_CLK_FW_NAME(lpll_gate, "lpll-gate", "ext-26m", 0xa0,
  50                                     0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240);
  51 static SPRD_PLL_SC_GATE_CLK_FW_NAME(twpll_gate, "twpll-gate", "ext-26m", 0xa4,
  52                                     0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240);
  53 static SPRD_PLL_SC_GATE_CLK_FW_NAME(gpll_gate, "gpll-gate", "ext-26m", 0xa8,
  54                                     0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240);
  55 static SPRD_PLL_SC_GATE_CLK_FW_NAME(rpll_gate, "rpll-gate", "ext-26m", 0xac,
  56                                     0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240);
  57 static SPRD_PLL_SC_GATE_CLK_FW_NAME(cppll_gate, "cppll-gate", "ext-26m", 0xe4,
  58                                     0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240);
  59 static SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll0_gate, "mpll0-gate", "ext-26m", 0x190,
  60                                     0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240);
  61 static SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll1_gate, "mpll1-gate", "ext-26m", 0x194,
  62                                     0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240);
  63 static SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll2_gate, "mpll2-gate", "ext-26m", 0x198,
  64                                     0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240);
  65
  66 static struct sprd_clk_common *ums512_pmu_gate_clks[] = {
  67         /* address base is 0x327e0000 */
  68         &isppll_gate.common,
  69         &dpll0_gate.common,
  70         &dpll1_gate.common,
  71         &lpll_gate.common,
  72         &twpll_gate.common,
  73         &gpll_gate.common,
  74         &rpll_gate.common,
  75         &cppll_gate.common,
  76         &mpll0_gate.common,
  77         &mpll1_gate.common,
  78         &mpll2_gate.common,
  79 };
  80
  81 static struct clk_hw_onecell_data ums512_pmu_gate_hws = {
  82         .hws    = {
  83                 [CLK_26M_AUD]           = &clk_26m_aud.hw,
  84                 [CLK_13M]               = &clk_13m.hw,
  85                 [CLK_6M5]               = &clk_6m5.hw,
  86                 [CLK_4M3]               = &clk_4m3.hw,
  87                 [CLK_2M]                = &clk_2m.hw,
  88                 [CLK_1M]                = &clk_1m.hw,
  89                 [CLK_250K]              = &clk_250k.hw,
  90                 [CLK_RCO_25M]           = &rco_25m.hw,
  91                 [CLK_RCO_4M]            = &rco_4m.hw,
  92                 [CLK_RCO_2M]            = &rco_2m.hw,
  93                 [CLK_ISPPLL_GATE]       = &isppll_gate.common.hw,
  94                 [CLK_DPLL0_GATE]        = &dpll0_gate.common.hw,
  95                 [CLK_DPLL1_GATE]        = &dpll1_gate.common.hw,
  96                 [CLK_LPLL_GATE]         = &lpll_gate.common.hw,
  97                 [CLK_TWPLL_GATE]        = &twpll_gate.common.hw,
  98                 [CLK_GPLL_GATE]         = &gpll_gate.common.hw,
  99                 [CLK_RPLL_GATE]         = &rpll_gate.common.hw,
 100                 [CLK_CPPLL_GATE]        = &cppll_gate.common.hw,
 101                 [CLK_MPLL0_GATE]        = &mpll0_gate.common.hw,
 102                 [CLK_MPLL1_GATE]        = &mpll1_gate.common.hw,
 103                 [CLK_MPLL2_GATE]        = &mpll2_gate.common.hw,
 104         },
 105         .num = CLK_PMU_GATE_NUM,
 106 };
 107
 108 static struct sprd_clk_desc ums512_pmu_gate_desc = {
 109         .clk_clks       = ums512_pmu_gate_clks,
 110         .num_clk_clks   = ARRAY_SIZE(ums512_pmu_gate_clks),
 111         .hw_clks        = &ums512_pmu_gate_hws,
 112 };
 113
 114 /* pll clock at g0 */
 115 static const u64 itable_dpll0[7] = { 6, 0, 0,
 116                         1173000000ULL, 1475000000ULL,
 117                         1855000000ULL, 1866000000ULL };
 118
 119 static struct clk_bit_field f_dpll0[PLL_FACT_MAX] = {
 120         { .shift = 18,  .width = 1 },   /* lock_done    */
 121         { .shift = 0,   .width = 1 },   /* div_s        */
 122         { .shift = 67,  .width = 1 },   /* mod_en       */
 123         { .shift = 1,   .width = 1 },   /* sdm_en       */
 124         { .shift = 0,   .width = 0 },   /* refin        */
 125         { .shift = 4,   .width = 3 },   /* icp          */
 126         { .shift = 7,   .width = 11 },  /* n            */
 127         { .shift = 55,  .width = 7 },   /* nint         */
 128         { .shift = 32,  .width = 23},   /* kint         */
 129         { .shift = 0,   .width = 0 },   /* prediv       */
 130         { .shift = 0,   .width = 0 },   /* postdiv      */
 131 };
 132 static SPRD_PLL_HW(dpll0, "dpll0", &dpll0_gate.common.hw, 0x4, 3,
 133                    itable_dpll0, f_dpll0, 240, 1000, 1000, 0, 0);
 134 static CLK_FIXED_FACTOR_HW(dpll0_58m31, "dpll0-58m31", &dpll0.common.hw,
 135                            32, 1, 0);
 136
 137 static struct sprd_clk_common *ums512_g0_pll_clks[] = {
 138         /* address base is 0x32390000 */
 139         &dpll0.common,
 140 };
 141
 142 static struct clk_hw_onecell_data ums512_g0_pll_hws = {
 143         .hws    = {
 144                 [CLK_DPLL0]             = &dpll0.common.hw,
 145                 [CLK_DPLL0_58M31]       = &dpll0_58m31.hw,
 146         },
 147         .num    = CLK_ANLG_PHY_G0_NUM,
 148 };
 149
 150 static struct sprd_clk_desc ums512_g0_pll_desc = {
 151         .clk_clks       = ums512_g0_pll_clks,
 152         .num_clk_clks   = ARRAY_SIZE(ums512_g0_pll_clks),
 153         .hw_clks        = &ums512_g0_pll_hws,
 154 };
 155
 156 /* pll clock at g2 */
 157 static const u64 itable_mpll[8] = { 7, 0,
 158                         1400000000ULL, 1600000000ULL,
 159                         1800000000ULL, 2000000000ULL,
 160                         2200000000ULL, 2500000000ULL };
 161
 162 static struct clk_bit_field f_mpll[PLL_FACT_MAX] = {
 163         { .shift = 17,  .width = 1 },   /* lock_done    */
 164         { .shift = 0,   .width = 1 },   /* div_s        */
 165         { .shift = 67,  .width = 1 },   /* mod_en       */
 166         { .shift = 1,   .width = 1 },   /* sdm_en       */
 167         { .shift = 0,   .width = 0 },   /* refin        */
 168         { .shift = 2,   .width = 3 },   /* icp          */
 169         { .shift = 5,   .width = 11 },  /* n            */
 170         { .shift = 55,  .width = 7 },   /* nint         */
 171         { .shift = 32,  .width = 23},   /* kint         */
 172         { .shift = 0,   .width = 0 },   /* prediv       */
 173         { .shift = 77,  .width = 1 },   /* postdiv      */
 174 };
 175 static SPRD_PLL_HW(mpll1, "mpll1", &mpll1_gate.common.hw, 0x0, 3,
 176                    itable_mpll, f_mpll, 240, 1000, 1000, 1, 1200000000);
 177 static CLK_FIXED_FACTOR_HW(mpll1_63m38, "mpll1-63m38", &mpll1.common.hw,
 178                            32, 1, 0);
 179
 180 static struct sprd_clk_common *ums512_g2_pll_clks[] = {
 181         /* address base is 0x323B0000 */
 182         &mpll1.common,
 183 };
 184
 185 static struct clk_hw_onecell_data ums512_g2_pll_hws = {
 186         .hws    = {
 187                 [CLK_MPLL1]             = &mpll1.common.hw,
 188                 [CLK_MPLL1_63M38]       = &mpll1_63m38.hw,
 189         },
 190         .num    = CLK_ANLG_PHY_G2_NUM,
 191 };
 192
 193 static struct sprd_clk_desc ums512_g2_pll_desc = {
 194         .clk_clks       = ums512_g2_pll_clks,
 195         .num_clk_clks   = ARRAY_SIZE(ums512_g2_pll_clks),
 196         .hw_clks        = &ums512_g2_pll_hws,
 197 };
 198
 199 /* pll at g3 */
 200 static const u64 itable[8] = { 7, 0, 0,
 201                         900000000ULL, 1100000000ULL,
 202                         1300000000ULL, 1500000000ULL,
 203                         1600000000ULL };
 204
 205 static struct clk_bit_field f_pll[PLL_FACT_MAX] = {
 206         { .shift = 18,  .width = 1 },   /* lock_done    */
 207         { .shift = 0,   .width = 1 },   /* div_s        */
 208         { .shift = 67,  .width = 1 },   /* mod_en       */
 209         { .shift = 1,   .width = 1 },   /* sdm_en       */
 210         { .shift = 0,   .width = 0 },   /* refin        */
 211         { .shift = 2,   .width = 3 },   /* icp          */
 212         { .shift = 5,   .width = 11 },  /* n            */
 213         { .shift = 55,  .width = 7 },   /* nint         */
 214         { .shift = 32,  .width = 23},   /* kint         */
 215         { .shift = 0,   .width = 0 },   /* prediv       */
 216         { .shift = 77,  .width = 1 },   /* postdiv      */
 217 };
 218
 219 static SPRD_PLL_FW_NAME(rpll, "rpll", "ext-26m", 0x0, 3,
 220                         itable, f_pll, 240, 1000, 1000, 1, 750000000);
 221
 222 static SPRD_SC_GATE_CLK_FW_NAME(audio_gate, "audio-gate", "ext-26m", 0x24,
 223                                 0x1000, BIT(1), CLK_IGNORE_UNUSED, 0);
 224
 225 static struct clk_bit_field f_mpll2[PLL_FACT_MAX] = {
 226         { .shift = 16,  .width = 1 },   /* lock_done    */
 227         { .shift = 0,   .width = 1 },   /* div_s        */
 228         { .shift = 67,  .width = 1 },   /* mod_en       */
 229         { .shift = 1,   .width = 1 },   /* sdm_en       */
 230         { .shift = 0,   .width = 0 },   /* refin        */
 231         { .shift = 2,   .width = 3 },   /* icp          */
 232         { .shift = 5,   .width = 11 },  /* n            */
 233         { .shift = 55,  .width = 7 },   /* nint         */
 234         { .shift = 32,  .width = 23},   /* kint         */
 235         { .shift = 0,   .width = 0 },   /* prediv       */
 236         { .shift = 77,  .width = 1 },   /* postdiv      */
 237 };
 238 static SPRD_PLL_HW(mpll0, "mpll0", &mpll0_gate.common.hw, 0x54, 3,
 239                    itable_mpll, f_mpll, 240, 1000, 1000, 1, 1200000000);
 240 static CLK_FIXED_FACTOR_HW(mpll0_56m88, "mpll0-56m88", &mpll0.common.hw,
 241                            32, 1, 0);
 242
 243 static const u64 itable_mpll2[6] = { 5,
 244                         1200000000ULL, 1400000000ULL,
 245                         1600000000ULL, 1800000000ULL,
 246                         2000000000ULL };
 247
 248 static SPRD_PLL_HW(mpll2, "mpll2", &mpll2_gate.common.hw, 0x9c, 3,
 249                    itable_mpll2, f_mpll2, 240, 1000, 1000, 1, 1000000000);
 250 static CLK_FIXED_FACTOR_HW(mpll2_47m13, "mpll2-47m13", &mpll2.common.hw,
 251                            32, 1, 0);
 252
 253 static struct sprd_clk_common *ums512_g3_pll_clks[] = {
 254         /* address base is 0x323c0000 */
 255         &rpll.common,
 256         &audio_gate.common,
 257         &mpll0.common,
 258         &mpll2.common,
 259 };
 260
 261 static struct clk_hw_onecell_data ums512_g3_pll_hws = {
 262         .hws    = {
 263                 [CLK_RPLL]              = &rpll.common.hw,
 264                 [CLK_AUDIO_GATE]        = &audio_gate.common.hw,
 265                 [CLK_MPLL0]             = &mpll0.common.hw,
 266                 [CLK_MPLL0_56M88]       = &mpll0_56m88.hw,
 267                 [CLK_MPLL2]             = &mpll2.common.hw,
 268                 [CLK_MPLL2_47M13]       = &mpll2_47m13.hw,
 269         },
 270         .num    = CLK_ANLG_PHY_G3_NUM,
 271 };
 272
 273 static struct sprd_clk_desc ums512_g3_pll_desc = {
 274         .clk_clks       = ums512_g3_pll_clks,
 275         .num_clk_clks   = ARRAY_SIZE(ums512_g3_pll_clks),
 276         .hw_clks        = &ums512_g3_pll_hws,
 277 };
 278
 279 /* pll clock at gc */
 280 static SPRD_PLL_FW_NAME(twpll, "twpll", "ext-26m", 0x0, 3,
 281                         itable, f_pll, 240, 1000, 1000, 1, 750000000);
 282 static CLK_FIXED_FACTOR_HW(twpll_768m, "twpll-768m", &twpll.common.hw,
 283                            2, 1, 0);
 284 static CLK_FIXED_FACTOR_HW(twpll_384m, "twpll-384m", &twpll.common.hw,
 285                            4, 1, 0);
 286 static CLK_FIXED_FACTOR_HW(twpll_192m, "twpll-192m", &twpll.common.hw,
 287                            8, 1, 0);
 288 static CLK_FIXED_FACTOR_HW(twpll_96m, "twpll-96m", &twpll.common.hw,
 289                            16, 1, 0);
 290 static CLK_FIXED_FACTOR_HW(twpll_48m, "twpll-48m", &twpll.common.hw,
 291                            32, 1, 0);
 292 static CLK_FIXED_FACTOR_HW(twpll_24m, "twpll-24m", &twpll.common.hw,
 293                            64, 1, 0);
 294 static CLK_FIXED_FACTOR_HW(twpll_12m, "twpll-12m", &twpll.common.hw,
 295                            128, 1, 0);
 296 static CLK_FIXED_FACTOR_HW(twpll_512m, "twpll-512m", &twpll.common.hw,
 297                            3, 1, 0);
 298 static CLK_FIXED_FACTOR_HW(twpll_256m, "twpll-256m", &twpll.common.hw,
 299                            6, 1, 0);
 300 static CLK_FIXED_FACTOR_HW(twpll_128m, "twpll-128m", &twpll.common.hw,
 301                            12, 1, 0);
 302 static CLK_FIXED_FACTOR_HW(twpll_64m, "twpll-64m", &twpll.common.hw,
 303                            24, 1, 0);
 304 static CLK_FIXED_FACTOR_HW(twpll_307m2, "twpll-307m2", &twpll.common.hw,
 305                            5, 1, 0);
 306 static CLK_FIXED_FACTOR_HW(twpll_219m4, "twpll-219m4", &twpll.common.hw,
 307                            7, 1, 0);
 308 static CLK_FIXED_FACTOR_HW(twpll_170m6, "twpll-170m6", &twpll.common.hw,
 309                            9, 1, 0);
 310 static CLK_FIXED_FACTOR_HW(twpll_153m6, "twpll-153m6", &twpll.common.hw,
 311                            10, 1, 0);
 312 static CLK_FIXED_FACTOR_HW(twpll_76m8, "twpll-76m8", &twpll.common.hw,
 313                            20, 1, 0);
 314 static CLK_FIXED_FACTOR_HW(twpll_51m2, "twpll-51m2", &twpll.common.hw,
 315                            30, 1, 0);
 316 static CLK_FIXED_FACTOR_HW(twpll_38m4, "twpll-38m4", &twpll.common.hw,
 317                            40, 1, 0);
 318 static CLK_FIXED_FACTOR_HW(twpll_19m2, "twpll-19m2", &twpll.common.hw,
 319                            80, 1, 0);
 320 static CLK_FIXED_FACTOR_HW(twpll_12m29, "twpll-12m29", &twpll.common.hw,
 321                            125, 1, 0);
 322
 323 static SPRD_PLL_FW_NAME(lpll, "lpll", "ext-26m", 0x18, 3,
 324                         itable, f_pll, 240, 1000, 1000, 1, 750000000);
 325 static CLK_FIXED_FACTOR_HW(lpll_614m4, "lpll-614m4", &lpll.common.hw,
 326                            2, 1, 0);
 327 static CLK_FIXED_FACTOR_HW(lpll_409m6, "lpll-409m6", &lpll.common.hw,
 328                            3, 1, 0);
 329 static CLK_FIXED_FACTOR_HW(lpll_245m76, "lpll-245m76", &lpll.common.hw,
 330                            5, 1, 0);
 331 static CLK_FIXED_FACTOR_HW(lpll_30m72, "lpll-30m72", &lpll.common.hw,
 332                            40, 1, 0);
 333
 334 static SPRD_PLL_FW_NAME(isppll, "isppll", "ext-26m", 0x30, 3,
 335                         itable, f_pll, 240, 1000, 1000, 1, 750000000);
 336 static CLK_FIXED_FACTOR_HW(isppll_468m, "isppll-468m", &isppll.common.hw,
 337                            2, 1, 0);
 338 static CLK_FIXED_FACTOR_HW(isppll_78m, "isppll-78m", &isppll.common.hw,
 339                            12, 1, 0);
 340
 341 static SPRD_PLL_HW(gpll, "gpll", &gpll_gate.common.hw, 0x48, 3,
 342                    itable, f_pll, 240, 1000, 1000, 1, 750000000);
 343 static CLK_FIXED_FACTOR_HW(gpll_40m, "gpll-40m", &gpll.common.hw,
 344                            20, 1, 0);
 345
 346 static SPRD_PLL_HW(cppll, "cppll", &cppll_gate.common.hw, 0x60, 3,
 347                    itable, f_pll, 240, 1000, 1000, 1, 750000000);
 348 static CLK_FIXED_FACTOR_HW(cppll_39m32, "cppll-39m32", &cppll.common.hw,
 349                            26, 1, 0);
 350
 351 static struct sprd_clk_common *ums512_gc_pll_clks[] = {
 352         /* address base is 0x323e0000 */
 353         &twpll.common,
 354         &lpll.common,
 355         &isppll.common,
 356         &gpll.common,
 357         &cppll.common,
 358 };
 359
 360 static struct clk_hw_onecell_data ums512_gc_pll_hws = {
 361         .hws    = {
 362                 [CLK_TWPLL]             = &twpll.common.hw,
 363                 [CLK_TWPLL_768M]        = &twpll_768m.hw,
 364                 [CLK_TWPLL_384M]        = &twpll_384m.hw,
 365                 [CLK_TWPLL_192M]        = &twpll_192m.hw,
 366                 [CLK_TWPLL_96M]         = &twpll_96m.hw,
 367                 [CLK_TWPLL_48M]         = &twpll_48m.hw,
 368                 [CLK_TWPLL_24M]         = &twpll_24m.hw,
 369                 [CLK_TWPLL_12M]         = &twpll_12m.hw,
 370                 [CLK_TWPLL_512M]        = &twpll_512m.hw,
 371                 [CLK_TWPLL_256M]        = &twpll_256m.hw,
 372                 [CLK_TWPLL_128M]        = &twpll_128m.hw,
 373                 [CLK_TWPLL_64M]         = &twpll_64m.hw,
 374                 [CLK_TWPLL_307M2]       = &twpll_307m2.hw,
 375                 [CLK_TWPLL_219M4]       = &twpll_219m4.hw,
 376                 [CLK_TWPLL_170M6]       = &twpll_170m6.hw,
 377                 [CLK_TWPLL_153M6]       = &twpll_153m6.hw,
 378                 [CLK_TWPLL_76M8]        = &twpll_76m8.hw,
 379                 [CLK_TWPLL_51M2]        = &twpll_51m2.hw,
 380                 [CLK_TWPLL_38M4]        = &twpll_38m4.hw,
 381                 [CLK_TWPLL_19M2]        = &twpll_19m2.hw,
 382                 [CLK_TWPLL_12M29]       = &twpll_12m29.hw,
 383                 [CLK_LPLL]              = &lpll.common.hw,
 384                 [CLK_LPLL_614M4]        = &lpll_614m4.hw,
 385                 [CLK_LPLL_409M6]        = &lpll_409m6.hw,
 386                 [CLK_LPLL_245M76]       = &lpll_245m76.hw,
 387                 [CLK_LPLL_30M72]        = &lpll_30m72.hw,
 388                 [CLK_ISPPLL]            = &isppll.common.hw,
 389                 [CLK_ISPPLL_468M]       = &isppll_468m.hw,
 390                 [CLK_ISPPLL_78M]        = &isppll_78m.hw,
 391                 [CLK_GPLL]              = &gpll.common.hw,
 392                 [CLK_GPLL_40M]          = &gpll_40m.hw,
 393                 [CLK_CPPLL]             = &cppll.common.hw,
 394                 [CLK_CPPLL_39M32]       = &cppll_39m32.hw,
 395         },
 396         .num    = CLK_ANLG_PHY_GC_NUM,
 397 };
 398
 399 static struct sprd_clk_desc ums512_gc_pll_desc = {
 400         .clk_clks       = ums512_gc_pll_clks,
 401         .num_clk_clks   = ARRAY_SIZE(ums512_gc_pll_clks),
 402         .hw_clks        = &ums512_gc_pll_hws,
 403 };
 404
 405 /* ap ahb gates */
 406 static SPRD_SC_GATE_CLK_FW_NAME(dsi_eb, "dsi-eb", "ext-26m",
 407                                 0x0, 0x1000, BIT(0), 0, 0);
 408 static SPRD_SC_GATE_CLK_FW_NAME(dispc_eb, "dispc-eb", "ext-26m",
 409                                 0x0, 0x1000, BIT(1), 0, 0);
 410 static SPRD_SC_GATE_CLK_FW_NAME(vsp_eb, "vsp-eb", "ext-26m",
 411                                 0x0, 0x1000, BIT(2), 0, 0);
 412 static SPRD_SC_GATE_CLK_FW_NAME(vdma_eb, "vdma-eb", "ext-26m",
 413                                 0x0, 0x1000, BIT(3), 0, 0);
 414 static SPRD_SC_GATE_CLK_FW_NAME(dma_pub_eb, "dma-pub-eb", "ext-26m",
 415                                 0x0, 0x1000, BIT(4), 0, 0);
 416 static SPRD_SC_GATE_CLK_FW_NAME(dma_sec_eb, "dma-sec-eb", "ext-26m",
 417                                 0x0, 0x1000, BIT(5), 0, 0);
 418 static SPRD_SC_GATE_CLK_FW_NAME(ipi_eb, "ipi-eb", "ext-26m",
 419                                 0x0, 0x1000, BIT(6), 0, 0);
 420 static SPRD_SC_GATE_CLK_FW_NAME(ahb_ckg_eb, "ahb-ckg-eb", "ext-26m",
 421                                 0x0, 0x1000, BIT(7), CLK_IGNORE_UNUSED, 0);
 422 static SPRD_SC_GATE_CLK_FW_NAME(bm_clk_eb, "bm-clk-eb", "ext-26m",
 423                                 0x0, 0x1000, BIT(8), CLK_IGNORE_UNUSED, 0);
 424
 425 static struct sprd_clk_common *ums512_apahb_gate[] = {
 426         /* address base is 0x20100000 */
 427         &dsi_eb.common,
 428         &dispc_eb.common,
 429         &vsp_eb.common,
 430         &vdma_eb.common,
 431         &dma_pub_eb.common,
 432         &dma_sec_eb.common,
 433         &ipi_eb.common,
 434         &ahb_ckg_eb.common,
 435         &bm_clk_eb.common,
 436 };
 437
 438 static struct clk_hw_onecell_data ums512_apahb_gate_hws = {
 439         .hws    = {
 440                 [CLK_DSI_EB]            = &dsi_eb.common.hw,
 441                 [CLK_DISPC_EB]          = &dispc_eb.common.hw,
 442                 [CLK_VSP_EB]            = &vsp_eb.common.hw,
 443                 [CLK_VDMA_EB]           = &vdma_eb.common.hw,
 444                 [CLK_DMA_PUB_EB]        = &dma_pub_eb.common.hw,
 445                 [CLK_DMA_SEC_EB]        = &dma_sec_eb.common.hw,
 446                 [CLK_IPI_EB]            = &ipi_eb.common.hw,
 447                 [CLK_AHB_CKG_EB]        = &ahb_ckg_eb.common.hw,
 448                 [CLK_BM_CLK_EB]         = &bm_clk_eb.common.hw,
 449         },
 450         .num    = CLK_AP_AHB_GATE_NUM,
 451 };
 452
 453 static struct sprd_clk_desc ums512_apahb_gate_desc = {
 454         .clk_clks       = ums512_apahb_gate,
 455         .num_clk_clks   = ARRAY_SIZE(ums512_apahb_gate),
 456         .hw_clks        = &ums512_apahb_gate_hws,
 457 };
 458
 459 /* ap clks */
 460 static const struct clk_parent_data ap_apb_parents[] = {
 461         { .fw_name = "ext-26m" },
 462         { .hw = &twpll_64m.hw  },
 463         { .hw = &twpll_96m.hw  },
 464         { .hw = &twpll_128m.hw  },
 465 };
 466 static SPRD_MUX_CLK_DATA(ap_apb_clk, "ap-apb-clk", ap_apb_parents,
 467                          0x20, 0, 2, UMS512_MUX_FLAG);
 468
 469 static const struct clk_parent_data ipi_parents[] = {
 470         { .fw_name = "ext-26m" },
 471         { .hw = &twpll_64m.hw  },
 472         { .hw = &twpll_96m.hw  },
 473         { .hw = &twpll_128m.hw  },
 474 };
 475 static SPRD_MUX_CLK_DATA(ipi_clk, "ipi-clk", ipi_parents,
 476                          0x24, 0, 2, UMS512_MUX_FLAG);
 477
 478 static const struct clk_parent_data ap_uart_parents[] = {
 479         { .fw_name = "ext-26m" },
 480         { .hw = &twpll_48m.hw  },
 481         { .hw = &twpll_51m2.hw  },
 482         { .hw = &twpll_96m.hw  },
 483 };
 484 static SPRD_COMP_CLK_DATA(ap_uart0_clk, "ap-uart0-clk", ap_uart_parents,
 485                           0x28, 0, 2, 8, 3, 0);
 486 static SPRD_COMP_CLK_DATA(ap_uart1_clk, "ap-uart1-clk", ap_uart_parents,
 487                           0x2c, 0, 2, 8, 3, 0);
 488 static SPRD_COMP_CLK_DATA(ap_uart2_clk, "ap-uart2-clk", ap_uart_parents,
 489                           0x30, 0, 2, 8, 3, 0);
 490
 491 static const struct clk_parent_data i2c_parents[] = {
 492         { .fw_name = "ext-26m" },
 493         { .hw = &twpll_48m.hw  },
 494         { .hw = &twpll_51m2.hw  },
 495         { .hw = &twpll_153m6.hw  },
 496 };
 497 static SPRD_COMP_CLK_DATA(ap_i2c0_clk, "ap-i2c0-clk", i2c_parents,
 498                           0x34, 0, 2, 8, 3, 0);
 499 static SPRD_COMP_CLK_DATA(ap_i2c1_clk, "ap-i2c1-clk", i2c_parents,
 500                           0x38, 0, 2, 8, 3, 0);
 501 static SPRD_COMP_CLK_DATA(ap_i2c2_clk, "ap-i2c2-clk", i2c_parents,
 502                           0x3c, 0, 2, 8, 3, 0);
 503 static SPRD_COMP_CLK_DATA(ap_i2c3_clk, "ap-i2c3-clk", i2c_parents,
 504                           0x40, 0, 2, 8, 3, 0);
 505 static SPRD_COMP_CLK_DATA(ap_i2c4_clk, "ap-i2c4-clk", i2c_parents,
 506                           0x44, 0, 2, 8, 3, 0);
 507
 508 static const struct clk_parent_data spi_parents[] = {
 509         { .fw_name = "ext-26m" },
 510         { .hw = &twpll_128m.hw  },
 511         { .hw = &twpll_153m6.hw  },
 512         { .hw = &twpll_192m.hw  },
 513 };
 514 static SPRD_COMP_CLK_DATA(ap_spi0_clk, "ap-spi0-clk", spi_parents,
 515                           0x48, 0, 2, 8, 3, 0);
 516 static SPRD_COMP_CLK_DATA(ap_spi1_clk, "ap-spi1-clk", spi_parents,
 517                           0x4c, 0, 2, 8, 3, 0);
 518 static SPRD_COMP_CLK_DATA(ap_spi2_clk, "ap-spi2-clk", spi_parents,
 519                           0x50, 0, 2, 8, 3, 0);
 520 static SPRD_COMP_CLK_DATA(ap_spi3_clk, "ap-spi3-clk", spi_parents,
 521                           0x54, 0, 2, 8, 3, 0);
 522
 523 static const struct clk_parent_data iis_parents[] = {
 524         { .fw_name = "ext-26m" },
 525         { .hw = &twpll_128m.hw  },
 526         { .hw = &twpll_153m6.hw  },
 527 };
 528 static SPRD_COMP_CLK_DATA(ap_iis0_clk, "ap-iis0-clk", iis_parents,
 529                           0x58, 0, 2, 8, 3, 0);
 530 static SPRD_COMP_CLK_DATA(ap_iis1_clk, "ap-iis1-clk", iis_parents,
 531                           0x5c, 0, 2, 8, 3, 0);
 532 static SPRD_COMP_CLK_DATA(ap_iis2_clk, "ap-iis2-clk", iis_parents,
 533                           0x60, 0, 2, 8, 3, 0);
 534
 535 static const struct clk_parent_data sim_parents[] = {
 536         { .fw_name = "ext-26m" },
 537         { .hw = &twpll_51m2.hw  },
 538         { .hw = &twpll_64m.hw  },
 539         { .hw = &twpll_96m.hw  },
 540         { .hw = &twpll_128m.hw  },
 541 };
 542 static SPRD_COMP_CLK_DATA(ap_sim_clk, "ap-sim-clk", sim_parents,
 543                           0x64, 0, 3, 8, 3, 0);
 544
 545 static const struct clk_parent_data ap_ce_parents[] = {
 546         { .fw_name = "ext-26m" },
 547         { .hw = &twpll_96m.hw  },
 548         { .hw = &twpll_192m.hw  },
 549         { .hw = &twpll_256m.hw  },
 550 };
 551 static SPRD_MUX_CLK_DATA(ap_ce_clk, "ap-ce-clk", ap_ce_parents,
 552                          0x68, 0, 2, UMS512_MUX_FLAG);
 553
 554 static const struct clk_parent_data sdio_parents[] = {
 555         { .hw = &clk_1m.hw  },
 556         { .fw_name = "ext-26m" },
 557         { .hw = &twpll_307m2.hw  },
 558         { .hw = &twpll_384m.hw  },
 559         { .hw = &rpll.common.hw  },
 560         { .hw = &lpll_409m6.hw  },
 561 };
 562 static SPRD_MUX_CLK_DATA(sdio0_2x_clk, "sdio0-2x", sdio_parents,
 563                          0x80, 0, 3, UMS512_MUX_FLAG);
 564 static SPRD_MUX_CLK_DATA(sdio1_2x_clk, "sdio1-2x", sdio_parents,
 565                          0x88, 0, 3, UMS512_MUX_FLAG);
 566 static SPRD_MUX_CLK_DATA(emmc_2x_clk, "emmc-2x", sdio_parents,
 567                          0x90, 0, 3, UMS512_MUX_FLAG);
 568
 569 static const struct clk_parent_data vsp_parents[] = {
 570         { .hw = &twpll_256m.hw  },
 571         { .hw = &twpll_307m2.hw  },
 572         { .hw = &twpll_384m.hw  },
 573 };
 574 static SPRD_MUX_CLK_DATA(vsp_clk, "vsp-clk", vsp_parents,
 575                          0x98, 0, 2, UMS512_MUX_FLAG);
 576
 577 static const struct clk_parent_data dispc0_parents[] = {
 578         { .hw = &twpll_153m6.hw  },
 579         { .hw = &twpll_192m.hw  },
 580         { .hw = &twpll_256m.hw  },
 581         { .hw = &twpll_307m2.hw  },
 582         { .hw = &twpll_384m.hw  },
 583 };
 584 static SPRD_MUX_CLK_DATA(dispc0_clk, "dispc0-clk", dispc0_parents,
 585                          0x9c, 0, 3, UMS512_MUX_FLAG);
 586
 587 static const struct clk_parent_data dispc0_dpi_parents[] = {
 588         { .hw = &twpll_96m.hw  },
 589         { .hw = &twpll_128m.hw  },
 590         { .hw = &twpll_153m6.hw  },
 591         { .hw = &twpll_192m.hw  },
 592 };
 593 static SPRD_COMP_CLK_DATA(dispc0_dpi_clk, "dispc0-dpi-clk", dispc0_dpi_parents,
 594                           0xa0, 0, 3, 8, 4, 0);
 595
 596 static const struct clk_parent_data dsi_apb_parents[] = {
 597         { .hw = &twpll_96m.hw  },
 598         { .hw = &twpll_128m.hw  },
 599         { .hw = &twpll_153m6.hw  },
 600         { .hw = &twpll_192m.hw  },
 601 };
 602 static SPRD_MUX_CLK_DATA(dsi_apb_clk, "dsi-apb-clk", dsi_apb_parents,
 603                          0xa4, 0, 2, UMS512_MUX_FLAG);
 604
 605 static SPRD_GATE_CLK_FW_NAME(dsi_rxesc, "dsi-rxesc", "ext-26m",
 606                              0xa8, BIT(16), 0, 0);
 607
 608 static SPRD_GATE_CLK_FW_NAME(dsi_lanebyte, "dsi-lanebyte", "ext-26m",
 609                              0xac, BIT(16), 0, 0);
 610
 611 static const struct clk_parent_data vdsp_parents[] = {
 612         { .hw = &twpll_256m.hw  },
 613         { .hw = &twpll_384m.hw  },
 614         { .hw = &twpll_512m.hw  },
 615         { .hw = &lpll_614m4.hw  },
 616         { .hw = &twpll_768m.hw  },
 617         { .hw = &isppll.common.hw  },
 618 };
 619 static SPRD_MUX_CLK_DATA(vdsp_clk, "vdsp-clk", vdsp_parents,
 620                          0xb0, 0, 3, UMS512_MUX_FLAG);
 621 static SPRD_DIV_CLK_HW(vdsp_m_clk, "vdsp-m-clk", &vdsp_clk.common.hw,
 622                        0xb4, 8, 2, 0);
 623
 624 static struct sprd_clk_common *ums512_ap_clks[] = {
 625         /* address base is 0x20200000 */
 626         &ap_apb_clk.common,
 627         &ipi_clk.common,
 628         &ap_uart0_clk.common,
 629         &ap_uart1_clk.common,
 630         &ap_uart2_clk.common,
 631         &ap_i2c0_clk.common,
 632         &ap_i2c1_clk.common,
 633         &ap_i2c2_clk.common,
 634         &ap_i2c3_clk.common,
 635         &ap_i2c4_clk.common,
 636         &ap_spi0_clk.common,
 637         &ap_spi1_clk.common,
 638         &ap_spi2_clk.common,
 639         &ap_spi3_clk.common,
 640         &ap_iis0_clk.common,
 641         &ap_iis1_clk.common,
 642         &ap_iis2_clk.common,
 643         &ap_sim_clk.common,
 644         &ap_ce_clk.common,
 645         &sdio0_2x_clk.common,
 646         &sdio1_2x_clk.common,
 647         &emmc_2x_clk.common,
 648         &vsp_clk.common,
 649         &dispc0_clk.common,
 650         &dispc0_dpi_clk.common,
 651         &dsi_apb_clk.common,
 652         &dsi_rxesc.common,
 653         &dsi_lanebyte.common,
 654         &vdsp_clk.common,
 655         &vdsp_m_clk.common,
 656
 657 };
 658
 659 static struct clk_hw_onecell_data ums512_ap_clk_hws = {
 660         .hws    = {
 661                 [CLK_AP_APB]            = &ap_apb_clk.common.hw,
 662                 [CLK_IPI]               = &ipi_clk.common.hw,
 663                 [CLK_AP_UART0]          = &ap_uart0_clk.common.hw,
 664                 [CLK_AP_UART1]          = &ap_uart1_clk.common.hw,
 665                 [CLK_AP_UART2]          = &ap_uart2_clk.common.hw,
 666                 [CLK_AP_I2C0]           = &ap_i2c0_clk.common.hw,
 667                 [CLK_AP_I2C1]           = &ap_i2c1_clk.common.hw,
 668                 [CLK_AP_I2C2]           = &ap_i2c2_clk.common.hw,
 669                 [CLK_AP_I2C3]           = &ap_i2c3_clk.common.hw,
 670                 [CLK_AP_I2C4]           = &ap_i2c4_clk.common.hw,
 671                 [CLK_AP_SPI0]           = &ap_spi0_clk.common.hw,
 672                 [CLK_AP_SPI1]           = &ap_spi1_clk.common.hw,
 673                 [CLK_AP_SPI2]           = &ap_spi2_clk.common.hw,
 674                 [CLK_AP_SPI3]           = &ap_spi3_clk.common.hw,
 675                 [CLK_AP_IIS0]           = &ap_iis0_clk.common.hw,
 676                 [CLK_AP_IIS1]           = &ap_iis1_clk.common.hw,
 677                 [CLK_AP_IIS2]           = &ap_iis2_clk.common.hw,
 678                 [CLK_AP_SIM]            = &ap_sim_clk.common.hw,
 679                 [CLK_AP_CE]             = &ap_ce_clk.common.hw,
 680                 [CLK_SDIO0_2X]          = &sdio0_2x_clk.common.hw,
 681                 [CLK_SDIO1_2X]          = &sdio1_2x_clk.common.hw,
 682                 [CLK_EMMC_2X]           = &emmc_2x_clk.common.hw,
 683                 [CLK_VSP]               = &vsp_clk.common.hw,
 684                 [CLK_DISPC0]            = &dispc0_clk.common.hw,
 685                 [CLK_DISPC0_DPI]        = &dispc0_dpi_clk.common.hw,
 686                 [CLK_DSI_APB]           = &dsi_apb_clk.common.hw,
 687                 [CLK_DSI_RXESC]         = &dsi_rxesc.common.hw,
 688                 [CLK_DSI_LANEBYTE]      = &dsi_lanebyte.common.hw,
 689                 [CLK_VDSP]              = &vdsp_clk.common.hw,
 690                 [CLK_VDSP_M]            = &vdsp_m_clk.common.hw,
 691         },
 692         .num    = CLK_AP_CLK_NUM,
 693 };
 694
 695 static struct sprd_clk_desc ums512_ap_clk_desc = {
 696         .clk_clks       = ums512_ap_clks,
 697         .num_clk_clks   = ARRAY_SIZE(ums512_ap_clks),
 698         .hw_clks        = &ums512_ap_clk_hws,
 699 };
 700
 701 /* aon apb clks */
 702 static const struct clk_parent_data aon_apb_parents[] = {
 703         { .hw = &rco_4m.hw  },
 704         { .fw_name = "ext-4m"  },
 705         { .hw = &clk_13m.hw  },
 706         { .hw = &rco_25m.hw  },
 707         { .fw_name = "ext-26m" },
 708         { .hw = &twpll_96m.hw  },
 709         { .fw_name = "rco-100m" },
 710         { .hw = &twpll_128m.hw  },
 711 };
 712 static SPRD_COMP_CLK_DATA(aon_apb_clk, "aon-apb-clk", aon_apb_parents,
 713                           0x220, 0, 3, 8, 2, 0);
 714
 715
 716 static const struct clk_parent_data adi_parents[] = {
 717         { .hw = &rco_4m.hw  },
 718         { .fw_name = "ext-26m" },
 719         { .hw = &rco_25m.hw  },
 720         { .hw = &twpll_38m4.hw  },
 721         { .hw = &twpll_51m2.hw  },
 722 };
 723 static SPRD_MUX_CLK_DATA(adi_clk, "adi-clk", adi_parents,
 724                          0x224, 0, 3, UMS512_MUX_FLAG);
 725
 726 static const struct clk_parent_data aux_parents[] = {
 727         { .fw_name = "ext-32k" },
 728         { .fw_name = "ext-26m" },
 729         { .hw = &clk_26m_aud.hw  },
 730         { .hw = &rco_25m.hw  },
 731         { .hw = &cppll_39m32.hw  },
 732         { .hw = &mpll0_56m88.hw  },
 733         { .hw = &mpll1_63m38.hw  },
 734         { .hw = &mpll2_47m13.hw  },
 735         { .hw = &dpll0_58m31.hw  },
 736         { .hw = &gpll_40m.hw  },
 737         { .hw = &twpll_48m.hw  },
 738 };
 739 static const struct clk_parent_data aux1_parents[] = {
 740         { .fw_name = "ext-32k" },
 741         { .fw_name = "ext-26m" },
 742         { .hw = &clk_26m_aud.hw  },
 743         { .hw = &rco_25m.hw  },
 744         { .hw = &cppll_39m32.hw  },
 745         { .hw = &mpll0_56m88.hw  },
 746         { .hw = &mpll1_63m38.hw  },
 747         { .hw = &mpll2_47m13.hw  },
 748         { .hw = &dpll0_58m31.hw  },
 749         { .hw = &gpll_40m.hw  },
 750         { .hw = &twpll_19m2.hw  },
 751         { .hw = &lpll_30m72.hw  },
 752         { .hw = &rpll.common.hw  },
 753         { .hw = &twpll_12m29.hw  },
 754
 755 };
 756 static SPRD_COMP_CLK_DATA(aux0_clk, "aux0-clk", aux_parents,
 757                           0x228, 0, 5, 8, 4, 0);
 758 static SPRD_COMP_CLK_DATA(aux1_clk, "aux1-clk", aux1_parents,
 759                           0x22c, 0, 5, 8, 4, 0);
 760 static SPRD_COMP_CLK_DATA(aux2_clk, "aux2-clk", aux_parents,
 761                           0x230, 0, 5, 8, 4, 0);
 762 static SPRD_COMP_CLK_DATA(probe_clk, "probe-clk", aux_parents,
 763                           0x234, 0, 5, 8, 4, 0);
 764
 765 static const struct clk_parent_data pwm_parents[] = {
 766         { .fw_name = "ext-32k" },
 767         { .fw_name = "ext-26m" },
 768         { .hw = &rco_4m.hw  },
 769         { .hw = &rco_25m.hw  },
 770         { .hw = &twpll_48m.hw  },
 771 };
 772 static SPRD_MUX_CLK_DATA(pwm0_clk, "pwm0-clk", pwm_parents,
 773                          0x238, 0, 3, UMS512_MUX_FLAG);
 774 static SPRD_MUX_CLK_DATA(pwm1_clk, "pwm1-clk", pwm_parents,
 775                          0x23c, 0, 3, UMS512_MUX_FLAG);
 776 static SPRD_MUX_CLK_DATA(pwm2_clk, "pwm2-clk", pwm_parents,
 777                          0x240, 0, 3, UMS512_MUX_FLAG);
 778 static SPRD_MUX_CLK_DATA(pwm3_clk, "pwm3-clk", pwm_parents,
 779                          0x244, 0, 3, UMS512_MUX_FLAG);
 780
 781 static const struct clk_parent_data efuse_parents[] = {
 782         { .hw = &rco_25m.hw  },
 783         { .fw_name = "ext-26m" },
 784 };
 785 static SPRD_MUX_CLK_DATA(efuse_clk, "efuse-clk", efuse_parents,
 786                          0x248, 0, 1, UMS512_MUX_FLAG);
 787
 788 static const struct clk_parent_data uart_parents[] = {
 789         { .hw = &rco_4m.hw  },
 790         { .fw_name = "ext-26m" },
 791         { .hw = &twpll_48m.hw  },
 792         { .hw = &twpll_51m2.hw  },
 793         { .hw = &twpll_96m.hw  },
 794         { .fw_name = "rco-100m" },
 795         { .hw = &twpll_128m.hw  },
 796 };
 797 static SPRD_MUX_CLK_DATA(uart0_clk, "uart0-clk", uart_parents,
 798                          0x24c, 0, 3, UMS512_MUX_FLAG);
 799 static SPRD_MUX_CLK_DATA(uart1_clk, "uart1-clk", uart_parents,
 800                          0x250, 0, 3, UMS512_MUX_FLAG);
 801
 802 static const struct clk_parent_data thm_parents[] = {
 803         { .fw_name = "ext-32k" },
 804         { .hw = &clk_250k.hw  },
 805 };
 806 static SPRD_MUX_CLK_DATA(thm0_clk, "thm0-clk", thm_parents,
 807                          0x260, 0, 1, UMS512_MUX_FLAG);
 808 static SPRD_MUX_CLK_DATA(thm1_clk, "thm1-clk", thm_parents,
 809                          0x264, 0, 1, UMS512_MUX_FLAG);
 810 static SPRD_MUX_CLK_DATA(thm2_clk, "thm2-clk", thm_parents,
 811                          0x268, 0, 1, UMS512_MUX_FLAG);
 812 static SPRD_MUX_CLK_DATA(thm3_clk, "thm3-clk", thm_parents,
 813                          0x26c, 0, 1, UMS512_MUX_FLAG);
 814
 815 static const struct clk_parent_data aon_i2c_parents[] = {
 816         { .hw = &rco_4m.hw  },
 817         { .fw_name = "ext-26m" },
 818         { .hw = &twpll_48m.hw  },
 819         { .hw = &twpll_51m2.hw  },
 820         { .fw_name = "rco-100m" },
 821         { .hw = &twpll_153m6.hw  },
 822 };
 823 static SPRD_MUX_CLK_DATA(aon_i2c_clk, "aon-i2c-clk", aon_i2c_parents,
 824                          0x27c, 0, 3, UMS512_MUX_FLAG);
 825
 826 static const struct clk_parent_data aon_iis_parents[] = {
 827         { .fw_name = "ext-26m" },
 828         { .hw = &twpll_128m.hw  },
 829         { .hw = &twpll_153m6.hw  },
 830 };
 831 static SPRD_MUX_CLK_DATA(aon_iis_clk, "aon-iis-clk", aon_iis_parents,
 832                          0x280, 0, 2, UMS512_MUX_FLAG);
 833
 834 static const struct clk_parent_data scc_parents[] = {
 835         { .fw_name = "ext-26m" },
 836         { .hw = &twpll_48m.hw  },
 837         { .hw = &twpll_51m2.hw  },
 838         { .hw = &twpll_96m.hw  },
 839 };
 840 static SPRD_MUX_CLK_DATA(scc_clk, "scc-clk", scc_parents,
 841                          0x284, 0, 2, UMS512_MUX_FLAG);
 842
 843 static const struct clk_parent_data apcpu_dap_parents[] = {
 844         { .fw_name = "ext-26m" },
 845         { .hw = &rco_4m.hw  },
 846         { .hw = &twpll_76m8.hw  },
 847         { .fw_name = "rco-100m" },
 848         { .hw = &twpll_128m.hw  },
 849         { .hw = &twpll_153m6.hw  },
 850 };
 851 static SPRD_MUX_CLK_DATA(apcpu_dap_clk, "apcpu-dap-clk", apcpu_dap_parents,
 852                          0x288, 0, 3, UMS512_MUX_FLAG);
 853
 854 static SPRD_GATE_CLK_FW_NAME(apcpu_dap_mtck, "apcpu-dap-mtck", "ext-26m",
 855                              0x28c, BIT(16), 0, 0);
 856
 857 static const struct clk_parent_data apcpu_ts_parents[] = {
 858         { .fw_name = "ext-32m" },
 859         { .fw_name = "ext-26m" },
 860         { .hw = &twpll_128m.hw  },
 861         { .hw = &twpll_153m6.hw  },
 862 };
 863 static SPRD_MUX_CLK_DATA(apcpu_ts_clk, "apcpu-ts-clk", apcpu_ts_parents,
 864                          0x290, 0, 2, UMS512_MUX_FLAG);
 865
 866 static const struct clk_parent_data debug_ts_parents[] = {
 867         { .fw_name = "ext-26m" },
 868         { .hw = &twpll_76m8.hw  },
 869         { .hw = &twpll_128m.hw  },
 870         { .hw = &twpll_192m.hw  },
 871 };
 872 static SPRD_MUX_CLK_DATA(debug_ts_clk, "debug-ts-clk", debug_ts_parents,
 873                          0x294, 0, 2, UMS512_MUX_FLAG);
 874
 875 static SPRD_GATE_CLK_FW_NAME(dsi_test_s, "dsi-test-s", "ext-26m",
 876                              0x298, BIT(16), 0, 0);
 877
 878 static const struct clk_parent_data djtag_tck_parents[] = {
 879         { .hw = &rco_4m.hw  },
 880         { .fw_name = "ext-26m" },
 881 };
 882 static SPRD_MUX_CLK_DATA(djtag_tck_clk, "djtag-tck-clk", djtag_tck_parents,
 883                          0x2b4, 0, 1, UMS512_MUX_FLAG);
 884
 885 static SPRD_GATE_CLK_FW_NAME(djtag_tck_hw, "djtag-tck-hw", "ext-26m",
 886                              0x2b8, BIT(16), 0, 0);
 887
 888 static const struct clk_parent_data aon_tmr_parents[] = {
 889         { .hw = &rco_4m.hw  },
 890         { .hw = &rco_25m.hw  },
 891         { .fw_name = "ext-26m" },
 892 };
 893 static SPRD_MUX_CLK_DATA(aon_tmr_clk, "aon-tmr-clk", aon_tmr_parents,
 894                          0x2c0, 0, 2, UMS512_MUX_FLAG);
 895
 896 static const struct clk_parent_data aon_pmu_parents[] = {
 897         { .fw_name = "ext-32k" },
 898         { .hw = &rco_4m.hw  },
 899         { .fw_name = "ext-4m" },
 900 };
 901 static SPRD_MUX_CLK_DATA(aon_pmu_clk, "aon-pmu-clk", aon_pmu_parents,
 902                          0x2c8, 0, 2, UMS512_MUX_FLAG);
 903
 904 static const struct clk_parent_data debounce_parents[] = {
 905         { .fw_name = "ext-32k" },
 906         { .hw = &rco_4m.hw  },
 907         { .hw = &rco_25m.hw  },
 908         { .fw_name = "ext-26m" },
 909 };
 910 static SPRD_MUX_CLK_DATA(debounce_clk, "debounce-clk", debounce_parents,
 911                          0x2cc, 0, 2, UMS512_MUX_FLAG);
 912
 913 static const struct clk_parent_data apcpu_pmu_parents[] = {
 914         { .fw_name = "ext-26m" },
 915         { .hw = &twpll_76m8.hw  },
 916         { .fw_name = "rco-100m" },
 917         { .hw = &twpll_128m.hw  },
 918 };
 919 static SPRD_MUX_CLK_DATA(apcpu_pmu_clk, "apcpu-pmu-clk", apcpu_pmu_parents,
 920                          0x2d0, 0, 2, UMS512_MUX_FLAG);
 921
 922 static const struct clk_parent_data top_dvfs_parents[] = {
 923         { .fw_name = "ext-26m" },
 924         { .hw = &twpll_96m.hw  },
 925         { .fw_name = "rco-100m" },
 926         { .hw = &twpll_128m.hw  },
 927 };
 928 static SPRD_MUX_CLK_DATA(top_dvfs_clk, "top-dvfs-clk", top_dvfs_parents,
 929                          0x2d8, 0, 2, UMS512_MUX_FLAG);
 930
 931 static SPRD_GATE_CLK_FW_NAME(otg_utmi, "otg-utmi", "ext-26m", 0x2dc,
 932                                 BIT(16), 0, 0);
 933
 934 static const struct clk_parent_data otg_ref_parents[] = {
 935         { .hw = &twpll_12m.hw  },
 936         { .fw_name = "ext-26m" },
 937 };
 938 static SPRD_MUX_CLK_DATA(otg_ref_clk, "otg-ref-clk", otg_ref_parents,
 939                          0x2e0, 0, 1, UMS512_MUX_FLAG);
 940
 941 static const struct clk_parent_data cssys_parents[] = {
 942         { .hw = &rco_25m.hw  },
 943         { .fw_name = "ext-26m" },
 944         { .fw_name = "rco-100m" },
 945         { .hw = &twpll_153m6.hw  },
 946         { .hw = &twpll_384m.hw  },
 947         { .hw = &twpll_512m.hw  },
 948 };
 949 static SPRD_COMP_CLK_DATA(cssys_clk, "cssys-clk", cssys_parents,
 950                           0x2e4, 0, 3, 8, 2, 0);
 951 static SPRD_DIV_CLK_HW(cssys_pub_clk, "cssys-pub-clk", &cssys_clk.common.hw,
 952                        0x2e8, 8, 2, 0);
 953 static SPRD_DIV_CLK_HW(cssys_apb_clk, "cssys-apb-clk", &cssys_clk.common.hw,
 954                        0x2ec, 8, 3, 0);
 955
 956 static const struct clk_parent_data ap_axi_parents[] = {
 957         { .fw_name = "ext-26m" },
 958         { .hw = &twpll_76m8.hw  },
 959         { .hw = &twpll_128m.hw  },
 960         { .hw = &twpll_256m.hw  },
 961 };
 962 static SPRD_MUX_CLK_DATA(ap_axi_clk, "ap-axi-clk", ap_axi_parents,
 963                          0x2f0, 0, 2, UMS512_MUX_FLAG);
 964
 965 static const struct clk_parent_data ap_mm_parents[] = {
 966         { .fw_name = "ext-26m" },
 967         { .hw = &twpll_96m.hw  },
 968         { .hw = &twpll_128m.hw  },
 969         { .hw = &twpll_153m6.hw  },
 970 };
 971 static SPRD_MUX_CLK_DATA(ap_mm_clk, "ap-mm-clk", ap_mm_parents,
 972                          0x2f4, 0, 2, UMS512_MUX_FLAG);
 973
 974 static const struct clk_parent_data sdio2_2x_parents[] = {
 975         { .hw = &clk_1m.hw  },
 976         { .fw_name = "ext-26m" },
 977         { .hw = &twpll_307m2.hw  },
 978         { .hw = &twpll_384m.hw  },
 979         { .hw = &rpll.common.hw  },
 980         { .hw = &lpll_409m6.hw  },
 981 };
 982 static SPRD_MUX_CLK_DATA(sdio2_2x_clk, "sdio2-2x-clk", sdio2_2x_parents,
 983                          0x2f8, 0, 3, UMS512_MUX_FLAG);
 984
 985 static const struct clk_parent_data analog_io_apb_parents[] = {
 986         { .fw_name = "ext-26m" },
 987         { .hw = &twpll_48m.hw  },
 988 };
 989 static SPRD_COMP_CLK_DATA(analog_io_apb, "analog-io-apb", analog_io_apb_parents,
 990                           0x300, 0, 1, 8, 2, 0);
 991
 992 static const struct clk_parent_data dmc_ref_parents[] = {
 993         { .hw = &clk_6m5.hw  },
 994         { .hw = &clk_13m.hw  },
 995         { .fw_name = "ext-26m" },
 996 };
 997 static SPRD_MUX_CLK_DATA(dmc_ref_clk, "dmc-ref-clk", dmc_ref_parents,
 998                          0x304, 0, 2, UMS512_MUX_FLAG);
 999
1000 static const struct clk_parent_data emc_parents[] = {
1001         { .fw_name = "ext-26m" },
1002         { .hw = &twpll_384m.hw  },
1003         { .hw = &twpll_512m.hw  },
1004         { .hw = &twpll_768m.hw  },
1005 };
1006 static SPRD_MUX_CLK_DATA(emc_clk, "emc-clk", emc_parents,
1007                          0x30c, 0, 2, UMS512_MUX_FLAG);
1008
1009 static const struct clk_parent_data usb_parents[] = {
1010         { .hw = &rco_25m.hw  },
1011         { .fw_name = "ext-26m" },
1012         { .hw = &twpll_192m.hw  },
1013         { .hw = &twpll_96m.hw  },
1014         { .fw_name = "rco-100m" },
1015         { .hw = &twpll_128m.hw  },
1016 };
1017 static SPRD_COMP_CLK_DATA(usb_clk, "usb-clk", usb_parents,
1018                           0x310, 0, 3, 8, 2, 0);
1019
1020 static const struct clk_parent_data pmu_26m_parents[] = {
1021         { .hw = &rco_25m.hw  },
1022         { .fw_name = "ext-26m" },
1023 };
1024 static SPRD_MUX_CLK_DATA(pmu_26m_clk, "26m-pmu-clk", pmu_26m_parents,
1025                          0x318, 0, 1, UMS512_MUX_FLAG);
1026
1027 static struct sprd_clk_common *ums512_aon_apb[] = {
1028         /* address base is 0x32080200 */
1029         &aon_apb_clk.common,
1030         &adi_clk.common,
1031         &aux0_clk.common,
1032         &aux1_clk.common,
1033         &aux2_clk.common,
1034         &probe_clk.common,
1035         &pwm0_clk.common,
1036         &pwm1_clk.common,
1037         &pwm2_clk.common,
1038         &pwm3_clk.common,
1039         &efuse_clk.common,
1040         &uart0_clk.common,
1041         &uart1_clk.common,
1042         &thm0_clk.common,
1043         &thm1_clk.common,
1044         &thm2_clk.common,
1045         &thm3_clk.common,
1046         &aon_i2c_clk.common,
1047         &aon_iis_clk.common,
1048         &scc_clk.common,
1049         &apcpu_dap_clk.common,
1050         &apcpu_dap_mtck.common,
1051         &apcpu_ts_clk.common,
1052         &debug_ts_clk.common,
1053         &dsi_test_s.common,
1054         &djtag_tck_clk.common,
1055         &djtag_tck_hw.common,
1056         &aon_tmr_clk.common,
1057         &aon_pmu_clk.common,
1058         &debounce_clk.common,
1059         &apcpu_pmu_clk.common,
1060         &top_dvfs_clk.common,
1061         &otg_utmi.common,
1062         &otg_ref_clk.common,
1063         &cssys_clk.common,
1064         &cssys_pub_clk.common,
1065         &cssys_apb_clk.common,
1066         &ap_axi_clk.common,
1067         &ap_mm_clk.common,
1068         &sdio2_2x_clk.common,
1069         &analog_io_apb.common,
1070         &dmc_ref_clk.common,
1071         &emc_clk.common,
1072         &usb_clk.common,
1073         &pmu_26m_clk.common,
1074 };
1075
1076 static struct clk_hw_onecell_data ums512_aon_apb_hws = {
1077         .hws    = {
1078                 [CLK_AON_APB]           = &aon_apb_clk.common.hw,
1079                 [CLK_ADI]               = &adi_clk.common.hw,
1080                 [CLK_AUX0]              = &aux0_clk.common.hw,
1081                 [CLK_AUX1]              = &aux1_clk.common.hw,
1082                 [CLK_AUX2]              = &aux2_clk.common.hw,
1083                 [CLK_PROBE]             = &probe_clk.common.hw,
1084                 [CLK_PWM0]              = &pwm0_clk.common.hw,
1085                 [CLK_PWM1]              = &pwm1_clk.common.hw,
1086                 [CLK_PWM2]              = &pwm2_clk.common.hw,
1087                 [CLK_PWM3]              = &pwm3_clk.common.hw,
1088                 [CLK_EFUSE]             = &efuse_clk.common.hw,
1089                 [CLK_UART0]             = &uart0_clk.common.hw,
1090                 [CLK_UART1]             = &uart1_clk.common.hw,
1091                 [CLK_THM0]              = &thm0_clk.common.hw,
1092                 [CLK_THM1]              = &thm1_clk.common.hw,
1093                 [CLK_THM2]              = &thm2_clk.common.hw,
1094                 [CLK_THM3]              = &thm3_clk.common.hw,
1095                 [CLK_AON_I2C]           = &aon_i2c_clk.common.hw,
1096                 [CLK_AON_IIS]           = &aon_iis_clk.common.hw,
1097                 [CLK_SCC]               = &scc_clk.common.hw,
1098                 [CLK_APCPU_DAP]         = &apcpu_dap_clk.common.hw,
1099                 [CLK_APCPU_DAP_MTCK]    = &apcpu_dap_mtck.common.hw,
1100                 [CLK_APCPU_TS]          = &apcpu_ts_clk.common.hw,
1101                 [CLK_DEBUG_TS]          = &debug_ts_clk.common.hw,
1102                 [CLK_DSI_TEST_S]        = &dsi_test_s.common.hw,
1103                 [CLK_DJTAG_TCK]         = &djtag_tck_clk.common.hw,
1104                 [CLK_DJTAG_TCK_HW]      = &djtag_tck_hw.common.hw,
1105                 [CLK_AON_TMR]           = &aon_tmr_clk.common.hw,
1106                 [CLK_AON_PMU]           = &aon_pmu_clk.common.hw,
1107                 [CLK_DEBOUNCE]          = &debounce_clk.common.hw,
1108                 [CLK_APCPU_PMU]         = &apcpu_pmu_clk.common.hw,
1109                 [CLK_TOP_DVFS]          = &top_dvfs_clk.common.hw,
1110                 [CLK_OTG_UTMI]          = &otg_utmi.common.hw,
1111                 [CLK_OTG_REF]           = &otg_ref_clk.common.hw,
1112                 [CLK_CSSYS]             = &cssys_clk.common.hw,
1113                 [CLK_CSSYS_PUB]         = &cssys_pub_clk.common.hw,
1114                 [CLK_CSSYS_APB]         = &cssys_apb_clk.common.hw,
1115                 [CLK_AP_AXI]            = &ap_axi_clk.common.hw,
1116                 [CLK_AP_MM]             = &ap_mm_clk.common.hw,
1117                 [CLK_SDIO2_2X]          = &sdio2_2x_clk.common.hw,
1118                 [CLK_ANALOG_IO_APB]     = &analog_io_apb.common.hw,
1119                 [CLK_DMC_REF_CLK]       = &dmc_ref_clk.common.hw,
1120                 [CLK_EMC]               = &emc_clk.common.hw,
1121                 [CLK_USB]               = &usb_clk.common.hw,
1122                 [CLK_26M_PMU]           = &pmu_26m_clk.common.hw,
1123         },
1124         .num    = CLK_AON_APB_NUM,
1125 };
1126
1127 static struct sprd_clk_desc ums512_aon_apb_desc = {
1128         .clk_clks       = ums512_aon_apb,
1129         .num_clk_clks   = ARRAY_SIZE(ums512_aon_apb),
1130         .hw_clks        = &ums512_aon_apb_hws,
1131 };
1132
1133 /* aon apb gates */
1134 static SPRD_SC_GATE_CLK_FW_NAME(rc100m_cal_eb, "rc100m-cal-eb", "ext-26m",
1135                                 0x0, 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0);
1136 static SPRD_SC_GATE_CLK_FW_NAME(djtag_tck_eb, "djtag-tck-eb", "ext-26m",
1137                                 0x0, 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
1138 static SPRD_SC_GATE_CLK_FW_NAME(djtag_eb, "djtag-eb", "ext-26m",
1139                                 0x0, 0x1000, BIT(3), CLK_IGNORE_UNUSED, 0);
1140 static SPRD_SC_GATE_CLK_FW_NAME(aux0_eb, "aux0-eb", "ext-26m",
1141                                 0x0, 0x1000, BIT(4), 0, 0);
1142 static SPRD_SC_GATE_CLK_FW_NAME(aux1_eb, "aux1-eb", "ext-26m",
1143                                 0x0, 0x1000, BIT(5), 0, 0);
1144 static SPRD_SC_GATE_CLK_FW_NAME(aux2_eb, "aux2-eb", "ext-26m",
1145                                 0x0, 0x1000, BIT(6), 0, 0);
1146 static SPRD_SC_GATE_CLK_FW_NAME(probe_eb, "probe-eb", "ext-26m",
1147                                 0x0, 0x1000, BIT(7), 0, 0);
1148 static SPRD_SC_GATE_CLK_FW_NAME(mm_eb, "mm-eb", "ext-26m",
1149                                 0x0, 0x1000, BIT(9), 0, 0);
1150 static SPRD_SC_GATE_CLK_FW_NAME(gpu_eb, "gpu-eb", "ext-26m",
1151                                 0x0, 0x1000, BIT(11), 0, 0);
1152 static SPRD_SC_GATE_CLK_FW_NAME(mspi_eb, "mspi-eb", "ext-26m",
1153                                 0x0, 0x1000, BIT(12), CLK_IGNORE_UNUSED, 0);
1154 static SPRD_SC_GATE_CLK_FW_NAME(apcpu_dap_eb, "apcpu-dap-eb", "ext-26m",
1155                                 0x0, 0x1000, BIT(14), CLK_IGNORE_UNUSED, 0);
1156 static SPRD_SC_GATE_CLK_FW_NAME(aon_cssys_eb, "aon-cssys-eb", "ext-26m",
1157                                 0x0, 0x1000, BIT(15), CLK_IGNORE_UNUSED, 0);
1158 static SPRD_SC_GATE_CLK_FW_NAME(cssys_apb_eb, "cssys-apb-eb", "ext-26m",
1159                                 0x0, 0x1000, BIT(16), CLK_IGNORE_UNUSED, 0);
1160 static SPRD_SC_GATE_CLK_FW_NAME(cssys_pub_eb, "cssys-pub-eb", "ext-26m",
1161                                 0x0, 0x1000, BIT(17), CLK_IGNORE_UNUSED, 0);
1162 static SPRD_SC_GATE_CLK_FW_NAME(sdphy_cfg_eb, "sdphy-cfg-eb", "ext-26m",
1163                                 0x0, 0x1000, BIT(19), 0, 0);
1164 static SPRD_SC_GATE_CLK_FW_NAME(sdphy_ref_eb, "sdphy-ref-eb", "ext-26m",
1165                                 0x0, 0x1000, BIT(20), 0, 0);
1166 static SPRD_SC_GATE_CLK_FW_NAME(efuse_eb, "efuse-eb", "ext-26m",
1167                                 0x4, 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0);
1168 static SPRD_SC_GATE_CLK_FW_NAME(gpio_eb, "gpio-eb", "ext-26m",
1169                                 0x4, 0x1000, BIT(1), CLK_IGNORE_UNUSED, 0);
1170 static SPRD_SC_GATE_CLK_FW_NAME(mbox_eb, "mbox-eb", "ext-26m",
1171                                 0x4, 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
1172 static SPRD_SC_GATE_CLK_FW_NAME(kpd_eb, "kpd-eb", "ext-26m",
1173                                 0x4, 0x1000, BIT(3), 0, 0);
1174 static SPRD_SC_GATE_CLK_FW_NAME(aon_syst_eb, "aon-syst-eb", "ext-26m",
1175                                 0x4, 0x1000, BIT(4), CLK_IGNORE_UNUSED, 0);
1176 static SPRD_SC_GATE_CLK_FW_NAME(ap_syst_eb, "ap-syst-eb", "ext-26m",
1177                                 0x4, 0x1000, BIT(5), CLK_IGNORE_UNUSED, 0);
1178 static SPRD_SC_GATE_CLK_FW_NAME(aon_tmr_eb, "aon-tmr-eb", "ext-26m",
1179                                 0x4, 0x1000, BIT(6), CLK_IGNORE_UNUSED, 0);
1180 static SPRD_SC_GATE_CLK_FW_NAME(otg_utmi_eb, "otg-utmi-eb", "ext-26m",
1181                                 0x4, 0x1000, BIT(8), CLK_IGNORE_UNUSED, 0);
1182 static SPRD_SC_GATE_CLK_FW_NAME(otg_phy_eb, "otg-phy-eb", "ext-26m",
1183                                 0x4, 0x1000, BIT(9), CLK_IGNORE_UNUSED, 0);
1184 static SPRD_SC_GATE_CLK_FW_NAME(splk_eb, "splk-eb", "ext-26m",
1185                                 0x4, 0x1000, BIT(10), CLK_IGNORE_UNUSED, 0);
1186 static SPRD_SC_GATE_CLK_FW_NAME(pin_eb, "pin-eb", "ext-26m",
1187                                 0x4, 0x1000, BIT(11), CLK_IGNORE_UNUSED, 0);
1188 static SPRD_SC_GATE_CLK_FW_NAME(ana_eb, "ana-eb", "ext-26m",
1189                                 0x4, 0x1000, BIT(12), CLK_IGNORE_UNUSED, 0);
1190 static SPRD_SC_GATE_CLK_FW_NAME(apcpu_ts0_eb, "apcpu-ts0-eb", "ext-26m",
1191                                 0x4, 0x1000, BIT(17), CLK_IGNORE_UNUSED, 0);
1192 static SPRD_SC_GATE_CLK_FW_NAME(apb_busmon_eb, "apb-busmon-eb", "ext-26m",
1193                                 0x4, 0x1000, BIT(18), CLK_IGNORE_UNUSED, 0);
1194 static SPRD_SC_GATE_CLK_FW_NAME(aon_iis_eb, "aon-iis-eb", "ext-26m",
1195                                 0x4, 0x1000, BIT(19), CLK_IGNORE_UNUSED, 0);
1196 static SPRD_SC_GATE_CLK_FW_NAME(scc_eb, "scc-eb", "ext-26m",
1197                                 0x4, 0x1000, BIT(20), CLK_IGNORE_UNUSED, 0);
1198 static SPRD_SC_GATE_CLK_FW_NAME(thm0_eb, "thm0-eb", "ext-26m",
1199                                 0x8, 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0);
1200 static SPRD_SC_GATE_CLK_FW_NAME(thm1_eb, "thm1-eb", "ext-26m",
1201                                 0x8, 0x1000, BIT(1), CLK_IGNORE_UNUSED, 0);
1202 static SPRD_SC_GATE_CLK_FW_NAME(thm2_eb, "thm2-eb", "ext-26m",
1203                                 0x8, 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
1204 static SPRD_SC_GATE_CLK_FW_NAME(asim_top_eb, "asim-top", "ext-26m",
1205                                 0x8, 0x1000, BIT(3), CLK_IGNORE_UNUSED, 0);
1206 static SPRD_SC_GATE_CLK_FW_NAME(i2c_eb, "i2c-eb", "ext-26m",
1207                                 0x8, 0x1000, BIT(7), CLK_IGNORE_UNUSED, 0);
1208 static SPRD_SC_GATE_CLK_FW_NAME(pmu_eb, "pmu-eb", "ext-26m",
1209                                 0x8, 0x1000, BIT(8), CLK_IGNORE_UNUSED, 0);
1210 static SPRD_SC_GATE_CLK_FW_NAME(adi_eb, "adi-eb", "ext-26m",
1211                                 0x8, 0x1000, BIT(9), CLK_IGNORE_UNUSED, 0);
1212 static SPRD_SC_GATE_CLK_FW_NAME(eic_eb, "eic-eb", "ext-26m",
1213                                 0x8, 0x1000, BIT(10), CLK_IGNORE_UNUSED, 0);
1214 static SPRD_SC_GATE_CLK_FW_NAME(ap_intc0_eb, "ap-intc0-eb", "ext-26m",
1215                                 0x8, 0x1000, BIT(11), CLK_IGNORE_UNUSED, 0);
1216 static SPRD_SC_GATE_CLK_FW_NAME(ap_intc1_eb, "ap-intc1-eb", "ext-26m",
1217                                 0x8, 0x1000, BIT(12), CLK_IGNORE_UNUSED, 0);
1218 static SPRD_SC_GATE_CLK_FW_NAME(ap_intc2_eb, "ap-intc2-eb", "ext-26m",
1219                                 0x8, 0x1000, BIT(13), CLK_IGNORE_UNUSED, 0);
1220 static SPRD_SC_GATE_CLK_FW_NAME(ap_intc3_eb, "ap-intc3-eb", "ext-26m",
1221                                 0x8, 0x1000, BIT(14), CLK_IGNORE_UNUSED, 0);
1222 static SPRD_SC_GATE_CLK_FW_NAME(ap_intc4_eb, "ap-intc4-eb", "ext-26m",
1223                                 0x8, 0x1000, BIT(15), CLK_IGNORE_UNUSED, 0);
1224 static SPRD_SC_GATE_CLK_FW_NAME(ap_intc5_eb, "ap-intc5-eb", "ext-26m",
1225                                 0x8, 0x1000, BIT(16), CLK_IGNORE_UNUSED, 0);
1226 static SPRD_SC_GATE_CLK_FW_NAME(audcp_intc_eb, "audcp-intc-eb", "ext-26m",
1227                                 0x8, 0x1000, BIT(17), CLK_IGNORE_UNUSED, 0);
1228 static SPRD_SC_GATE_CLK_FW_NAME(ap_tmr0_eb, "ap-tmr0-eb", "ext-26m",
1229                                 0x8, 0x1000, BIT(22), CLK_IGNORE_UNUSED, 0);
1230 static SPRD_SC_GATE_CLK_FW_NAME(ap_tmr1_eb, "ap-tmr1-eb", "ext-26m",
1231                                 0x8, 0x1000, BIT(23), CLK_IGNORE_UNUSED, 0);
1232 static SPRD_SC_GATE_CLK_FW_NAME(ap_tmr2_eb, "ap-tmr2-eb", "ext-26m",
1233                                 0x8, 0x1000, BIT(24), CLK_IGNORE_UNUSED, 0);
1234 static SPRD_SC_GATE_CLK_FW_NAME(pwm0_eb, "pwm0-eb", "ext-26m",
1235                                 0x8, 0x1000, BIT(25), 0, 0);
1236 static SPRD_SC_GATE_CLK_FW_NAME(pwm1_eb, "pwm1-eb", "ext-26m",
1237                                 0x8, 0x1000, BIT(26), 0, 0);
1238 static SPRD_SC_GATE_CLK_FW_NAME(pwm2_eb, "pwm2-eb", "ext-26m",
1239                                 0x8, 0x1000, BIT(27), 0, 0);
1240 static SPRD_SC_GATE_CLK_FW_NAME(pwm3_eb, "pwm3-eb", "ext-26m",
1241                                 0x8, 0x1000, BIT(28), 0, 0);
1242 static SPRD_SC_GATE_CLK_FW_NAME(ap_wdg_eb, "ap-wdg-eb", "ext-26m",
1243                                 0x8, 0x1000, BIT(29), 0, 0);
1244 static SPRD_SC_GATE_CLK_FW_NAME(apcpu_wdg_eb, "apcpu-wdg-eb", "ext-26m",
1245                                 0x8, 0x1000, BIT(30), 0, 0);
1246 static SPRD_SC_GATE_CLK_FW_NAME(serdes_eb, "serdes-eb", "ext-26m",
1247                                 0x8, 0x1000, BIT(31), 0, 0);
1248 static SPRD_SC_GATE_CLK_FW_NAME(arch_rtc_eb, "arch-rtc-eb", "ext-26m",
1249                                 0x18, 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0);
1250 static SPRD_SC_GATE_CLK_FW_NAME(kpd_rtc_eb, "kpd-rtc-eb", "ext-26m",
1251                                 0x18, 0x1000, BIT(1), CLK_IGNORE_UNUSED, 0);
1252 static SPRD_SC_GATE_CLK_FW_NAME(aon_syst_rtc_eb, "aon-syst-rtc-eb", "ext-26m",
1253                                 0x18, 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
1254 static SPRD_SC_GATE_CLK_FW_NAME(ap_syst_rtc_eb, "ap-syst-rtc-eb", "ext-26m",
1255                                 0x18, 0x1000, BIT(3), CLK_IGNORE_UNUSED, 0);
1256 static SPRD_SC_GATE_CLK_FW_NAME(aon_tmr_rtc_eb, "aon-tmr-rtc-eb", "ext-26m",
1257                                 0x18, 0x1000, BIT(4), CLK_IGNORE_UNUSED, 0);
1258 static SPRD_SC_GATE_CLK_FW_NAME(eic_rtc_eb, "eic-rtc-eb", "ext-26m",
1259                                 0x18, 0x1000, BIT(5), CLK_IGNORE_UNUSED, 0);
1260 static SPRD_SC_GATE_CLK_FW_NAME(eic_rtcdv5_eb, "eic-rtcdv5-eb", "ext-26m",
1261                                 0x18, 0x1000, BIT(6), CLK_IGNORE_UNUSED, 0);
1262 static SPRD_SC_GATE_CLK_FW_NAME(ap_wdg_rtc_eb, "ap-wdg-rtc-eb", "ext-26m",
1263                                 0x18, 0x1000, BIT(7), CLK_IGNORE_UNUSED, 0);
1264 static SPRD_SC_GATE_CLK_FW_NAME(ac_wdg_rtc_eb, "ac-wdg-rtc-eb", "ext-26m",
1265                                 0x18, 0x1000, BIT(8), CLK_IGNORE_UNUSED, 0);
1266 static SPRD_SC_GATE_CLK_FW_NAME(ap_tmr0_rtc_eb, "ap-tmr0-rtc-eb", "ext-26m",
1267                                 0x18, 0x1000, BIT(9), CLK_IGNORE_UNUSED, 0);
1268 static SPRD_SC_GATE_CLK_FW_NAME(ap_tmr1_rtc_eb, "ap-tmr1-rtc-eb", "ext-26m",
1269                                 0x18, 0x1000, BIT(10), CLK_IGNORE_UNUSED, 0);
1270 static SPRD_SC_GATE_CLK_FW_NAME(ap_tmr2_rtc_eb, "ap-tmr2-rtc-eb", "ext-26m",
1271                                 0x18, 0x1000, BIT(11), CLK_IGNORE_UNUSED, 0);
1272 static SPRD_SC_GATE_CLK_FW_NAME(dcxo_lc_rtc_eb, "dcxo-lc-rtc-eb", "ext-26m",
1273                                 0x18, 0x1000, BIT(12), CLK_IGNORE_UNUSED, 0);
1274 static SPRD_SC_GATE_CLK_FW_NAME(bb_cal_rtc_eb, "bb-cal-rtc-eb", "ext-26m",
1275                                 0x18, 0x1000, BIT(13), CLK_IGNORE_UNUSED, 0);
1276 static SPRD_SC_GATE_CLK_FW_NAME(ap_emmc_rtc_eb, "ap-emmc-rtc-eb", "ext-26m",
1277                                 0x18, 0x1000, BIT(14), CLK_IGNORE_UNUSED, 0);
1278 static SPRD_SC_GATE_CLK_FW_NAME(ap_sdio0_rtc_eb, "ap-sdio0-rtc-eb", "ext-26m",
1279                                 0x18, 0x1000, BIT(15), CLK_IGNORE_UNUSED, 0);
1280 static SPRD_SC_GATE_CLK_FW_NAME(ap_sdio1_rtc_eb, "ap-sdio1-rtc-eb", "ext-26m",
1281                                 0x18, 0x1000, BIT(16), CLK_IGNORE_UNUSED, 0);
1282 static SPRD_SC_GATE_CLK_FW_NAME(ap_sdio2_rtc_eb, "ap-sdio2-rtc-eb", "ext-26m",
1283                                 0x18, 0x1000, BIT(17), CLK_IGNORE_UNUSED, 0);
1284 static SPRD_SC_GATE_CLK_FW_NAME(dsi_csi_test_eb, "dsi-csi-test-eb", "ext-26m",
1285                                 0x138, 0x1000, BIT(8), 0, 0);
1286 static SPRD_SC_GATE_CLK_FW_NAME(djtag_tck_en, "djtag-tck-en", "ext-26m",
1287                                 0x138, 0x1000, BIT(9), CLK_IGNORE_UNUSED, 0);
1288 static SPRD_SC_GATE_CLK_FW_NAME(dphy_ref_eb, "dphy-ref-eb", "ext-26m",
1289                                 0x138, 0x1000, BIT(10), CLK_IGNORE_UNUSED, 0);
1290 static SPRD_SC_GATE_CLK_FW_NAME(dmc_ref_eb, "dmc-ref-eb", "ext-26m",
1291                                 0x138, 0x1000, BIT(11), CLK_IGNORE_UNUSED, 0);
1292 static SPRD_SC_GATE_CLK_FW_NAME(otg_ref_eb, "otg-ref-eb", "ext-26m",
1293                                 0x138, 0x1000, BIT(12), CLK_IGNORE_UNUSED, 0);
1294 static SPRD_SC_GATE_CLK_FW_NAME(tsen_eb, "tsen-eb", "ext-26m",
1295                                 0x138, 0x1000, BIT(13), 0, 0);
1296 static SPRD_SC_GATE_CLK_FW_NAME(tmr_eb, "tmr-eb", "ext-26m",
1297                                 0x138, 0x1000, BIT(14), CLK_IGNORE_UNUSED, 0);
1298 static SPRD_SC_GATE_CLK_FW_NAME(rc100m_ref_eb, "rc100m-ref-eb", "ext-26m",
1299                                 0x138, 0x1000, BIT(15), CLK_IGNORE_UNUSED, 0);
1300 static SPRD_SC_GATE_CLK_FW_NAME(rc100m_fdk_eb, "rc100m-fdk-eb", "ext-26m",
1301                                 0x138, 0x1000, BIT(16), CLK_IGNORE_UNUSED, 0);
1302 static SPRD_SC_GATE_CLK_FW_NAME(debounce_eb, "debounce-eb", "ext-26m",
1303                                 0x138, 0x1000, BIT(17), CLK_IGNORE_UNUSED, 0);
1304 static SPRD_SC_GATE_CLK_FW_NAME(det_32k_eb, "det-32k-eb", "ext-26m",
1305                                 0x138, 0x1000, BIT(18), CLK_IGNORE_UNUSED, 0);
1306 static SPRD_SC_GATE_CLK_FW_NAME(top_cssys_en, "top-cssys-en", "ext-26m",
1307                                 0x13c, 0x1000, BIT(0), 0, 0);
1308 static SPRD_SC_GATE_CLK_FW_NAME(ap_axi_en, "ap-axi-en", "ext-26m",
1309                                 0x13c, 0x1000, BIT(1), CLK_IGNORE_UNUSED, 0);
1310 static SPRD_SC_GATE_CLK_FW_NAME(sdio0_2x_en, "sdio0-2x-en", "ext-26m",
1311                                 0x13c, 0x1000, BIT(2), 0, 0);
1312 static SPRD_SC_GATE_CLK_FW_NAME(sdio0_1x_en, "sdio0-1x-en", "ext-26m",
1313                                 0x13c, 0x1000, BIT(3), 0, 0);
1314 static SPRD_SC_GATE_CLK_FW_NAME(sdio1_2x_en, "sdio1-2x-en", "ext-26m",
1315                                 0x13c, 0x1000, BIT(4), 0, 0);
1316 static SPRD_SC_GATE_CLK_FW_NAME(sdio1_1x_en, "sdio1-1x-en", "ext-26m",
1317                                 0x13c, 0x1000, BIT(5), 0, 0);
1318 static SPRD_SC_GATE_CLK_FW_NAME(sdio2_2x_en, "sdio2-2x-en", "ext-26m",
1319                                 0x13c, 0x1000, BIT(6), 0, 0);
1320 static SPRD_SC_GATE_CLK_FW_NAME(sdio2_1x_en, "sdio2-1x-en", "ext-26m",
1321                                 0x13c, 0x1000, BIT(7), 0, 0);
1322 static SPRD_SC_GATE_CLK_FW_NAME(emmc_2x_en, "emmc-2x-en", "ext-26m",
1323                                 0x13c, 0x1000, BIT(8), 0, 0);
1324 static SPRD_SC_GATE_CLK_FW_NAME(emmc_1x_en, "emmc-1x-en", "ext-26m",
1325                                 0x13c, 0x1000, BIT(9), 0, 0);
1326 static SPRD_SC_GATE_CLK_FW_NAME(pll_test_en, "pll-test-en", "ext-26m",
1327                                 0x13c, 0x1000, BIT(14), 0, 0);
1328 static SPRD_SC_GATE_CLK_FW_NAME(cphy_cfg_en, "cphy-cfg-en", "ext-26m",
1329                                 0x13c, 0x1000, BIT(15), 0, 0);
1330 static SPRD_SC_GATE_CLK_FW_NAME(debug_ts_en, "debug-ts-en", "ext-26m",
1331                                 0x13c, 0x1000, BIT(18), 0, 0);
1332 static SPRD_SC_GATE_CLK_FW_NAME(access_aud_en, "access-aud-en",
1333                                 "ext-26m", 0x14c, 0x1000, BIT(0), 0, 0);
1334
1335 static struct sprd_clk_common *ums512_aon_gate[] = {
1336         /* address base is 0x327d0000 */
1337         &rc100m_cal_eb.common,
1338         &djtag_tck_eb.common,
1339         &djtag_eb.common,
1340         &aux0_eb.common,
1341         &aux1_eb.common,
1342         &aux2_eb.common,
1343         &probe_eb.common,
1344         &mm_eb.common,
1345         &gpu_eb.common,
1346         &mspi_eb.common,
1347         &apcpu_dap_eb.common,
1348         &aon_cssys_eb.common,
1349         &cssys_apb_eb.common,
1350         &cssys_pub_eb.common,
1351         &sdphy_cfg_eb.common,
1352         &sdphy_ref_eb.common,
1353         &efuse_eb.common,
1354         &gpio_eb.common,
1355         &mbox_eb.common,
1356         &kpd_eb.common,
1357         &aon_syst_eb.common,
1358         &ap_syst_eb.common,
1359         &aon_tmr_eb.common,
1360         &otg_utmi_eb.common,
1361         &otg_phy_eb.common,
1362         &splk_eb.common,
1363         &pin_eb.common,
1364         &ana_eb.common,
1365         &apcpu_ts0_eb.common,
1366         &apb_busmon_eb.common,
1367         &aon_iis_eb.common,
1368         &scc_eb.common,
1369         &thm0_eb.common,
1370         &thm1_eb.common,
1371         &thm2_eb.common,
1372         &asim_top_eb.common,
1373         &i2c_eb.common,
1374         &pmu_eb.common,
1375         &adi_eb.common,
1376         &eic_eb.common,
1377         &ap_intc0_eb.common,
1378         &ap_intc1_eb.common,
1379         &ap_intc2_eb.common,
1380         &ap_intc3_eb.common,
1381         &ap_intc4_eb.common,
1382         &ap_intc5_eb.common,
1383         &audcp_intc_eb.common,
1384         &ap_tmr0_eb.common,
1385         &ap_tmr1_eb.common,
1386         &ap_tmr2_eb.common,
1387         &pwm0_eb.common,
1388         &pwm1_eb.common,
1389         &pwm2_eb.common,
1390         &pwm3_eb.common,
1391         &ap_wdg_eb.common,
1392         &apcpu_wdg_eb.common,
1393         &serdes_eb.common,
1394         &arch_rtc_eb.common,
1395         &kpd_rtc_eb.common,
1396         &aon_syst_rtc_eb.common,
1397         &ap_syst_rtc_eb.common,
1398         &aon_tmr_rtc_eb.common,
1399         &eic_rtc_eb.common,
1400         &eic_rtcdv5_eb.common,
1401         &ap_wdg_rtc_eb.common,
1402         &ac_wdg_rtc_eb.common,
1403         &ap_tmr0_rtc_eb.common,
1404         &ap_tmr1_rtc_eb.common,
1405         &ap_tmr2_rtc_eb.common,
1406         &dcxo_lc_rtc_eb.common,
1407         &bb_cal_rtc_eb.common,
1408         &ap_emmc_rtc_eb.common,
1409         &ap_sdio0_rtc_eb.common,
1410         &ap_sdio1_rtc_eb.common,
1411         &ap_sdio2_rtc_eb.common,
1412         &dsi_csi_test_eb.common,
1413         &djtag_tck_en.common,
1414         &dphy_ref_eb.common,
1415         &dmc_ref_eb.common,
1416         &otg_ref_eb.common,
1417         &tsen_eb.common,
1418         &tmr_eb.common,
1419         &rc100m_ref_eb.common,
1420         &rc100m_fdk_eb.common,
1421         &debounce_eb.common,
1422         &det_32k_eb.common,
1423         &top_cssys_en.common,
1424         &ap_axi_en.common,
1425         &sdio0_2x_en.common,
1426         &sdio0_1x_en.common,
1427         &sdio1_2x_en.common,
1428         &sdio1_1x_en.common,
1429         &sdio2_2x_en.common,
1430         &sdio2_1x_en.common,
1431         &emmc_2x_en.common,
1432         &emmc_1x_en.common,
1433         &pll_test_en.common,
1434         &cphy_cfg_en.common,
1435         &debug_ts_en.common,
1436         &access_aud_en.common,
1437 };
1438
1439 static struct clk_hw_onecell_data ums512_aon_gate_hws = {
1440         .hws    = {
1441                 [CLK_RC100M_CAL_EB]     = &rc100m_cal_eb.common.hw,
1442                 [CLK_DJTAG_TCK_EB]      = &djtag_tck_eb.common.hw,
1443                 [CLK_DJTAG_EB]          = &djtag_eb.common.hw,
1444                 [CLK_AUX0_EB]           = &aux0_eb.common.hw,
1445                 [CLK_AUX1_EB]           = &aux1_eb.common.hw,
1446                 [CLK_AUX2_EB]           = &aux2_eb.common.hw,
1447                 [CLK_PROBE_EB]          = &probe_eb.common.hw,
1448                 [CLK_MM_EB]             = &mm_eb.common.hw,
1449                 [CLK_GPU_EB]            = &gpu_eb.common.hw,
1450                 [CLK_MSPI_EB]           = &mspi_eb.common.hw,
1451                 [CLK_APCPU_DAP_EB]      = &apcpu_dap_eb.common.hw,
1452                 [CLK_AON_CSSYS_EB]      = &aon_cssys_eb.common.hw,
1453                 [CLK_CSSYS_APB_EB]      = &cssys_apb_eb.common.hw,
1454                 [CLK_CSSYS_PUB_EB]      = &cssys_pub_eb.common.hw,
1455                 [CLK_SDPHY_CFG_EB]      = &sdphy_cfg_eb.common.hw,
1456                 [CLK_SDPHY_REF_EB]      = &sdphy_ref_eb.common.hw,
1457                 [CLK_EFUSE_EB]          = &efuse_eb.common.hw,
1458                 [CLK_GPIO_EB]           = &gpio_eb.common.hw,
1459                 [CLK_MBOX_EB]           = &mbox_eb.common.hw,
1460                 [CLK_KPD_EB]            = &kpd_eb.common.hw,
1461                 [CLK_AON_SYST_EB]       = &aon_syst_eb.common.hw,
1462                 [CLK_AP_SYST_EB]        = &ap_syst_eb.common.hw,
1463                 [CLK_AON_TMR_EB]        = &aon_tmr_eb.common.hw,
1464                 [CLK_OTG_UTMI_EB]       = &otg_utmi_eb.common.hw,
1465                 [CLK_OTG_PHY_EB]        = &otg_phy_eb.common.hw,
1466                 [CLK_SPLK_EB]           = &splk_eb.common.hw,
1467                 [CLK_PIN_EB]            = &pin_eb.common.hw,
1468                 [CLK_ANA_EB]            = &ana_eb.common.hw,
1469                 [CLK_APCPU_TS0_EB]      = &apcpu_ts0_eb.common.hw,
1470                 [CLK_APB_BUSMON_EB]     = &apb_busmon_eb.common.hw,
1471                 [CLK_AON_IIS_EB]        = &aon_iis_eb.common.hw,
1472                 [CLK_SCC_EB]            = &scc_eb.common.hw,
1473                 [CLK_THM0_EB]           = &thm0_eb.common.hw,
1474                 [CLK_THM1_EB]           = &thm1_eb.common.hw,
1475                 [CLK_THM2_EB]           = &thm2_eb.common.hw,
1476                 [CLK_ASIM_TOP_EB]       = &asim_top_eb.common.hw,
1477                 [CLK_I2C_EB]            = &i2c_eb.common.hw,
1478                 [CLK_PMU_EB]            = &pmu_eb.common.hw,
1479                 [CLK_ADI_EB]            = &adi_eb.common.hw,
1480                 [CLK_EIC_EB]            = &eic_eb.common.hw,
1481                 [CLK_AP_INTC0_EB]       = &ap_intc0_eb.common.hw,
1482                 [CLK_AP_INTC1_EB]       = &ap_intc1_eb.common.hw,
1483                 [CLK_AP_INTC2_EB]       = &ap_intc2_eb.common.hw,
1484                 [CLK_AP_INTC3_EB]       = &ap_intc3_eb.common.hw,
1485                 [CLK_AP_INTC4_EB]       = &ap_intc4_eb.common.hw,
1486                 [CLK_AP_INTC5_EB]       = &ap_intc5_eb.common.hw,
1487                 [CLK_AUDCP_INTC_EB]     = &audcp_intc_eb.common.hw,
1488                 [CLK_AP_TMR0_EB]        = &ap_tmr0_eb.common.hw,
1489                 [CLK_AP_TMR1_EB]        = &ap_tmr1_eb.common.hw,
1490                 [CLK_AP_TMR2_EB]        = &ap_tmr2_eb.common.hw,
1491                 [CLK_PWM0_EB]           = &pwm0_eb.common.hw,
1492                 [CLK_PWM1_EB]           = &pwm1_eb.common.hw,
1493                 [CLK_PWM2_EB]           = &pwm2_eb.common.hw,
1494                 [CLK_PWM3_EB]           = &pwm3_eb.common.hw,
1495                 [CLK_AP_WDG_EB]         = &ap_wdg_eb.common.hw,
1496                 [CLK_APCPU_WDG_EB]      = &apcpu_wdg_eb.common.hw,
1497                 [CLK_SERDES_EB]         = &serdes_eb.common.hw,
1498                 [CLK_ARCH_RTC_EB]       = &arch_rtc_eb.common.hw,
1499                 [CLK_KPD_RTC_EB]        = &kpd_rtc_eb.common.hw,
1500                 [CLK_AON_SYST_RTC_EB]   = &aon_syst_rtc_eb.common.hw,
1501                 [CLK_AP_SYST_RTC_EB]    = &ap_syst_rtc_eb.common.hw,
1502                 [CLK_AON_TMR_RTC_EB]    = &aon_tmr_rtc_eb.common.hw,
1503                 [CLK_EIC_RTC_EB]        = &eic_rtc_eb.common.hw,
1504                 [CLK_EIC_RTCDV5_EB]     = &eic_rtcdv5_eb.common.hw,
1505                 [CLK_AP_WDG_RTC_EB]     = &ap_wdg_rtc_eb.common.hw,
1506                 [CLK_AC_WDG_RTC_EB]     = &ac_wdg_rtc_eb.common.hw,
1507                 [CLK_AP_TMR0_RTC_EB]    = &ap_tmr0_rtc_eb.common.hw,
1508                 [CLK_AP_TMR1_RTC_EB]    = &ap_tmr1_rtc_eb.common.hw,
1509                 [CLK_AP_TMR2_RTC_EB]    = &ap_tmr2_rtc_eb.common.hw,
1510                 [CLK_DCXO_LC_RTC_EB]    = &dcxo_lc_rtc_eb.common.hw,
1511                 [CLK_BB_CAL_RTC_EB]     = &bb_cal_rtc_eb.common.hw,
1512                 [CLK_AP_EMMC_RTC_EB]    = &ap_emmc_rtc_eb.common.hw,
1513                 [CLK_AP_SDIO0_RTC_EB]   = &ap_sdio0_rtc_eb.common.hw,
1514                 [CLK_AP_SDIO1_RTC_EB]   = &ap_sdio1_rtc_eb.common.hw,
1515                 [CLK_AP_SDIO2_RTC_EB]   = &ap_sdio2_rtc_eb.common.hw,
1516                 [CLK_DSI_CSI_TEST_EB]   = &dsi_csi_test_eb.common.hw,
1517                 [CLK_DJTAG_TCK_EN]      = &djtag_tck_en.common.hw,
1518                 [CLK_DPHY_REF_EB]       = &dphy_ref_eb.common.hw,
1519                 [CLK_DMC_REF_EB]        = &dmc_ref_eb.common.hw,
1520                 [CLK_OTG_REF_EB]        = &otg_ref_eb.common.hw,
1521                 [CLK_TSEN_EB]           = &tsen_eb.common.hw,
1522                 [CLK_TMR_EB]            = &tmr_eb.common.hw,
1523                 [CLK_RC100M_REF_EB]     = &rc100m_ref_eb.common.hw,
1524                 [CLK_RC100M_FDK_EB]     = &rc100m_fdk_eb.common.hw,
1525                 [CLK_DEBOUNCE_EB]       = &debounce_eb.common.hw,
1526                 [CLK_DET_32K_EB]        = &det_32k_eb.common.hw,
1527                 [CLK_TOP_CSSYS_EB]      = &top_cssys_en.common.hw,
1528                 [CLK_AP_AXI_EN]         = &ap_axi_en.common.hw,
1529                 [CLK_SDIO0_2X_EN]       = &sdio0_2x_en.common.hw,
1530                 [CLK_SDIO0_1X_EN]       = &sdio0_1x_en.common.hw,
1531                 [CLK_SDIO1_2X_EN]       = &sdio1_2x_en.common.hw,
1532                 [CLK_SDIO1_1X_EN]       = &sdio1_1x_en.common.hw,
1533                 [CLK_SDIO2_2X_EN]       = &sdio2_2x_en.common.hw,
1534                 [CLK_SDIO2_1X_EN]       = &sdio2_1x_en.common.hw,
1535                 [CLK_EMMC_2X_EN]        = &emmc_2x_en.common.hw,
1536                 [CLK_EMMC_1X_EN]        = &emmc_1x_en.common.hw,
1537                 [CLK_PLL_TEST_EN]       = &pll_test_en.common.hw,
1538                 [CLK_CPHY_CFG_EN]       = &cphy_cfg_en.common.hw,
1539                 [CLK_DEBUG_TS_EN]       = &debug_ts_en.common.hw,
1540                 [CLK_ACCESS_AUD_EN]     = &access_aud_en.common.hw,
1541         },
1542         .num    = CLK_AON_APB_GATE_NUM,
1543 };
1544
1545 static struct sprd_clk_desc ums512_aon_gate_desc = {
1546         .clk_clks       = ums512_aon_gate,
1547         .num_clk_clks   = ARRAY_SIZE(ums512_aon_gate),
1548         .hw_clks        = &ums512_aon_gate_hws,
1549 };
1550
1551 /* audcp apb gates */
1552 /* Audcp apb clocks configure CLK_IGNORE_UNUSED because these clocks may be
1553  * controlled by audcp sys at the same time. It may be cause an execption if
1554  * kernel gates these clock.
1555  */
1556 static SPRD_SC_GATE_CLK_HW(audcp_wdg_eb, "audcp-wdg-eb",
1557                            &access_aud_en.common.hw, 0x0, 0x100, BIT(1),
1558                            CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON);
1559 static SPRD_SC_GATE_CLK_HW(audcp_rtc_wdg_eb, "audcp-rtc-wdg-eb",
1560                            &access_aud_en.common.hw, 0x0, 0x100, BIT(2),
1561                            CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON);
1562 static SPRD_SC_GATE_CLK_HW(audcp_tmr0_eb, "audcp-tmr0-eb",
1563                            &access_aud_en.common.hw, 0x0, 0x100, BIT(5),
1564                            CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON);
1565 static SPRD_SC_GATE_CLK_HW(audcp_tmr1_eb, "audcp-tmr1-eb",
1566                            &access_aud_en.common.hw, 0x0, 0x100, BIT(6),
1567                            CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON);
1568
1569 static struct sprd_clk_common *ums512_audcpapb_gate[] = {
1570         /* address base is 0x3350d000 */
1571         &audcp_wdg_eb.common,
1572         &audcp_rtc_wdg_eb.common,
1573         &audcp_tmr0_eb.common,
1574         &audcp_tmr1_eb.common,
1575 };
1576
1577 static struct clk_hw_onecell_data ums512_audcpapb_gate_hws = {
1578         .hws    = {
1579                 [CLK_AUDCP_WDG_EB]      = &audcp_wdg_eb.common.hw,
1580                 [CLK_AUDCP_RTC_WDG_EB]  = &audcp_rtc_wdg_eb.common.hw,
1581                 [CLK_AUDCP_TMR0_EB]     = &audcp_tmr0_eb.common.hw,
1582                 [CLK_AUDCP_TMR1_EB]     = &audcp_tmr1_eb.common.hw,
1583         },
1584         .num    = CLK_AUDCP_APB_GATE_NUM,
1585 };
1586
1587 static const struct sprd_clk_desc ums512_audcpapb_gate_desc = {
1588         .clk_clks       = ums512_audcpapb_gate,
1589         .num_clk_clks   = ARRAY_SIZE(ums512_audcpapb_gate),
1590         .hw_clks        = &ums512_audcpapb_gate_hws,
1591 };
1592
1593 /* audcp ahb gates */
1594 /* Audcp aphb clocks configure CLK_IGNORE_UNUSED because these clocks may be
1595  * controlled by audcp sys at the same time. It may be cause an execption if
1596  * kernel gates these clock.
1597  */
1598 static SPRD_SC_GATE_CLK_HW(audcp_iis0_eb, "audcp-iis0-eb",
1599                            &access_aud_en.common.hw, 0x0, 0x100, BIT(0),
1600                            CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON);
1601 static SPRD_SC_GATE_CLK_HW(audcp_iis1_eb, "audcp-iis1-eb",
1602                            &access_aud_en.common.hw, 0x0, 0x100, BIT(1),
1603                            CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON);
1604 static SPRD_SC_GATE_CLK_HW(audcp_iis2_eb, "audcp-iis2-eb",
1605                            &access_aud_en.common.hw, 0x0, 0x100, BIT(2),
1606                            CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON);
1607 static SPRD_SC_GATE_CLK_HW(audcp_uart_eb, "audcp-uart-eb",
1608                            &access_aud_en.common.hw, 0x0, 0x100, BIT(4),
1609                            CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON);
1610 static SPRD_SC_GATE_CLK_HW(audcp_dma_cp_eb, "audcp-dma-cp-eb",
1611                            &access_aud_en.common.hw, 0x0, 0x100, BIT(5),
1612                            CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON);
1613 static SPRD_SC_GATE_CLK_HW(audcp_dma_ap_eb, "audcp-dma-ap-eb",
1614                            &access_aud_en.common.hw, 0x0, 0x100, BIT(6),
1615                            CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON);
1616 static SPRD_SC_GATE_CLK_HW(audcp_src48k_eb, "audcp-src48k-eb",
1617                            &access_aud_en.common.hw, 0x0, 0x100, BIT(10),
1618                            CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON);
1619 static SPRD_SC_GATE_CLK_HW(audcp_mcdt_eb, "audcp-mcdt-eb",
1620                            &access_aud_en.common.hw, 0x0, 0x100, BIT(12),
1621                            CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON);
1622 static SPRD_SC_GATE_CLK_HW(audcp_vbcifd_eb, "audcp-vbcifd-eb",
1623                            &access_aud_en.common.hw, 0x0, 0x100, BIT(13),
1624                            CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON);
1625 static SPRD_SC_GATE_CLK_HW(audcp_vbc_eb, "audcp-vbc-eb",
1626                            &access_aud_en.common.hw, 0x0, 0x100, BIT(14),
1627                            CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON);
1628 static SPRD_SC_GATE_CLK_HW(audcp_splk_eb,  "audcp-splk-eb",
1629                            &access_aud_en.common.hw, 0x0, 0x100, BIT(15),
1630                            CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON);
1631 static SPRD_SC_GATE_CLK_HW(audcp_icu_eb, "audcp-icu-eb",
1632                            &access_aud_en.common.hw, 0x0, 0x100, BIT(16),
1633                            CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON);
1634 static SPRD_SC_GATE_CLK_HW(dma_ap_ashb_eb, "dma-ap-ashb-eb",
1635                            &access_aud_en.common.hw, 0x0, 0x100, BIT(17),
1636                            CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON);
1637 static SPRD_SC_GATE_CLK_HW(dma_cp_ashb_eb, "dma-cp-ashb-eb",
1638                            &access_aud_en.common.hw, 0x0, 0x100, BIT(18),
1639                            CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON);
1640 static SPRD_SC_GATE_CLK_HW(audcp_aud_eb, "audcp-aud-eb",
1641                            &access_aud_en.common.hw, 0x0, 0x100, BIT(19),
1642                            CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON);
1643 static SPRD_SC_GATE_CLK_HW(audcp_vbc_24m_eb, "audcp-vbc-24m-eb",
1644                            &access_aud_en.common.hw, 0x0, 0x100, BIT(21),
1645                            CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON);
1646 static SPRD_SC_GATE_CLK_HW(audcp_tmr_26m_eb, "audcp-tmr-26m-eb",
1647                            &access_aud_en.common.hw, 0x0, 0x100, BIT(22),
1648                            CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON);
1649 static SPRD_SC_GATE_CLK_HW(audcp_dvfs_ashb_eb, "audcp-dvfs-ashb-eb",
1650                            &access_aud_en.common.hw, 0x0, 0x100, BIT(23),
1651                            CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON);
1652
1653 static struct sprd_clk_common *ums512_audcpahb_gate[] = {
1654         /* address base is 0x335e0000 */
1655         &audcp_iis0_eb.common,
1656         &audcp_iis1_eb.common,
1657         &audcp_iis2_eb.common,
1658         &audcp_uart_eb.common,
1659         &audcp_dma_cp_eb.common,
1660         &audcp_dma_ap_eb.common,
1661         &audcp_src48k_eb.common,
1662         &audcp_mcdt_eb.common,
1663         &audcp_vbcifd_eb.common,
1664         &audcp_vbc_eb.common,
1665         &audcp_splk_eb.common,
1666         &audcp_icu_eb.common,
1667         &dma_ap_ashb_eb.common,
1668         &dma_cp_ashb_eb.common,
1669         &audcp_aud_eb.common,
1670         &audcp_vbc_24m_eb.common,
1671         &audcp_tmr_26m_eb.common,
1672         &audcp_dvfs_ashb_eb.common,
1673 };
1674
1675 static struct clk_hw_onecell_data ums512_audcpahb_gate_hws = {
1676         .hws    = {
1677                 [CLK_AUDCP_IIS0_EB]             = &audcp_iis0_eb.common.hw,
1678                 [CLK_AUDCP_IIS1_EB]             = &audcp_iis1_eb.common.hw,
1679                 [CLK_AUDCP_IIS2_EB]             = &audcp_iis2_eb.common.hw,
1680                 [CLK_AUDCP_UART_EB]             = &audcp_uart_eb.common.hw,
1681                 [CLK_AUDCP_DMA_CP_EB]           = &audcp_dma_cp_eb.common.hw,
1682                 [CLK_AUDCP_DMA_AP_EB]           = &audcp_dma_ap_eb.common.hw,
1683                 [CLK_AUDCP_SRC48K_EB]           = &audcp_src48k_eb.common.hw,
1684                 [CLK_AUDCP_MCDT_EB]             = &audcp_mcdt_eb.common.hw,
1685                 [CLK_AUDCP_VBCIFD_EB]           = &audcp_vbcifd_eb.common.hw,
1686                 [CLK_AUDCP_VBC_EB]              = &audcp_vbc_eb.common.hw,
1687                 [CLK_AUDCP_SPLK_EB]             = &audcp_splk_eb.common.hw,
1688                 [CLK_AUDCP_ICU_EB]              = &audcp_icu_eb.common.hw,
1689                 [CLK_AUDCP_DMA_AP_ASHB_EB]      = &dma_ap_ashb_eb.common.hw,
1690                 [CLK_AUDCP_DMA_CP_ASHB_EB]      = &dma_cp_ashb_eb.common.hw,
1691                 [CLK_AUDCP_AUD_EB]              = &audcp_aud_eb.common.hw,
1692                 [CLK_AUDCP_VBC_24M_EB]          = &audcp_vbc_24m_eb.common.hw,
1693                 [CLK_AUDCP_TMR_26M_EB]          = &audcp_tmr_26m_eb.common.hw,
1694                 [CLK_AUDCP_DVFS_ASHB_EB]        = &audcp_dvfs_ashb_eb.common.hw,
1695         },
1696         .num    = CLK_AUDCP_AHB_GATE_NUM,
1697 };
1698
1699 static const struct sprd_clk_desc ums512_audcpahb_gate_desc = {
1700         .clk_clks       = ums512_audcpahb_gate,
1701         .num_clk_clks   = ARRAY_SIZE(ums512_audcpahb_gate),
1702         .hw_clks        = &ums512_audcpahb_gate_hws,
1703 };
1704
1705 /* gpu clocks */
1706 static SPRD_GATE_CLK_HW(gpu_core_gate, "gpu-core-gate", &gpu_eb.common.hw,
1707                         0x4, BIT(0), 0, 0);
1708
1709 static const struct clk_parent_data gpu_parents[] = {
1710         { .fw_name = "ext-26m" },
1711         { .hw = &twpll_384m.hw  },
1712         { .hw = &twpll_512m.hw  },
1713         { .hw = &lpll_614m4.hw  },
1714         { .hw = &twpll_768m.hw  },
1715         { .hw = &gpll.common.hw  },
1716 };
1717
1718 static SPRD_COMP_CLK_DATA(gpu_core_clk, "gpu-core-clk", gpu_parents,
1719                           0x4, 4, 3, 8, 3, 0);
1720
1721 static SPRD_GATE_CLK_HW(gpu_mem_gate, "gpu-mem-gate", &gpu_eb.common.hw,
1722                         0x8, BIT(0), 0, 0);
1723
1724 static SPRD_COMP_CLK_DATA(gpu_mem_clk, "gpu-mem-clk", gpu_parents,
1725                           0x8, 4, 3, 8, 3, 0);
1726
1727 static SPRD_GATE_CLK_HW(gpu_sys_gate, "gpu-sys-gate", &gpu_eb.common.hw,
1728                         0xc, BIT(0), 0, 0);
1729
1730 static SPRD_DIV_CLK_HW(gpu_sys_clk, "gpu-sys-clk", &gpu_eb.common.hw,
1731                        0xc, 4, 3, 0);
1732
1733 static struct sprd_clk_common *ums512_gpu_clk[] = {
1734         /* address base is 0x60100000 */
1735         &gpu_core_gate.common,
1736         &gpu_core_clk.common,
1737         &gpu_mem_gate.common,
1738         &gpu_mem_clk.common,
1739         &gpu_sys_gate.common,
1740         &gpu_sys_clk.common,
1741 };
1742
1743 static struct clk_hw_onecell_data ums512_gpu_clk_hws = {
1744         .hws    = {
1745                 [CLK_GPU_CORE_EB]       = &gpu_core_gate.common.hw,
1746                 [CLK_GPU_CORE]          = &gpu_core_clk.common.hw,
1747                 [CLK_GPU_MEM_EB]        = &gpu_mem_gate.common.hw,
1748                 [CLK_GPU_MEM]           = &gpu_mem_clk.common.hw,
1749                 [CLK_GPU_SYS_EB]        = &gpu_sys_gate.common.hw,
1750                 [CLK_GPU_SYS]           = &gpu_sys_clk.common.hw,
1751         },
1752         .num    = CLK_GPU_CLK_NUM,
1753 };
1754
1755 static struct sprd_clk_desc ums512_gpu_clk_desc = {
1756         .clk_clks       = ums512_gpu_clk,
1757         .num_clk_clks   = ARRAY_SIZE(ums512_gpu_clk),
1758         .hw_clks        = &ums512_gpu_clk_hws,
1759 };
1760
1761 /* mm clocks */
1762 static const struct clk_parent_data mm_ahb_parents[] = {
1763         { .fw_name = "ext-26m" },
1764         { .hw = &twpll_96m.hw  },
1765         { .hw = &twpll_128m.hw  },
1766         { .hw = &twpll_153m6.hw  },
1767 };
1768 static SPRD_MUX_CLK_DATA(mm_ahb_clk, "mm-ahb-clk", mm_ahb_parents,
1769                          0x20, 0, 2, UMS512_MUX_FLAG);
1770
1771 static const struct clk_parent_data mm_mtx_parents[] = {
1772         { .hw = &twpll_76m8.hw  },
1773         { .hw = &twpll_128m.hw  },
1774         { .hw = &twpll_256m.hw  },
1775         { .hw = &twpll_307m2.hw  },
1776         { .hw = &twpll_384m.hw  },
1777         { .hw = &isppll_468m.hw  },
1778         { .hw = &twpll_512m.hw  },
1779 };
1780 static SPRD_MUX_CLK_DATA(mm_mtx_clk, "mm-mtx-clk", mm_mtx_parents,
1781                          0x24, 0, 3, UMS512_MUX_FLAG);
1782
1783 static const struct clk_parent_data sensor_parents[] = {
1784         { .fw_name = "ext-26m" },
1785         { .hw = &twpll_48m.hw  },
1786         { .hw = &twpll_76m8.hw  },
1787         { .hw = &twpll_96m.hw  },
1788 };
1789 static SPRD_COMP_CLK_DATA(sensor0_clk, "sensor0-clk", sensor_parents,
1790                           0x28, 0, 2, 8, 3, 0);
1791 static SPRD_COMP_CLK_DATA(sensor1_clk, "sensor1-clk", sensor_parents,
1792                           0x2c, 0, 2, 8, 3, 0);
1793 static SPRD_COMP_CLK_DATA(sensor2_clk, "sensor2-clk", sensor_parents,
1794                           0x30, 0, 2, 8, 3, 0);
1795
1796 static const struct clk_parent_data cpp_parents[] = {
1797         { .hw = &twpll_76m8.hw  },
1798         { .hw = &twpll_128m.hw  },
1799         { .hw = &twpll_256m.hw  },
1800         { .hw = &twpll_384m.hw  },
1801 };
1802 static SPRD_MUX_CLK_DATA(cpp_clk, "cpp-clk", cpp_parents,
1803                          0x34, 0, 2, UMS512_MUX_FLAG);
1804
1805 static const struct clk_parent_data jpg_parents[] = {
1806         { .hw = &twpll_76m8.hw  },
1807         { .hw = &twpll_128m.hw  },
1808         { .hw = &twpll_256m.hw  },
1809         { .hw = &twpll_384m.hw  },
1810 };
1811 static SPRD_MUX_CLK_DATA(jpg_clk, "jpg-clk", jpg_parents,
1812                          0x38, 0, 2, UMS512_MUX_FLAG);
1813
1814 static const struct clk_parent_data fd_parents[] = {
1815         { .hw = &twpll_76m8.hw  },
1816         { .hw = &twpll_192m.hw  },
1817         { .hw = &twpll_307m2.hw  },
1818         { .hw = &twpll_384m.hw  },
1819 };
1820 static SPRD_MUX_CLK_DATA(fd_clk, "fd-clk", fd_parents,
1821                          0x3c, 0, 2, UMS512_MUX_FLAG);
1822
1823 static const struct clk_parent_data dcam_if_parents[] = {
1824         { .hw = &twpll_192m.hw  },
1825         { .hw = &twpll_256m.hw  },
1826         { .hw = &twpll_307m2.hw  },
1827         { .hw = &twpll_384m.hw  },
1828         { .hw = &isppll_468m.hw  },
1829 };
1830 static SPRD_MUX_CLK_DATA(dcam_if_clk, "dcam-if-clk", dcam_if_parents,
1831                          0x40, 0, 3, UMS512_MUX_FLAG);
1832
1833 static const struct clk_parent_data dcam_axi_parents[] = {
1834         { .hw = &twpll_256m.hw  },
1835         { .hw = &twpll_307m2.hw  },
1836         { .hw = &twpll_384m.hw  },
1837         { .hw = &isppll_468m.hw  },
1838 };
1839 static SPRD_MUX_CLK_DATA(dcam_axi_clk, "dcam-axi-clk", dcam_axi_parents,
1840                          0x44, 0, 2, UMS512_MUX_FLAG);
1841
1842 static const struct clk_parent_data isp_parents[] = {
1843         { .hw = &twpll_256m.hw  },
1844         { .hw = &twpll_307m2.hw  },
1845         { .hw = &twpll_384m.hw  },
1846         { .hw = &isppll_468m.hw  },
1847         { .hw = &twpll_512m.hw  },
1848 };
1849 static SPRD_MUX_CLK_DATA(isp_clk, "isp-clk", isp_parents,
1850                          0x48, 0, 3, UMS512_MUX_FLAG);
1851
1852 static SPRD_GATE_CLK_HW(mipi_csi0, "mipi-csi0", &mm_eb.common.hw,
1853                         0x4c, BIT(16), CLK_IGNORE_UNUSED, 0);
1854
1855 static SPRD_GATE_CLK_HW(mipi_csi1, "mipi-csi1", &mm_eb.common.hw,
1856                         0x50, BIT(16), CLK_IGNORE_UNUSED, 0);
1857
1858 static SPRD_GATE_CLK_HW(mipi_csi2, "mipi-csi2", &mm_eb.common.hw,
1859                         0x54, BIT(16), CLK_IGNORE_UNUSED, 0);
1860
1861 static struct sprd_clk_common *ums512_mm_clk[] = {
1862         /* address base is 0x62100000 */
1863         &mm_ahb_clk.common,
1864         &mm_mtx_clk.common,
1865         &sensor0_clk.common,
1866         &sensor1_clk.common,
1867         &sensor2_clk.common,
1868         &cpp_clk.common,
1869         &jpg_clk.common,
1870         &fd_clk.common,
1871         &dcam_if_clk.common,
1872         &dcam_axi_clk.common,
1873         &isp_clk.common,
1874         &mipi_csi0.common,
1875         &mipi_csi1.common,
1876         &mipi_csi2.common,
1877 };
1878
1879 static struct clk_hw_onecell_data ums512_mm_clk_hws = {
1880         .hws    = {
1881                 [CLK_MM_AHB]    = &mm_ahb_clk.common.hw,
1882                 [CLK_MM_MTX]    = &mm_mtx_clk.common.hw,
1883                 [CLK_SENSOR0]   = &sensor0_clk.common.hw,
1884                 [CLK_SENSOR1]   = &sensor1_clk.common.hw,
1885                 [CLK_SENSOR2]   = &sensor2_clk.common.hw,
1886                 [CLK_CPP]       = &cpp_clk.common.hw,
1887                 [CLK_JPG]       = &jpg_clk.common.hw,
1888                 [CLK_FD]        = &fd_clk.common.hw,
1889                 [CLK_DCAM_IF]   = &dcam_if_clk.common.hw,
1890                 [CLK_DCAM_AXI]  = &dcam_axi_clk.common.hw,
1891                 [CLK_ISP]       = &isp_clk.common.hw,
1892                 [CLK_MIPI_CSI0] = &mipi_csi0.common.hw,
1893                 [CLK_MIPI_CSI1] = &mipi_csi1.common.hw,
1894                 [CLK_MIPI_CSI2] = &mipi_csi2.common.hw,
1895         },
1896         .num    = CLK_MM_CLK_NUM,
1897 };
1898
1899 static struct sprd_clk_desc ums512_mm_clk_desc = {
1900         .clk_clks       = ums512_mm_clk,
1901         .num_clk_clks   = ARRAY_SIZE(ums512_mm_clk),
1902         .hw_clks        = &ums512_mm_clk_hws,
1903 };
1904
1905 /* mm gate clocks */
1906 static SPRD_SC_GATE_CLK_HW(mm_cpp_eb, "mm-cpp-eb", &mm_eb.common.hw,
1907                            0x0, 0x1000, BIT(0), 0, 0);
1908 static SPRD_SC_GATE_CLK_HW(mm_jpg_eb, "mm-jpg-eb", &mm_eb.common.hw,
1909                            0x0, 0x1000, BIT(1), 0, 0);
1910 static SPRD_SC_GATE_CLK_HW(mm_dcam_eb, "mm-dcam-eb", &mm_eb.common.hw,
1911                            0x0, 0x1000, BIT(2), 0, 0);
1912 static SPRD_SC_GATE_CLK_HW(mm_isp_eb, "mm-isp-eb", &mm_eb.common.hw,
1913                            0x0, 0x1000, BIT(3), 0, 0);
1914 static SPRD_SC_GATE_CLK_HW(mm_csi2_eb, "mm-csi2-eb", &mm_eb.common.hw,
1915                            0x0, 0x1000, BIT(4), 0, 0);
1916 static SPRD_SC_GATE_CLK_HW(mm_csi1_eb, "mm-csi1-eb", &mm_eb.common.hw,
1917                            0x0, 0x1000, BIT(5), 0, 0);
1918 static SPRD_SC_GATE_CLK_HW(mm_csi0_eb, "mm-csi0-eb", &mm_eb.common.hw,
1919                            0x0, 0x1000, BIT(6), 0, 0);
1920 static SPRD_SC_GATE_CLK_HW(mm_ckg_eb, "mm-ckg-eb", &mm_eb.common.hw,
1921                            0x0, 0x1000, BIT(7), 0, 0);
1922 static SPRD_SC_GATE_CLK_HW(mm_isp_ahb_eb, "mm-isp-ahb-eb", &mm_eb.common.hw,
1923                            0x0, 0x1000, BIT(8), 0, 0);
1924 static SPRD_SC_GATE_CLK_HW(mm_dvfs_eb, "mm-dvfs-eb", &mm_eb.common.hw,
1925                            0x0, 0x1000, BIT(9), 0, 0);
1926 static SPRD_SC_GATE_CLK_HW(mm_fd_eb, "mm-fd-eb", &mm_eb.common.hw,
1927                            0x0, 0x1000, BIT(10), 0, 0);
1928 static SPRD_SC_GATE_CLK_HW(mm_sensor2_en, "mm-sensor2-en", &mm_eb.common.hw,
1929                            0x8, 0x1000, BIT(0), 0, 0);
1930 static SPRD_SC_GATE_CLK_HW(mm_sensor1_en, "mm-sensor1-en", &mm_eb.common.hw,
1931                            0x8, 0x1000, BIT(1), 0, 0);
1932 static SPRD_SC_GATE_CLK_HW(mm_sensor0_en, "mm-sensor0-en", &mm_eb.common.hw,
1933                            0x8, 0x1000, BIT(2), 0, 0);
1934 static SPRD_SC_GATE_CLK_HW(mm_mipi_csi2_en, "mm-mipi-csi2-en", &mm_eb.common.hw,
1935                            0x8, 0x1000, BIT(3), 0, 0);
1936 static SPRD_SC_GATE_CLK_HW(mm_mipi_csi1_en, "mm-mipi-csi1-en", &mm_eb.common.hw,
1937                            0x8, 0x1000, BIT(4), 0, 0);
1938 static SPRD_SC_GATE_CLK_HW(mm_mipi_csi0_en, "mm-mipi-csi0-en", &mm_eb.common.hw,
1939                            0x8, 0x1000, BIT(5), 0, 0);
1940 static SPRD_SC_GATE_CLK_HW(mm_dcam_axi_en, "mm-dcam-axi-en", &mm_eb.common.hw,
1941                            0x8, 0x1000, BIT(6), 0, 0);
1942 static SPRD_SC_GATE_CLK_HW(mm_isp_axi_en, "mm-isp-axi-en", &mm_eb.common.hw,
1943                            0x8, 0x1000, BIT(7), 0, 0);
1944 static SPRD_SC_GATE_CLK_HW(mm_cphy_en, "mm-cphy-en", &mm_eb.common.hw,
1945                            0x8, 0x1000, BIT(8), 0, 0);
1946
1947 static struct sprd_clk_common *ums512_mm_gate_clk[] = {
1948         /* address base is 0x62200000 */
1949         &mm_cpp_eb.common,
1950         &mm_jpg_eb.common,
1951         &mm_dcam_eb.common,
1952         &mm_isp_eb.common,
1953         &mm_csi2_eb.common,
1954         &mm_csi1_eb.common,
1955         &mm_csi0_eb.common,
1956         &mm_ckg_eb.common,
1957         &mm_isp_ahb_eb.common,
1958         &mm_dvfs_eb.common,
1959         &mm_fd_eb.common,
1960         &mm_sensor2_en.common,
1961         &mm_sensor1_en.common,
1962         &mm_sensor0_en.common,
1963         &mm_mipi_csi2_en.common,
1964         &mm_mipi_csi1_en.common,
1965         &mm_mipi_csi0_en.common,
1966         &mm_dcam_axi_en.common,
1967         &mm_isp_axi_en.common,
1968         &mm_cphy_en.common,
1969 };
1970
1971 static struct clk_hw_onecell_data ums512_mm_gate_clk_hws = {
1972         .hws    = {
1973                 [CLK_MM_CPP_EB]         = &mm_cpp_eb.common.hw,
1974                 [CLK_MM_JPG_EB]         = &mm_jpg_eb.common.hw,
1975                 [CLK_MM_DCAM_EB]        = &mm_dcam_eb.common.hw,
1976                 [CLK_MM_ISP_EB]         = &mm_isp_eb.common.hw,
1977                 [CLK_MM_CSI2_EB]        = &mm_csi2_eb.common.hw,
1978                 [CLK_MM_CSI1_EB]        = &mm_csi1_eb.common.hw,
1979                 [CLK_MM_CSI0_EB]        = &mm_csi0_eb.common.hw,
1980                 [CLK_MM_CKG_EB]         = &mm_ckg_eb.common.hw,
1981                 [CLK_ISP_AHB_EB]        = &mm_isp_ahb_eb.common.hw,
1982                 [CLK_MM_DVFS_EB]        = &mm_dvfs_eb.common.hw,
1983                 [CLK_MM_FD_EB]          = &mm_fd_eb.common.hw,
1984                 [CLK_MM_SENSOR2_EB]     = &mm_sensor2_en.common.hw,
1985                 [CLK_MM_SENSOR1_EB]     = &mm_sensor1_en.common.hw,
1986                 [CLK_MM_SENSOR0_EB]     = &mm_sensor0_en.common.hw,
1987                 [CLK_MM_MIPI_CSI2_EB]   = &mm_mipi_csi2_en.common.hw,
1988                 [CLK_MM_MIPI_CSI1_EB]   = &mm_mipi_csi1_en.common.hw,
1989                 [CLK_MM_MIPI_CSI0_EB]   = &mm_mipi_csi0_en.common.hw,
1990                 [CLK_DCAM_AXI_EB]       = &mm_dcam_axi_en.common.hw,
1991                 [CLK_ISP_AXI_EB]        = &mm_isp_axi_en.common.hw,
1992                 [CLK_MM_CPHY_EB]        = &mm_cphy_en.common.hw,
1993         },
1994         .num    = CLK_MM_GATE_CLK_NUM,
1995 };
1996
1997 static struct sprd_clk_desc ums512_mm_gate_clk_desc = {
1998         .clk_clks       = ums512_mm_gate_clk,
1999         .num_clk_clks   = ARRAY_SIZE(ums512_mm_gate_clk),
2000         .hw_clks        = &ums512_mm_gate_clk_hws,
2001 };
2002
2003 /* ap apb gates */
2004 static SPRD_SC_GATE_CLK_FW_NAME(sim0_eb, "sim0-eb", "ext-26m",
2005                                 0x0, 0x1000, BIT(0), 0, 0);
2006 static SPRD_SC_GATE_CLK_FW_NAME(iis0_eb, "iis0-eb", "ext-26m",
2007                                 0x0, 0x1000, BIT(1), 0, 0);
2008 static SPRD_SC_GATE_CLK_FW_NAME(iis1_eb, "iis1-eb", "ext-26m",
2009                                 0x0, 0x1000, BIT(2), 0, 0);
2010 static SPRD_SC_GATE_CLK_FW_NAME(iis2_eb, "iis2-eb", "ext-26m",
2011                                 0x0, 0x1000, BIT(3), 0, 0);
2012 static SPRD_SC_GATE_CLK_FW_NAME(apb_reg_eb, "apb-reg-eb", "ext-26m",
2013                                 0x0, 0x1000, BIT(4), CLK_IGNORE_UNUSED, 0);
2014 static SPRD_SC_GATE_CLK_FW_NAME(spi0_eb, "spi0-eb", "ext-26m",
2015                                 0x0, 0x1000, BIT(5), 0, 0);
2016 static SPRD_SC_GATE_CLK_FW_NAME(spi1_eb, "spi1-eb", "ext-26m",
2017                                 0x0, 0x1000, BIT(6), 0, 0);
2018 static SPRD_SC_GATE_CLK_FW_NAME(spi2_eb, "spi2-eb", "ext-26m",
2019                                 0x0, 0x1000, BIT(7), 0, 0);
2020 static SPRD_SC_GATE_CLK_FW_NAME(spi3_eb, "spi3-eb", "ext-26m",
2021                                 0x0, 0x1000, BIT(8), 0, 0);
2022 static SPRD_SC_GATE_CLK_FW_NAME(i2c0_eb, "i2c0-eb", "ext-26m",
2023                                 0x0, 0x1000, BIT(9), 0, 0);
2024 static SPRD_SC_GATE_CLK_FW_NAME(i2c1_eb, "i2c1-eb", "ext-26m",
2025                                 0x0, 0x1000, BIT(10), 0, 0);
2026 static SPRD_SC_GATE_CLK_FW_NAME(i2c2_eb, "i2c2-eb", "ext-26m",
2027                                 0x0, 0x1000, BIT(11), 0, 0);
2028 static SPRD_SC_GATE_CLK_FW_NAME(i2c3_eb, "i2c3-eb", "ext-26m",
2029                                 0x0, 0x1000, BIT(12), 0, 0);
2030 static SPRD_SC_GATE_CLK_FW_NAME(i2c4_eb, "i2c4-eb", "ext-26m",
2031                                 0x0, 0x1000, BIT(13), 0, 0);
2032 static SPRD_SC_GATE_CLK_FW_NAME(uart0_eb, "uart0-eb", "ext-26m",
2033                                 0x0, 0x1000, BIT(14), CLK_IGNORE_UNUSED, 0);
2034 static SPRD_SC_GATE_CLK_FW_NAME(uart1_eb, "uart1-eb", "ext-26m",
2035                                 0x0, 0x1000, BIT(15), CLK_IGNORE_UNUSED, 0);
2036 static SPRD_SC_GATE_CLK_FW_NAME(uart2_eb, "uart2-eb", "ext-26m",
2037                                 0x0, 0x1000, BIT(16), CLK_IGNORE_UNUSED, 0);
2038 static SPRD_SC_GATE_CLK_FW_NAME(sim0_32k_eb, "sim0-32k-eb", "ext-26m",
2039                                 0x0, 0x1000, BIT(17), CLK_IGNORE_UNUSED, 0);
2040 static SPRD_SC_GATE_CLK_FW_NAME(spi0_lfin_eb, "spi0-lfin-eb", "ext-26m",
2041                                 0x0, 0x1000, BIT(18), CLK_IGNORE_UNUSED, 0);
2042 static SPRD_SC_GATE_CLK_FW_NAME(spi1_lfin_eb, "spi1-lfin-eb", "ext-26m",
2043                                 0x0, 0x1000, BIT(19), CLK_IGNORE_UNUSED, 0);
2044 static SPRD_SC_GATE_CLK_FW_NAME(spi2_lfin_eb, "spi2-lfin-eb", "ext-26m",
2045                                 0x0, 0x1000, BIT(20), CLK_IGNORE_UNUSED, 0);
2046 static SPRD_SC_GATE_CLK_FW_NAME(spi3_lfin_eb, "spi3-lfin-eb", "ext-26m",
2047                                 0x0, 0x1000, BIT(21), CLK_IGNORE_UNUSED, 0);
2048 static SPRD_SC_GATE_CLK_FW_NAME(sdio0_eb, "sdio0-eb", "ext-26m",
2049                                 0x0, 0x1000, BIT(22), 0, 0);
2050 static SPRD_SC_GATE_CLK_FW_NAME(sdio1_eb, "sdio1-eb", "ext-26m",
2051                                 0x0, 0x1000, BIT(23), 0, 0);
2052 static SPRD_SC_GATE_CLK_FW_NAME(sdio2_eb, "sdio2-eb", "ext-26m",
2053                                 0x0, 0x1000, BIT(24), 0, 0);
2054 static SPRD_SC_GATE_CLK_FW_NAME(emmc_eb, "emmc-eb", "ext-26m",
2055                                 0x0, 0x1000, BIT(25), 0, 0);
2056 static SPRD_SC_GATE_CLK_FW_NAME(sdio0_32k_eb, "sdio0-32k-eb", "ext-26m",
2057                                 0x0, 0x1000, BIT(26), 0, 0);
2058 static SPRD_SC_GATE_CLK_FW_NAME(sdio1_32k_eb, "sdio1-32k-eb", "ext-26m",
2059                                 0x0, 0x1000, BIT(27), 0, 0);
2060 static SPRD_SC_GATE_CLK_FW_NAME(sdio2_32k_eb, "sdio2-32k-eb", "ext-26m",
2061                                 0x0, 0x1000, BIT(28), 0, 0);
2062 static SPRD_SC_GATE_CLK_FW_NAME(emmc_32k_eb, "emmc-32k-eb", "ext-26m",
2063                                 0x0, 0x1000, BIT(29), 0, 0);
2064
2065 static struct sprd_clk_common *ums512_apapb_gate[] = {
2066         /* address base is 0x71000000 */
2067         &sim0_eb.common,
2068         &iis0_eb.common,
2069         &iis1_eb.common,
2070         &iis2_eb.common,
2071         &apb_reg_eb.common,
2072         &spi0_eb.common,
2073         &spi1_eb.common,
2074         &spi2_eb.common,
2075         &spi3_eb.common,
2076         &i2c0_eb.common,
2077         &i2c1_eb.common,
2078         &i2c2_eb.common,
2079         &i2c3_eb.common,
2080         &i2c4_eb.common,
2081         &uart0_eb.common,
2082         &uart1_eb.common,
2083         &uart2_eb.common,
2084         &sim0_32k_eb.common,
2085         &spi0_lfin_eb.common,
2086         &spi1_lfin_eb.common,
2087         &spi2_lfin_eb.common,
2088         &spi3_lfin_eb.common,
2089         &sdio0_eb.common,
2090         &sdio1_eb.common,
2091         &sdio2_eb.common,
2092         &emmc_eb.common,
2093         &sdio0_32k_eb.common,
2094         &sdio1_32k_eb.common,
2095         &sdio2_32k_eb.common,
2096         &emmc_32k_eb.common,
2097 };
2098
2099 static struct clk_hw_onecell_data ums512_apapb_gate_hws = {
2100         .hws    = {
2101                 [CLK_SIM0_EB]           = &sim0_eb.common.hw,
2102                 [CLK_IIS0_EB]           = &iis0_eb.common.hw,
2103                 [CLK_IIS1_EB]           = &iis1_eb.common.hw,
2104                 [CLK_IIS2_EB]           = &iis2_eb.common.hw,
2105                 [CLK_APB_REG_EB]        = &apb_reg_eb.common.hw,
2106                 [CLK_SPI0_EB]           = &spi0_eb.common.hw,
2107                 [CLK_SPI1_EB]           = &spi1_eb.common.hw,
2108                 [CLK_SPI2_EB]           = &spi2_eb.common.hw,
2109                 [CLK_SPI3_EB]           = &spi3_eb.common.hw,
2110                 [CLK_I2C0_EB]           = &i2c0_eb.common.hw,
2111                 [CLK_I2C1_EB]           = &i2c1_eb.common.hw,
2112                 [CLK_I2C2_EB]           = &i2c2_eb.common.hw,
2113                 [CLK_I2C3_EB]           = &i2c3_eb.common.hw,
2114                 [CLK_I2C4_EB]           = &i2c4_eb.common.hw,
2115                 [CLK_UART0_EB]          = &uart0_eb.common.hw,
2116                 [CLK_UART1_EB]          = &uart1_eb.common.hw,
2117                 [CLK_UART2_EB]          = &uart2_eb.common.hw,
2118                 [CLK_SIM0_32K_EB]       = &sim0_32k_eb.common.hw,
2119                 [CLK_SPI0_LFIN_EB]      = &spi0_lfin_eb.common.hw,
2120                 [CLK_SPI1_LFIN_EB]      = &spi1_lfin_eb.common.hw,
2121                 [CLK_SPI2_LFIN_EB]      = &spi2_lfin_eb.common.hw,
2122                 [CLK_SPI3_LFIN_EB]      = &spi3_lfin_eb.common.hw,
2123                 [CLK_SDIO0_EB]          = &sdio0_eb.common.hw,
2124                 [CLK_SDIO1_EB]          = &sdio1_eb.common.hw,
2125                 [CLK_SDIO2_EB]          = &sdio2_eb.common.hw,
2126                 [CLK_EMMC_EB]           = &emmc_eb.common.hw,
2127                 [CLK_SDIO0_32K_EB]      = &sdio0_32k_eb.common.hw,
2128                 [CLK_SDIO1_32K_EB]      = &sdio1_32k_eb.common.hw,
2129                 [CLK_SDIO2_32K_EB]      = &sdio2_32k_eb.common.hw,
2130                 [CLK_EMMC_32K_EB]       = &emmc_32k_eb.common.hw,
2131         },
2132         .num    = CLK_AP_APB_GATE_NUM,
2133 };
2134
2135 static struct sprd_clk_desc ums512_apapb_gate_desc = {
2136         .clk_clks       = ums512_apapb_gate,
2137         .num_clk_clks   = ARRAY_SIZE(ums512_apapb_gate),
2138         .hw_clks        = &ums512_apapb_gate_hws,
2139 };
2140
2141 static const struct of_device_id sprd_ums512_clk_ids[] = {
2142         { .compatible = "sprd,ums512-pmu-gate",         /* 0x327e0000 */
2143           .data = &ums512_pmu_gate_desc },
2144         { .compatible = "sprd,ums512-g0-pll",           /* 0x32390000 */
2145           .data = &ums512_g0_pll_desc },
2146         { .compatible = "sprd,ums512-g2-pll",           /* 0x323b0000 */
2147           .data = &ums512_g2_pll_desc },
2148         { .compatible = "sprd,ums512-g3-pll",           /* 0x323c0000 */
2149           .data = &ums512_g3_pll_desc },
2150         { .compatible = "sprd,ums512-gc-pll",           /* 0x323e0000 */
2151           .data = &ums512_gc_pll_desc },
2152         { .compatible = "sprd,ums512-apahb-gate",       /* 0x20100000 */
2153           .data = &ums512_apahb_gate_desc },
2154         { .compatible = "sprd,ums512-ap-clk",           /* 0x20200000 */
2155           .data = &ums512_ap_clk_desc },
2156         { .compatible = "sprd,ums512-aonapb-clk",       /* 0x32080200 */
2157           .data = &ums512_aon_apb_desc },
2158         { .compatible = "sprd,ums512-aon-gate",         /* 0x327d0000 */
2159           .data = &ums512_aon_gate_desc },
2160         { .compatible = "sprd,ums512-audcpapb-gate",    /* 0x3350d000 */
2161           .data = &ums512_audcpapb_gate_desc },
2162         { .compatible = "sprd,ums512-audcpahb-gate",    /* 0x335e0000 */
2163           .data = &ums512_audcpahb_gate_desc },
2164         { .compatible = "sprd,ums512-gpu-clk",          /* 0x60100000 */
2165           .data = &ums512_gpu_clk_desc },
2166         { .compatible = "sprd,ums512-mm-clk",           /* 0x62100000 */
2167           .data = &ums512_mm_clk_desc },
2168         { .compatible = "sprd,ums512-mm-gate-clk",      /* 0x62200000 */
2169           .data = &ums512_mm_gate_clk_desc },
2170         { .compatible = "sprd,ums512-apapb-gate",       /* 0x71000000 */
2171           .data = &ums512_apapb_gate_desc },
2172         { }
2173 };
2174 MODULE_DEVICE_TABLE(of, sprd_ums512_clk_ids);
2175
2176 static int ums512_clk_probe(struct platform_device *pdev)
2177 {
2178         const struct sprd_clk_desc *desc;
2179         int ret;
2180
2181         desc = device_get_match_data(&pdev->dev);
2182         if (!desc)
2183                 return -ENODEV;
2184
2185         ret = sprd_clk_regmap_init(pdev, desc);
2186         if (ret)
2187                 return ret;
2188
2189         return sprd_clk_probe(&pdev->dev, desc->hw_clks);
2190 }
2191
2192 static struct platform_driver ums512_clk_driver = {
2193         .probe  = ums512_clk_probe,
2194         .driver = {
2195                 .name   = "ums512-clk",
2196                 .of_match_table = sprd_ums512_clk_ids,
2197         },
2198 };
2199 module_platform_driver(ums512_clk_driver);
2200
2201 MODULE_DESCRIPTION("Unisoc UMS512 Clock Driver");
2202 MODULE_LICENSE("GPL");