1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2017, Intel Corporation
6 #ifndef __STRATIX10_CLK_H
7 #define __STRATIX10_CLK_H
9 struct stratix10_clock_data {
10 struct clk_onecell_data clk_data;
14 struct stratix10_pll_clock {
17 const char *const *parent_names;
23 struct stratix10_perip_c_clock {
26 const char *parent_name;
27 const char *const *parent_names;
33 struct stratix10_perip_cnt_clock {
36 const char *parent_name;
37 const char *const *parent_names;
42 unsigned long bypass_reg;
43 unsigned long bypass_shift;
46 struct stratix10_gate_clock {
49 const char *parent_name;
50 const char *const *parent_names;
53 unsigned long gate_reg;
55 unsigned long div_reg;
58 unsigned long bypass_reg;
63 struct clk *s10_register_pll(const char *, const char *const *, u8,
64 unsigned long, void __iomem *, unsigned long);
66 struct clk *s10_register_periph(const char *, const char *,
67 const char * const *, u8, unsigned long,
68 void __iomem *, unsigned long);
69 struct clk *s10_register_cnt_periph(const char *, const char *,
70 const char * const *, u8,
71 unsigned long, void __iomem *,
72 unsigned long, u8, unsigned long,
74 struct clk *s10_register_gate(const char *, const char *,
75 const char * const *, u8,
76 unsigned long, void __iomem *,
77 unsigned long, unsigned long,
78 unsigned long, unsigned long, u8,
79 unsigned long, u8, u8);
80 #endif /* __STRATIX10_CLK_H */