1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2017, Intel Corporation
6 #ifndef __STRATIX10_CLK_H
7 #define __STRATIX10_CLK_H
9 struct stratix10_clock_data {
13 struct clk_hw_onecell_data clk_data;
16 struct stratix10_pll_clock {
19 const struct clk_parent_data *parent_data;
25 struct stratix10_perip_c_clock {
28 const char *parent_name;
29 const struct clk_parent_data *parent_data;
35 struct n5x_perip_c_clock {
38 const char *parent_name;
39 const char *const *parent_names;
46 struct stratix10_perip_cnt_clock {
49 const char *parent_name;
50 const struct clk_parent_data *parent_data;
55 unsigned long bypass_reg;
56 unsigned long bypass_shift;
59 struct stratix10_gate_clock {
62 const char *parent_name;
63 const struct clk_parent_data *parent_data;
66 unsigned long gate_reg;
68 unsigned long div_reg;
71 unsigned long bypass_reg;
76 struct clk_hw *s10_register_pll(const struct stratix10_pll_clock *clks,
78 struct clk_hw *agilex_register_pll(const struct stratix10_pll_clock *clks,
80 struct clk_hw *n5x_register_pll(const struct stratix10_pll_clock *clks,
82 struct clk_hw *s10_register_periph(const struct stratix10_perip_c_clock *clks,
84 struct clk_hw *n5x_register_periph(const struct n5x_perip_c_clock *clks,
86 struct clk_hw *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *clks,
88 struct clk_hw *s10_register_gate(const struct stratix10_gate_clock *clks,
90 struct clk_hw *agilex_register_gate(const struct stratix10_gate_clock *clks,
92 #endif /* __STRATIX10_CLK_H */