drivers/clk/socfpga/clk-gate.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *  Copyright 2011-2012 Calxeda, Inc.
   4  *  Copyright (C) 2012-2013 Altera Corporation <www.altera.com>
   5  *
   6  * Based from clk-highbank.c
   7  */
   8 #include <linux/slab.h>
   9 #include <linux/clk-provider.h>
  10 #include <linux/io.h>
  11 #include <linux/mfd/syscon.h>
  12 #include <linux/of.h>
  13 #include <linux/regmap.h>
  14
  15 #include "clk.h"
  16
  17 #define SOCFPGA_L4_MP_CLK               "l4_mp_clk"
  18 #define SOCFPGA_L4_SP_CLK               "l4_sp_clk"
  19 #define SOCFPGA_NAND_CLK                "nand_clk"
  20 #define SOCFPGA_NAND_X_CLK              "nand_x_clk"
  21 #define SOCFPGA_MMC_CLK                 "sdmmc_clk"
  22 #define SOCFPGA_GPIO_DB_CLK_OFFSET      0xA8
  23
  24 #define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)
  25
  26 /* SDMMC Group for System Manager defines */
  27 #define SYSMGR_SDMMCGRP_CTRL_OFFSET    0x108
  28
  29 static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
  30 {
  31         u32 l4_src;
  32         u32 perpll_src;
  33         const char *name = clk_hw_get_name(hwclk);
  34
  35         if (streq(name, SOCFPGA_L4_MP_CLK)) {
  36                 l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
  37                 return l4_src & 0x1;
  38         }
  39         if (streq(name, SOCFPGA_L4_SP_CLK)) {
  40                 l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
  41                 return !!(l4_src & 2);
  42         }
  43
  44         perpll_src = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
  45         if (streq(name, SOCFPGA_MMC_CLK))
  46                 return perpll_src & 0x3;
  47         if (streq(name, SOCFPGA_NAND_CLK) ||
  48             streq(name, SOCFPGA_NAND_X_CLK))
  49                 return (perpll_src >> 2) & 3;
  50
  51         /* QSPI clock */
  52         return (perpll_src >> 4) & 3;
  53
  54 }
  55
  56 static int socfpga_clk_set_parent(struct clk_hw *hwclk, u8 parent)
  57 {
  58         u32 src_reg;
  59         const char *name = clk_hw_get_name(hwclk);
  60
  61         if (streq(name, SOCFPGA_L4_MP_CLK)) {
  62                 src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
  63                 src_reg &= ~0x1;
  64                 src_reg |= parent;
  65                 writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
  66         } else if (streq(name, SOCFPGA_L4_SP_CLK)) {
  67                 src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
  68                 src_reg &= ~0x2;
  69                 src_reg |= (parent << 1);
  70                 writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
  71         } else {
  72                 src_reg = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
  73                 if (streq(name, SOCFPGA_MMC_CLK)) {
  74                         src_reg &= ~0x3;
  75                         src_reg |= parent;
  76                 } else if (streq(name, SOCFPGA_NAND_CLK) ||
  77                         streq(name, SOCFPGA_NAND_X_CLK)) {
  78                         src_reg &= ~0xC;
  79                         src_reg |= (parent << 2);
  80                 } else {/* QSPI clock */
  81                         src_reg &= ~0x30;
  82                         src_reg |= (parent << 4);
  83                 }
  84                 writel(src_reg, clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
  85         }
  86
  87         return 0;
  88 }
  89
  90 static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
  91         unsigned long parent_rate)
  92 {
  93         struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
  94         u32 div = 1, val;
  95
  96         if (socfpgaclk->fixed_div)
  97                 div = socfpgaclk->fixed_div;
  98         else if (socfpgaclk->div_reg) {
  99                 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
 100                 val &= GENMASK(socfpgaclk->width - 1, 0);
 101                 /* Check for GPIO_DB_CLK by its offset */
 102                 if ((uintptr_t) socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET)
 103                         div = val + 1;
 104                 else
 105                         div = (1 << val);
 106         }
 107
 108         return parent_rate / div;
 109 }
 110
 111 static int socfpga_clk_prepare(struct clk_hw *hwclk)
 112 {
 113         struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
 114         struct regmap *sys_mgr_base_addr;
 115         int i;
 116         u32 hs_timing;
 117         u32 clk_phase[2];
 118
 119         if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) {
 120                 sys_mgr_base_addr = syscon_regmap_lookup_by_compatible("altr,sys-mgr");
 121                 if (IS_ERR(sys_mgr_base_addr)) {
 122                         pr_err("%s: failed to find altr,sys-mgr regmap!\n", __func__);
 123                         return -EINVAL;
 124                 }
 125
 126                 for (i = 0; i < 2; i++) {
 127                         switch (socfpgaclk->clk_phase[i]) {
 128                         case 0:
 129                                 clk_phase[i] = 0;
 130                                 break;
 131                         case 45:
 132                                 clk_phase[i] = 1;
 133                                 break;
 134                         case 90:
 135                                 clk_phase[i] = 2;
 136                                 break;
 137                         case 135:
 138                                 clk_phase[i] = 3;
 139                                 break;
 140                         case 180:
 141                                 clk_phase[i] = 4;
 142                                 break;
 143                         case 225:
 144                                 clk_phase[i] = 5;
 145                                 break;
 146                         case 270:
 147                                 clk_phase[i] = 6;
 148                                 break;
 149                         case 315:
 150                                 clk_phase[i] = 7;
 151                                 break;
 152                         default:
 153                                 clk_phase[i] = 0;
 154                                 break;
 155                         }
 156                 }
 157                 hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1]);
 158                 regmap_write(sys_mgr_base_addr, SYSMGR_SDMMCGRP_CTRL_OFFSET,
 159                         hs_timing);
 160         }
 161         return 0;
 162 }
 163
 164 static struct clk_ops gateclk_ops = {
 165         .prepare = socfpga_clk_prepare,
 166         .recalc_rate = socfpga_clk_recalc_rate,
 167         .get_parent = socfpga_clk_get_parent,
 168         .set_parent = socfpga_clk_set_parent,
 169 };
 170
 171 void __init socfpga_gate_init(struct device_node *node)
 172 {
 173         u32 clk_gate[2];
 174         u32 div_reg[3];
 175         u32 clk_phase[2];
 176         u32 fixed_div;
 177         struct clk_hw *hw_clk;
 178         struct socfpga_gate_clk *socfpga_clk;
 179         const char *clk_name = node->name;
 180         const char *parent_name[SOCFPGA_MAX_PARENTS];
 181         struct clk_init_data init;
 182         struct clk_ops *ops;
 183         int rc;
 184         int err;
 185
 186         socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
 187         if (WARN_ON(!socfpga_clk))
 188                 return;
 189
 190         ops = kmemdup(&gateclk_ops, sizeof(gateclk_ops), GFP_KERNEL);
 191         if (WARN_ON(!ops)) {
 192                 kfree(socfpga_clk);
 193                 return;
 194         }
 195
 196         rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2);
 197         if (rc)
 198                 clk_gate[0] = 0;
 199
 200         if (clk_gate[0]) {
 201                 socfpga_clk->hw.reg = clk_mgr_base_addr + clk_gate[0];
 202                 socfpga_clk->hw.bit_idx = clk_gate[1];
 203
 204                 ops->enable = clk_gate_ops.enable;
 205                 ops->disable = clk_gate_ops.disable;
 206         }
 207
 208         rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
 209         if (rc)
 210                 socfpga_clk->fixed_div = 0;
 211         else
 212                 socfpga_clk->fixed_div = fixed_div;
 213
 214         rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);
 215         if (!rc) {
 216                 socfpga_clk->div_reg = clk_mgr_base_addr + div_reg[0];
 217                 socfpga_clk->shift = div_reg[1];
 218                 socfpga_clk->width = div_reg[2];
 219         } else {
 220                 socfpga_clk->div_reg = NULL;
 221         }
 222
 223         rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2);
 224         if (!rc) {
 225                 socfpga_clk->clk_phase[0] = clk_phase[0];
 226                 socfpga_clk->clk_phase[1] = clk_phase[1];
 227         }
 228
 229         of_property_read_string(node, "clock-output-names", &clk_name);
 230
 231         init.name = clk_name;
 232         init.ops = ops;
 233         init.flags = 0;
 234
 235         init.num_parents = of_clk_parent_fill(node, parent_name, SOCFPGA_MAX_PARENTS);
 236         if (init.num_parents < 2) {
 237                 ops->get_parent = NULL;
 238                 ops->set_parent = NULL;
 239         }
 240
 241         init.parent_names = parent_name;
 242         socfpga_clk->hw.hw.init = &init;
 243
 244         hw_clk = &socfpga_clk->hw.hw;
 245
 246         err = clk_hw_register(NULL, hw_clk);
 247         if (err) {
 248                 kfree(ops);
 249                 kfree(socfpga_clk);
 250                 return;
 251         }
 252         rc = of_clk_add_provider(node, of_clk_src_simple_get, hw_clk);
 253         if (WARN_ON(rc))
 254                 return;
 255 }