1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2015 Altera Corporation. All rights reserved
5 #include <linux/slab.h>
6 #include <linux/clk-provider.h>
8 #include <linux/mfd/syscon.h>
10 #include <linux/regmap.h>
14 #define streq(a, b) (strcmp((a), (b)) == 0)
16 #define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)
18 /* SDMMC Group for System Manager defines */
19 #define SYSMGR_SDMMCGRP_CTRL_OFFSET 0x28
21 static unsigned long socfpga_gate_clk_recalc_rate(struct clk_hw *hwclk,
22 unsigned long parent_rate)
24 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
27 if (socfpgaclk->fixed_div)
28 div = socfpgaclk->fixed_div;
29 else if (socfpgaclk->div_reg) {
30 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
31 val &= GENMASK(socfpgaclk->width - 1, 0);
35 return parent_rate / div;
38 static int socfpga_clk_prepare(struct clk_hw *hwclk)
40 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
45 if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) {
46 for (i = 0; i < ARRAY_SIZE(clk_phase); i++) {
47 switch (socfpgaclk->clk_phase[i]) {
78 hs_timing = SYSMGR_SDMMC_CTRL_SET_AS10(clk_phase[0], clk_phase[1]);
79 if (!IS_ERR(socfpgaclk->sys_mgr_base_addr))
80 regmap_write(socfpgaclk->sys_mgr_base_addr,
81 SYSMGR_SDMMCGRP_CTRL_OFFSET, hs_timing);
83 pr_err("%s: cannot set clk_phase because sys_mgr_base_addr is not available!\n",
89 static struct clk_ops gateclk_ops = {
90 .prepare = socfpga_clk_prepare,
91 .recalc_rate = socfpga_gate_clk_recalc_rate,
94 static void __init __socfpga_gate_init(struct device_node *node,
95 const struct clk_ops *ops)
102 struct socfpga_gate_clk *socfpga_clk;
103 const char *clk_name = node->name;
104 const char *parent_name[SOCFPGA_MAX_PARENTS];
105 struct clk_init_data init;
108 socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
109 if (WARN_ON(!socfpga_clk))
112 rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2);
117 socfpga_clk->hw.reg = clk_mgr_a10_base_addr + clk_gate[0];
118 socfpga_clk->hw.bit_idx = clk_gate[1];
120 gateclk_ops.enable = clk_gate_ops.enable;
121 gateclk_ops.disable = clk_gate_ops.disable;
124 rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
126 socfpga_clk->fixed_div = 0;
128 socfpga_clk->fixed_div = fixed_div;
130 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);
132 socfpga_clk->div_reg = clk_mgr_a10_base_addr + div_reg[0];
133 socfpga_clk->shift = div_reg[1];
134 socfpga_clk->width = div_reg[2];
136 socfpga_clk->div_reg = NULL;
139 rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2);
141 socfpga_clk->clk_phase[0] = clk_phase[0];
142 socfpga_clk->clk_phase[1] = clk_phase[1];
144 socfpga_clk->sys_mgr_base_addr =
145 syscon_regmap_lookup_by_compatible("altr,sys-mgr");
146 if (IS_ERR(socfpga_clk->sys_mgr_base_addr)) {
147 pr_err("%s: failed to find altr,sys-mgr regmap!\n",
154 of_property_read_string(node, "clock-output-names", &clk_name);
156 init.name = clk_name;
160 init.num_parents = of_clk_parent_fill(node, parent_name, SOCFPGA_MAX_PARENTS);
161 init.parent_names = parent_name;
162 socfpga_clk->hw.hw.init = &init;
164 clk = clk_register(NULL, &socfpga_clk->hw.hw);
165 if (WARN_ON(IS_ERR(clk))) {
169 rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
174 void __init socfpga_a10_gate_init(struct device_node *node)
176 __socfpga_gate_init(node, &gateclk_ops);