2 * common clks module for all SiRF SoCs
4 * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
7 * Licensed under GPLv2 or later.
10 #include <linux/clk.h>
13 #define MHZ (KHZ * KHZ)
15 static void __iomem *sirfsoc_clk_vbase;
16 static void __iomem *sirfsoc_rsc_vbase;
17 static struct clk_onecell_data clk_data;
20 * SiRFprimaII clock controller
21 * - 2 oscillators: osc-26MHz, rtc-32.768KHz
22 * - 3 standard configurable plls: pll1, pll2 & pll3
23 * - 2 exclusive plls: usb phy pll and sata phy pll
24 * - 8 clock domains: cpu/cpudiv, mem/memdiv, sys/io, dsp, graphic, multimedia,
26 * Each clock domain can select its own clock source from five clock sources,
27 * X_XIN, X_XINW, PLL1, PLL2 and PLL3. The domain clock is used as the source
28 * clock of the group clock.
29 * - dsp domain: gps, mf
30 * - io domain: dmac, nand, audio, uart, i2c, spi, usp, pwm, pulse
31 * - sys domain: security
36 unsigned short regofs; /* register offset */
39 #define to_pllclk(_hw) container_of(_hw, struct clk_pll, hw)
43 signed char enable_bit; /* enable bit: 0 ~ 63 */
44 unsigned short regofs; /* register offset */
47 #define to_dmnclk(_hw) container_of(_hw, struct clk_dmn, hw)
51 signed char enable_bit; /* enable bit: 0 ~ 63 */
54 #define to_stdclk(_hw) container_of(_hw, struct clk_std, hw)
56 static int std_clk_is_enabled(struct clk_hw *hw);
57 static int std_clk_enable(struct clk_hw *hw);
58 static void std_clk_disable(struct clk_hw *hw);
60 static inline unsigned long clkc_readl(unsigned reg)
62 return readl(sirfsoc_clk_vbase + reg);
65 static inline void clkc_writel(u32 val, unsigned reg)
67 writel(val, sirfsoc_clk_vbase + reg);
74 static unsigned long pll_clk_recalc_rate(struct clk_hw *hw,
75 unsigned long parent_rate)
77 unsigned long fin = parent_rate;
78 struct clk_pll *clk = to_pllclk(hw);
79 u32 regcfg2 = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 -
80 SIRFSOC_CLKC_PLL1_CFG0;
82 if (clkc_readl(regcfg2) & BIT(2)) {
86 /* fout = fin * nf / nr / od */
87 u32 cfg0 = clkc_readl(clk->regofs);
88 u32 nf = (cfg0 & (BIT(13) - 1)) + 1;
89 u32 nr = ((cfg0 >> 13) & (BIT(6) - 1)) + 1;
90 u32 od = ((cfg0 >> 19) & (BIT(4) - 1)) + 1;
92 return fin / MHZ * nf / nr / od * MHZ;
96 static long pll_clk_round_rate(struct clk_hw *hw, unsigned long rate,
97 unsigned long *parent_rate)
99 unsigned long fin, nf, nr, od;
103 * fout = fin * nf / (nr * od);
104 * set od = 1, nr = fin/MHz, so fout = nf * MHz
106 rate = rate - rate % MHZ;
121 dividend = (u64)fin * nf;
122 do_div(dividend, nr * od);
124 return (long)dividend;
127 static int pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
128 unsigned long parent_rate)
130 struct clk_pll *clk = to_pllclk(hw);
131 unsigned long fin, nf, nr, od, reg;
134 * fout = fin * nf / (nr * od);
135 * set od = 1, nr = fin/MHz, so fout = nf * MHz
139 if (unlikely((rate % MHZ) || nf > BIT(13) || nf < 1))
146 BUG_ON((fin % MHZ) || nr > BIT(6));
150 reg = (nf - 1) | ((nr - 1) << 13) | ((od - 1) << 19);
151 clkc_writel(reg, clk->regofs);
153 reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG1 - SIRFSOC_CLKC_PLL1_CFG0;
154 clkc_writel((nf >> 1) - 1, reg);
156 reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - SIRFSOC_CLKC_PLL1_CFG0;
157 while (!(clkc_readl(reg) & BIT(6)))
163 static long cpu_clk_round_rate(struct clk_hw *hw, unsigned long rate,
164 unsigned long *parent_rate)
167 * SiRF SoC has not cpu clock control,
168 * So bypass to it's parent pll.
170 struct clk_hw *parent_clk = clk_hw_get_parent(hw);
171 struct clk_hw *pll_parent_clk = clk_hw_get_parent(parent_clk);
172 unsigned long pll_parent_rate = clk_hw_get_rate(pll_parent_clk);
173 return pll_clk_round_rate(parent_clk, rate, &pll_parent_rate);
176 static unsigned long cpu_clk_recalc_rate(struct clk_hw *hw,
177 unsigned long parent_rate)
180 * SiRF SoC has not cpu clock control,
181 * So return the parent pll rate.
183 struct clk_hw *parent_clk = clk_hw_get_parent(hw);
184 return clk_hw_get_rate(parent_clk);
187 static struct clk_ops std_pll_ops = {
188 .recalc_rate = pll_clk_recalc_rate,
189 .round_rate = pll_clk_round_rate,
190 .set_rate = pll_clk_set_rate,
193 static const char * const pll_clk_parents[] = {
197 static struct clk_init_data clk_pll1_init = {
200 .parent_names = pll_clk_parents,
201 .num_parents = ARRAY_SIZE(pll_clk_parents),
204 static struct clk_init_data clk_pll2_init = {
207 .parent_names = pll_clk_parents,
208 .num_parents = ARRAY_SIZE(pll_clk_parents),
211 static struct clk_init_data clk_pll3_init = {
214 .parent_names = pll_clk_parents,
215 .num_parents = ARRAY_SIZE(pll_clk_parents),
218 static struct clk_pll clk_pll1 = {
219 .regofs = SIRFSOC_CLKC_PLL1_CFG0,
221 .init = &clk_pll1_init,
225 static struct clk_pll clk_pll2 = {
226 .regofs = SIRFSOC_CLKC_PLL2_CFG0,
228 .init = &clk_pll2_init,
232 static struct clk_pll clk_pll3 = {
233 .regofs = SIRFSOC_CLKC_PLL3_CFG0,
235 .init = &clk_pll3_init,
240 * usb uses specified pll
243 static int usb_pll_clk_enable(struct clk_hw *hw)
245 u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
246 reg &= ~(SIRFSOC_USBPHY_PLL_POWERDOWN | SIRFSOC_USBPHY_PLL_BYPASS);
247 writel(reg, sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
248 while (!(readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL) &
249 SIRFSOC_USBPHY_PLL_LOCK))
255 static void usb_pll_clk_disable(struct clk_hw *clk)
257 u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
258 reg |= (SIRFSOC_USBPHY_PLL_POWERDOWN | SIRFSOC_USBPHY_PLL_BYPASS);
259 writel(reg, sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
262 static unsigned long usb_pll_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
264 u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
265 return (reg & SIRFSOC_USBPHY_PLL_BYPASS) ? parent_rate : 48*MHZ;
268 static struct clk_ops usb_pll_ops = {
269 .enable = usb_pll_clk_enable,
270 .disable = usb_pll_clk_disable,
271 .recalc_rate = usb_pll_clk_recalc_rate,
274 static struct clk_init_data clk_usb_pll_init = {
277 .parent_names = pll_clk_parents,
278 .num_parents = ARRAY_SIZE(pll_clk_parents),
281 static struct clk_hw usb_pll_clk_hw = {
282 .init = &clk_usb_pll_init,
286 * clock domains - cpu, mem, sys/io, dsp, gfx
289 static const char * const dmn_clk_parents[] = {
297 static u8 dmn_clk_get_parent(struct clk_hw *hw)
299 struct clk_dmn *clk = to_dmnclk(hw);
300 u32 cfg = clkc_readl(clk->regofs);
301 const char *name = clk_hw_get_name(hw);
303 /* parent of io domain can only be pll3 */
304 if (strcmp(name, "io") == 0)
307 WARN_ON((cfg & (BIT(3) - 1)) > 4);
309 return cfg & (BIT(3) - 1);
312 static int dmn_clk_set_parent(struct clk_hw *hw, u8 parent)
314 struct clk_dmn *clk = to_dmnclk(hw);
315 u32 cfg = clkc_readl(clk->regofs);
316 const char *name = clk_hw_get_name(hw);
318 /* parent of io domain can only be pll3 */
319 if (strcmp(name, "io") == 0)
322 cfg &= ~(BIT(3) - 1);
323 clkc_writel(cfg | parent, clk->regofs);
324 /* BIT(3) - switching status: 1 - busy, 0 - done */
325 while (clkc_readl(clk->regofs) & BIT(3))
331 static unsigned long dmn_clk_recalc_rate(struct clk_hw *hw,
332 unsigned long parent_rate)
335 unsigned long fin = parent_rate;
336 struct clk_dmn *clk = to_dmnclk(hw);
338 u32 cfg = clkc_readl(clk->regofs);
341 /* fcd bypass mode */
345 * wait count: bit[19:16], hold count: bit[23:20]
347 u32 wait = (cfg >> 16) & (BIT(4) - 1);
348 u32 hold = (cfg >> 20) & (BIT(4) - 1);
350 return fin / (wait + hold + 2);
354 static long dmn_clk_round_rate(struct clk_hw *hw, unsigned long rate,
355 unsigned long *parent_rate)
358 unsigned ratio, wait, hold;
359 const char *name = clk_hw_get_name(hw);
360 unsigned bits = (strcmp(name, "mem") == 0) ? 3 : 4;
367 if (ratio > BIT(bits + 1))
368 ratio = BIT(bits + 1);
370 wait = (ratio >> 1) - 1;
371 hold = ratio - wait - 2;
373 return fin / (wait + hold + 2);
376 static int dmn_clk_set_rate(struct clk_hw *hw, unsigned long rate,
377 unsigned long parent_rate)
379 struct clk_dmn *clk = to_dmnclk(hw);
381 unsigned ratio, wait, hold, reg;
382 const char *name = clk_hw_get_name(hw);
383 unsigned bits = (strcmp(name, "mem") == 0) ? 3 : 4;
388 if (unlikely(ratio < 2 || ratio > BIT(bits + 1)))
393 wait = (ratio >> 1) - 1;
394 hold = ratio - wait - 2;
396 reg = clkc_readl(clk->regofs);
397 reg &= ~(((BIT(bits) - 1) << 16) | ((BIT(bits) - 1) << 20));
398 reg |= (wait << 16) | (hold << 20) | BIT(25);
399 clkc_writel(reg, clk->regofs);
401 /* waiting FCD been effective */
402 while (clkc_readl(clk->regofs) & BIT(25))
408 static int cpu_clk_set_rate(struct clk_hw *hw, unsigned long rate,
409 unsigned long parent_rate)
412 struct clk *cur_parent;
414 if (rate == clk_get_rate(clk_pll1.hw.clk)) {
415 ret1 = clk_set_parent(hw->clk, clk_pll1.hw.clk);
419 if (rate == clk_get_rate(clk_pll2.hw.clk)) {
420 ret1 = clk_set_parent(hw->clk, clk_pll2.hw.clk);
424 if (rate == clk_get_rate(clk_pll3.hw.clk)) {
425 ret1 = clk_set_parent(hw->clk, clk_pll3.hw.clk);
429 cur_parent = clk_get_parent(hw->clk);
431 /* switch to tmp pll before setting parent clock's rate */
432 if (cur_parent == clk_pll1.hw.clk) {
433 ret1 = clk_set_parent(hw->clk, clk_pll2.hw.clk);
437 ret2 = clk_set_rate(clk_pll1.hw.clk, rate);
439 ret1 = clk_set_parent(hw->clk, clk_pll1.hw.clk);
441 return ret2 ? ret2 : ret1;
444 static struct clk_ops msi_ops = {
445 .set_rate = dmn_clk_set_rate,
446 .round_rate = dmn_clk_round_rate,
447 .recalc_rate = dmn_clk_recalc_rate,
448 .set_parent = dmn_clk_set_parent,
449 .get_parent = dmn_clk_get_parent,
452 static struct clk_init_data clk_mem_init = {
455 .parent_names = dmn_clk_parents,
456 .num_parents = ARRAY_SIZE(dmn_clk_parents),
459 static struct clk_dmn clk_mem = {
460 .regofs = SIRFSOC_CLKC_MEM_CFG,
462 .init = &clk_mem_init,
466 static struct clk_init_data clk_sys_init = {
469 .parent_names = dmn_clk_parents,
470 .num_parents = ARRAY_SIZE(dmn_clk_parents),
471 .flags = CLK_SET_RATE_GATE,
474 static struct clk_dmn clk_sys = {
475 .regofs = SIRFSOC_CLKC_SYS_CFG,
477 .init = &clk_sys_init,
481 static struct clk_init_data clk_io_init = {
484 .parent_names = dmn_clk_parents,
485 .num_parents = ARRAY_SIZE(dmn_clk_parents),
488 static struct clk_dmn clk_io = {
489 .regofs = SIRFSOC_CLKC_IO_CFG,
491 .init = &clk_io_init,
495 static struct clk_ops cpu_ops = {
496 .set_parent = dmn_clk_set_parent,
497 .get_parent = dmn_clk_get_parent,
498 .set_rate = cpu_clk_set_rate,
499 .round_rate = cpu_clk_round_rate,
500 .recalc_rate = cpu_clk_recalc_rate,
503 static struct clk_init_data clk_cpu_init = {
506 .parent_names = dmn_clk_parents,
507 .num_parents = ARRAY_SIZE(dmn_clk_parents),
508 .flags = CLK_SET_RATE_PARENT,
511 static struct clk_dmn clk_cpu = {
512 .regofs = SIRFSOC_CLKC_CPU_CFG,
514 .init = &clk_cpu_init,
518 static struct clk_ops dmn_ops = {
519 .is_enabled = std_clk_is_enabled,
520 .enable = std_clk_enable,
521 .disable = std_clk_disable,
522 .set_rate = dmn_clk_set_rate,
523 .round_rate = dmn_clk_round_rate,
524 .recalc_rate = dmn_clk_recalc_rate,
525 .set_parent = dmn_clk_set_parent,
526 .get_parent = dmn_clk_get_parent,
529 /* dsp, gfx, mm, lcd and vpp domain */
531 static struct clk_init_data clk_dsp_init = {
534 .parent_names = dmn_clk_parents,
535 .num_parents = ARRAY_SIZE(dmn_clk_parents),
538 static struct clk_dmn clk_dsp = {
539 .regofs = SIRFSOC_CLKC_DSP_CFG,
542 .init = &clk_dsp_init,
546 static struct clk_init_data clk_gfx_init = {
549 .parent_names = dmn_clk_parents,
550 .num_parents = ARRAY_SIZE(dmn_clk_parents),
553 static struct clk_dmn clk_gfx = {
554 .regofs = SIRFSOC_CLKC_GFX_CFG,
557 .init = &clk_gfx_init,
561 static struct clk_init_data clk_mm_init = {
564 .parent_names = dmn_clk_parents,
565 .num_parents = ARRAY_SIZE(dmn_clk_parents),
568 static struct clk_dmn clk_mm = {
569 .regofs = SIRFSOC_CLKC_MM_CFG,
572 .init = &clk_mm_init,
577 * for atlas6, gfx2d holds the bit of prima2's clk_mm
579 #define clk_gfx2d clk_mm
581 static struct clk_init_data clk_lcd_init = {
584 .parent_names = dmn_clk_parents,
585 .num_parents = ARRAY_SIZE(dmn_clk_parents),
588 static struct clk_dmn clk_lcd = {
589 .regofs = SIRFSOC_CLKC_LCD_CFG,
592 .init = &clk_lcd_init,
596 static struct clk_init_data clk_vpp_init = {
599 .parent_names = dmn_clk_parents,
600 .num_parents = ARRAY_SIZE(dmn_clk_parents),
603 static struct clk_dmn clk_vpp = {
604 .regofs = SIRFSOC_CLKC_LCD_CFG,
607 .init = &clk_vpp_init,
611 static struct clk_init_data clk_mmc01_init = {
614 .parent_names = dmn_clk_parents,
615 .num_parents = ARRAY_SIZE(dmn_clk_parents),
618 static struct clk_init_data clk_mmc23_init = {
621 .parent_names = dmn_clk_parents,
622 .num_parents = ARRAY_SIZE(dmn_clk_parents),
625 static struct clk_init_data clk_mmc45_init = {
628 .parent_names = dmn_clk_parents,
629 .num_parents = ARRAY_SIZE(dmn_clk_parents),
633 * peripheral controllers in io domain
636 static int std_clk_is_enabled(struct clk_hw *hw)
640 struct clk_std *clk = to_stdclk(hw);
642 bit = clk->enable_bit % 32;
643 reg = clk->enable_bit / 32;
644 reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg);
646 return !!(clkc_readl(reg) & BIT(bit));
649 static int std_clk_enable(struct clk_hw *hw)
653 struct clk_std *clk = to_stdclk(hw);
655 BUG_ON(clk->enable_bit < 0 || clk->enable_bit > 63);
657 bit = clk->enable_bit % 32;
658 reg = clk->enable_bit / 32;
659 reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg);
661 val = clkc_readl(reg) | BIT(bit);
662 clkc_writel(val, reg);
666 static void std_clk_disable(struct clk_hw *hw)
670 struct clk_std *clk = to_stdclk(hw);
672 BUG_ON(clk->enable_bit < 0 || clk->enable_bit > 63);
674 bit = clk->enable_bit % 32;
675 reg = clk->enable_bit / 32;
676 reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg);
678 val = clkc_readl(reg) & ~BIT(bit);
679 clkc_writel(val, reg);
682 static const char * const std_clk_io_parents[] = {
686 static struct clk_ops ios_ops = {
687 .is_enabled = std_clk_is_enabled,
688 .enable = std_clk_enable,
689 .disable = std_clk_disable,
692 static struct clk_init_data clk_cphif_init = {
695 .parent_names = std_clk_io_parents,
696 .num_parents = ARRAY_SIZE(std_clk_io_parents),
699 static struct clk_std clk_cphif = {
702 .init = &clk_cphif_init,
706 static struct clk_init_data clk_dmac0_init = {
709 .parent_names = std_clk_io_parents,
710 .num_parents = ARRAY_SIZE(std_clk_io_parents),
713 static struct clk_std clk_dmac0 = {
716 .init = &clk_dmac0_init,
720 static struct clk_init_data clk_dmac1_init = {
723 .parent_names = std_clk_io_parents,
724 .num_parents = ARRAY_SIZE(std_clk_io_parents),
727 static struct clk_std clk_dmac1 = {
730 .init = &clk_dmac1_init,
734 static struct clk_init_data clk_audio_init = {
737 .parent_names = std_clk_io_parents,
738 .num_parents = ARRAY_SIZE(std_clk_io_parents),
741 static struct clk_std clk_audio = {
744 .init = &clk_audio_init,
748 static struct clk_init_data clk_uart0_init = {
751 .parent_names = std_clk_io_parents,
752 .num_parents = ARRAY_SIZE(std_clk_io_parents),
755 static struct clk_std clk_uart0 = {
758 .init = &clk_uart0_init,
762 static struct clk_init_data clk_uart1_init = {
765 .parent_names = std_clk_io_parents,
766 .num_parents = ARRAY_SIZE(std_clk_io_parents),
769 static struct clk_std clk_uart1 = {
772 .init = &clk_uart1_init,
776 static struct clk_init_data clk_uart2_init = {
779 .parent_names = std_clk_io_parents,
780 .num_parents = ARRAY_SIZE(std_clk_io_parents),
783 static struct clk_std clk_uart2 = {
786 .init = &clk_uart2_init,
790 static struct clk_init_data clk_usp0_init = {
793 .parent_names = std_clk_io_parents,
794 .num_parents = ARRAY_SIZE(std_clk_io_parents),
797 static struct clk_std clk_usp0 = {
800 .init = &clk_usp0_init,
804 static struct clk_init_data clk_usp1_init = {
807 .parent_names = std_clk_io_parents,
808 .num_parents = ARRAY_SIZE(std_clk_io_parents),
811 static struct clk_std clk_usp1 = {
814 .init = &clk_usp1_init,
818 static struct clk_init_data clk_usp2_init = {
821 .parent_names = std_clk_io_parents,
822 .num_parents = ARRAY_SIZE(std_clk_io_parents),
825 static struct clk_std clk_usp2 = {
828 .init = &clk_usp2_init,
832 static struct clk_init_data clk_vip_init = {
835 .parent_names = std_clk_io_parents,
836 .num_parents = ARRAY_SIZE(std_clk_io_parents),
839 static struct clk_std clk_vip = {
842 .init = &clk_vip_init,
846 static struct clk_init_data clk_spi0_init = {
849 .parent_names = std_clk_io_parents,
850 .num_parents = ARRAY_SIZE(std_clk_io_parents),
853 static struct clk_std clk_spi0 = {
856 .init = &clk_spi0_init,
860 static struct clk_init_data clk_spi1_init = {
863 .parent_names = std_clk_io_parents,
864 .num_parents = ARRAY_SIZE(std_clk_io_parents),
867 static struct clk_std clk_spi1 = {
870 .init = &clk_spi1_init,
874 static struct clk_init_data clk_tsc_init = {
877 .parent_names = std_clk_io_parents,
878 .num_parents = ARRAY_SIZE(std_clk_io_parents),
881 static struct clk_std clk_tsc = {
884 .init = &clk_tsc_init,
888 static struct clk_init_data clk_i2c0_init = {
891 .parent_names = std_clk_io_parents,
892 .num_parents = ARRAY_SIZE(std_clk_io_parents),
895 static struct clk_std clk_i2c0 = {
898 .init = &clk_i2c0_init,
902 static struct clk_init_data clk_i2c1_init = {
905 .parent_names = std_clk_io_parents,
906 .num_parents = ARRAY_SIZE(std_clk_io_parents),
909 static struct clk_std clk_i2c1 = {
912 .init = &clk_i2c1_init,
916 static struct clk_init_data clk_pwmc_init = {
919 .parent_names = std_clk_io_parents,
920 .num_parents = ARRAY_SIZE(std_clk_io_parents),
923 static struct clk_std clk_pwmc = {
926 .init = &clk_pwmc_init,
930 static struct clk_init_data clk_efuse_init = {
933 .parent_names = std_clk_io_parents,
934 .num_parents = ARRAY_SIZE(std_clk_io_parents),
937 static struct clk_std clk_efuse = {
940 .init = &clk_efuse_init,
944 static struct clk_init_data clk_pulse_init = {
947 .parent_names = std_clk_io_parents,
948 .num_parents = ARRAY_SIZE(std_clk_io_parents),
951 static struct clk_std clk_pulse = {
954 .init = &clk_pulse_init,
958 static const char * const std_clk_dsp_parents[] = {
962 static struct clk_init_data clk_gps_init = {
965 .parent_names = std_clk_dsp_parents,
966 .num_parents = ARRAY_SIZE(std_clk_dsp_parents),
969 static struct clk_std clk_gps = {
972 .init = &clk_gps_init,
976 static struct clk_init_data clk_mf_init = {
979 .parent_names = std_clk_io_parents,
980 .num_parents = ARRAY_SIZE(std_clk_io_parents),
983 static struct clk_std clk_mf = {
986 .init = &clk_mf_init,
990 static const char * const std_clk_sys_parents[] = {
994 static struct clk_init_data clk_security_init = {
997 .parent_names = std_clk_sys_parents,
998 .num_parents = ARRAY_SIZE(std_clk_sys_parents),
1001 static struct clk_std clk_security = {
1004 .init = &clk_security_init,
1008 static const char * const std_clk_usb_parents[] = {
1012 static struct clk_init_data clk_usb0_init = {
1015 .parent_names = std_clk_usb_parents,
1016 .num_parents = ARRAY_SIZE(std_clk_usb_parents),
1019 static struct clk_std clk_usb0 = {
1022 .init = &clk_usb0_init,
1026 static struct clk_init_data clk_usb1_init = {
1029 .parent_names = std_clk_usb_parents,
1030 .num_parents = ARRAY_SIZE(std_clk_usb_parents),
1033 static struct clk_std clk_usb1 = {
1036 .init = &clk_usb1_init,