1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014 Tomasz Figa <t.figa@samsung.com>
5 * Based on Exynos Audio Subsystem Clock Controller driver:
7 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
8 * Author: Padmavathi Venna <padma.v@samsung.com>
10 * Driver for Audio Subsystem Clock Controller of S5PV210-compatible SoCs.
14 #include <linux/clk.h>
15 #include <linux/clk-provider.h>
16 #include <linux/of_address.h>
17 #include <linux/syscore_ops.h>
18 #include <linux/init.h>
19 #include <linux/platform_device.h>
21 #include <dt-bindings/clock/s5pv210-audss.h>
23 static DEFINE_SPINLOCK(lock);
24 static void __iomem *reg_base;
25 static struct clk_hw_onecell_data *clk_data;
27 #define ASS_CLK_SRC 0x0
28 #define ASS_CLK_DIV 0x4
29 #define ASS_CLK_GATE 0x8
31 #ifdef CONFIG_PM_SLEEP
32 static unsigned long reg_save[][2] = {
38 static int s5pv210_audss_clk_suspend(void)
42 for (i = 0; i < ARRAY_SIZE(reg_save); i++)
43 reg_save[i][1] = readl(reg_base + reg_save[i][0]);
48 static void s5pv210_audss_clk_resume(void)
52 for (i = 0; i < ARRAY_SIZE(reg_save); i++)
53 writel(reg_save[i][1], reg_base + reg_save[i][0]);
56 static struct syscore_ops s5pv210_audss_clk_syscore_ops = {
57 .suspend = s5pv210_audss_clk_suspend,
58 .resume = s5pv210_audss_clk_resume,
60 #endif /* CONFIG_PM_SLEEP */
62 /* register s5pv210_audss clocks */
63 static int s5pv210_audss_clk_probe(struct platform_device *pdev)
67 const char *mout_audss_p[2];
68 const char *mout_i2s_p[3];
70 struct clk_hw **clk_table;
71 struct clk *hclk, *pll_ref, *pll_in, *cdclk, *sclk_audio;
73 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
74 reg_base = devm_ioremap_resource(&pdev->dev, res);
76 return PTR_ERR(reg_base);
78 clk_data = devm_kzalloc(&pdev->dev,
79 struct_size(clk_data, hws, AUDSS_MAX_CLKS),
85 clk_data->num = AUDSS_MAX_CLKS;
86 clk_table = clk_data->hws;
88 hclk = devm_clk_get(&pdev->dev, "hclk");
90 dev_err(&pdev->dev, "failed to get hclk clock\n");
94 pll_in = devm_clk_get(&pdev->dev, "fout_epll");
96 dev_err(&pdev->dev, "failed to get fout_epll clock\n");
97 return PTR_ERR(pll_in);
100 sclk_audio = devm_clk_get(&pdev->dev, "sclk_audio0");
101 if (IS_ERR(sclk_audio)) {
102 dev_err(&pdev->dev, "failed to get sclk_audio0 clock\n");
103 return PTR_ERR(sclk_audio);
106 /* iiscdclk0 is an optional external I2S codec clock */
107 cdclk = devm_clk_get(&pdev->dev, "iiscdclk0");
108 pll_ref = devm_clk_get(&pdev->dev, "xxti");
110 if (!IS_ERR(pll_ref))
111 mout_audss_p[0] = __clk_get_name(pll_ref);
113 mout_audss_p[0] = "xxti";
114 mout_audss_p[1] = __clk_get_name(pll_in);
115 clk_table[CLK_MOUT_AUDSS] = clk_hw_register_mux(NULL, "mout_audss",
116 mout_audss_p, ARRAY_SIZE(mout_audss_p),
117 CLK_SET_RATE_NO_REPARENT,
118 reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
120 mout_i2s_p[0] = "mout_audss";
122 mout_i2s_p[1] = __clk_get_name(cdclk);
124 mout_i2s_p[1] = "iiscdclk0";
125 mout_i2s_p[2] = __clk_get_name(sclk_audio);
126 clk_table[CLK_MOUT_I2S_A] = clk_hw_register_mux(NULL, "mout_i2s_audss",
127 mout_i2s_p, ARRAY_SIZE(mout_i2s_p),
128 CLK_SET_RATE_NO_REPARENT,
129 reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);
131 clk_table[CLK_DOUT_AUD_BUS] = clk_hw_register_divider(NULL,
132 "dout_aud_bus", "mout_audss", 0,
133 reg_base + ASS_CLK_DIV, 0, 4, 0, &lock);
134 clk_table[CLK_DOUT_I2S_A] = clk_hw_register_divider(NULL,
135 "dout_i2s_audss", "mout_i2s_audss", 0,
136 reg_base + ASS_CLK_DIV, 4, 4, 0, &lock);
138 clk_table[CLK_I2S] = clk_hw_register_gate(NULL, "i2s_audss",
139 "dout_i2s_audss", CLK_SET_RATE_PARENT,
140 reg_base + ASS_CLK_GATE, 6, 0, &lock);
142 hclk_p = __clk_get_name(hclk);
144 clk_table[CLK_HCLK_I2S] = clk_hw_register_gate(NULL, "hclk_i2s_audss",
145 hclk_p, CLK_IGNORE_UNUSED,
146 reg_base + ASS_CLK_GATE, 5, 0, &lock);
147 clk_table[CLK_HCLK_UART] = clk_hw_register_gate(NULL, "hclk_uart_audss",
148 hclk_p, CLK_IGNORE_UNUSED,
149 reg_base + ASS_CLK_GATE, 4, 0, &lock);
150 clk_table[CLK_HCLK_HWA] = clk_hw_register_gate(NULL, "hclk_hwa_audss",
151 hclk_p, CLK_IGNORE_UNUSED,
152 reg_base + ASS_CLK_GATE, 3, 0, &lock);
153 clk_table[CLK_HCLK_DMA] = clk_hw_register_gate(NULL, "hclk_dma_audss",
154 hclk_p, CLK_IGNORE_UNUSED,
155 reg_base + ASS_CLK_GATE, 2, 0, &lock);
156 clk_table[CLK_HCLK_BUF] = clk_hw_register_gate(NULL, "hclk_buf_audss",
157 hclk_p, CLK_IGNORE_UNUSED,
158 reg_base + ASS_CLK_GATE, 1, 0, &lock);
159 clk_table[CLK_HCLK_RP] = clk_hw_register_gate(NULL, "hclk_rp_audss",
160 hclk_p, CLK_IGNORE_UNUSED,
161 reg_base + ASS_CLK_GATE, 0, 0, &lock);
163 for (i = 0; i < clk_data->num; i++) {
164 if (IS_ERR(clk_table[i])) {
165 dev_err(&pdev->dev, "failed to register clock %d\n", i);
166 ret = PTR_ERR(clk_table[i]);
171 ret = of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_onecell_get,
174 dev_err(&pdev->dev, "failed to add clock provider\n");
178 #ifdef CONFIG_PM_SLEEP
179 register_syscore_ops(&s5pv210_audss_clk_syscore_ops);
185 for (i = 0; i < clk_data->num; i++) {
186 if (!IS_ERR(clk_table[i]))
187 clk_hw_unregister(clk_table[i]);
193 static const struct of_device_id s5pv210_audss_clk_of_match[] = {
194 { .compatible = "samsung,s5pv210-audss-clock", },
198 static struct platform_driver s5pv210_audss_clk_driver = {
200 .name = "s5pv210-audss-clk",
201 .suppress_bind_attrs = true,
202 .of_match_table = s5pv210_audss_clk_of_match,
204 .probe = s5pv210_audss_clk_probe,
207 static int __init s5pv210_audss_clk_init(void)
209 return platform_driver_register(&s5pv210_audss_clk_driver);
211 core_initcall(s5pv210_audss_clk_init);