2 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
3 * Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
11 #include <linux/clk-provider.h>
15 #include <dt-bindings/clock/exynos7-clk.h>
17 /* Register Offset definitions for CMU_TOPC (0x10570000) */
18 #define CC_PLL_LOCK 0x0000
19 #define BUS0_PLL_LOCK 0x0004
20 #define BUS1_DPLL_LOCK 0x0008
21 #define MFC_PLL_LOCK 0x000C
22 #define AUD_PLL_LOCK 0x0010
23 #define CC_PLL_CON0 0x0100
24 #define BUS0_PLL_CON0 0x0110
25 #define BUS1_DPLL_CON0 0x0120
26 #define MFC_PLL_CON0 0x0130
27 #define AUD_PLL_CON0 0x0140
28 #define MUX_SEL_TOPC0 0x0200
29 #define MUX_SEL_TOPC1 0x0204
30 #define MUX_SEL_TOPC2 0x0208
31 #define MUX_SEL_TOPC3 0x020C
32 #define DIV_TOPC0 0x0600
33 #define DIV_TOPC1 0x0604
34 #define DIV_TOPC3 0x060C
35 #define ENABLE_ACLK_TOPC0 0x0800
36 #define ENABLE_ACLK_TOPC1 0x0804
37 #define ENABLE_SCLK_TOPC1 0x0A04
39 static const struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initconst = {
40 FFACTOR(0, "ffac_topc_bus0_pll_div2", "mout_topc_bus0_pll", 1, 2, 0),
41 FFACTOR(0, "ffac_topc_bus0_pll_div4",
42 "ffac_topc_bus0_pll_div2", 1, 2, 0),
43 FFACTOR(0, "ffac_topc_bus1_pll_div2", "mout_topc_bus1_pll", 1, 2, 0),
44 FFACTOR(0, "ffac_topc_cc_pll_div2", "mout_topc_cc_pll", 1, 2, 0),
45 FFACTOR(0, "ffac_topc_mfc_pll_div2", "mout_topc_mfc_pll", 1, 2, 0),
48 /* List of parent clocks for Muxes in CMU_TOPC */
49 PNAME(mout_topc_aud_pll_ctrl_p) = { "fin_pll", "fout_aud_pll" };
50 PNAME(mout_topc_bus0_pll_ctrl_p) = { "fin_pll", "fout_bus0_pll" };
51 PNAME(mout_topc_bus1_pll_ctrl_p) = { "fin_pll", "fout_bus1_pll" };
52 PNAME(mout_topc_cc_pll_ctrl_p) = { "fin_pll", "fout_cc_pll" };
53 PNAME(mout_topc_mfc_pll_ctrl_p) = { "fin_pll", "fout_mfc_pll" };
55 PNAME(mout_topc_group2) = { "mout_topc_bus0_pll_half",
56 "mout_topc_bus1_pll_half", "mout_topc_cc_pll_half",
57 "mout_topc_mfc_pll_half" };
59 PNAME(mout_topc_bus0_pll_half_p) = { "mout_topc_bus0_pll",
60 "ffac_topc_bus0_pll_div2", "ffac_topc_bus0_pll_div4"};
61 PNAME(mout_topc_bus1_pll_half_p) = { "mout_topc_bus1_pll",
62 "ffac_topc_bus1_pll_div2"};
63 PNAME(mout_topc_cc_pll_half_p) = { "mout_topc_cc_pll",
64 "ffac_topc_cc_pll_div2"};
65 PNAME(mout_topc_mfc_pll_half_p) = { "mout_topc_mfc_pll",
66 "ffac_topc_mfc_pll_div2"};
69 PNAME(mout_topc_bus0_pll_out_p) = {"mout_topc_bus0_pll",
70 "ffac_topc_bus0_pll_div2"};
72 static const unsigned long topc_clk_regs[] __initconst = {
92 static const struct samsung_mux_clock topc_mux_clks[] __initconst = {
93 MUX(0, "mout_topc_bus0_pll", mout_topc_bus0_pll_ctrl_p,
95 MUX(0, "mout_topc_bus1_pll", mout_topc_bus1_pll_ctrl_p,
97 MUX(0, "mout_topc_cc_pll", mout_topc_cc_pll_ctrl_p,
99 MUX(0, "mout_topc_mfc_pll", mout_topc_mfc_pll_ctrl_p,
100 MUX_SEL_TOPC0, 12, 1),
101 MUX(0, "mout_topc_bus0_pll_half", mout_topc_bus0_pll_half_p,
102 MUX_SEL_TOPC0, 16, 2),
103 MUX(0, "mout_topc_bus1_pll_half", mout_topc_bus1_pll_half_p,
104 MUX_SEL_TOPC0, 20, 1),
105 MUX(0, "mout_topc_cc_pll_half", mout_topc_cc_pll_half_p,
106 MUX_SEL_TOPC0, 24, 1),
107 MUX(0, "mout_topc_mfc_pll_half", mout_topc_mfc_pll_half_p,
108 MUX_SEL_TOPC0, 28, 1),
110 MUX(0, "mout_topc_aud_pll", mout_topc_aud_pll_ctrl_p,
111 MUX_SEL_TOPC1, 0, 1),
112 MUX(0, "mout_topc_bus0_pll_out", mout_topc_bus0_pll_out_p,
113 MUX_SEL_TOPC1, 16, 1),
115 MUX(0, "mout_aclk_ccore_133", mout_topc_group2, MUX_SEL_TOPC2, 4, 2),
117 MUX(0, "mout_aclk_mscl_532", mout_topc_group2, MUX_SEL_TOPC3, 20, 2),
118 MUX(0, "mout_aclk_peris_66", mout_topc_group2, MUX_SEL_TOPC3, 24, 2),
121 static const struct samsung_div_clock topc_div_clks[] __initconst = {
122 DIV(DOUT_ACLK_CCORE_133, "dout_aclk_ccore_133", "mout_aclk_ccore_133",
125 DIV(DOUT_ACLK_MSCL_532, "dout_aclk_mscl_532", "mout_aclk_mscl_532",
127 DIV(DOUT_ACLK_PERIS, "dout_aclk_peris_66", "mout_aclk_peris_66",
130 DIV(DOUT_SCLK_BUS0_PLL, "dout_sclk_bus0_pll", "mout_topc_bus0_pll_out",
132 DIV(DOUT_SCLK_BUS1_PLL, "dout_sclk_bus1_pll", "mout_topc_bus1_pll",
134 DIV(DOUT_SCLK_CC_PLL, "dout_sclk_cc_pll", "mout_topc_cc_pll",
136 DIV(DOUT_SCLK_MFC_PLL, "dout_sclk_mfc_pll", "mout_topc_mfc_pll",
138 DIV(DOUT_SCLK_AUD_PLL, "dout_sclk_aud_pll", "mout_topc_aud_pll",
142 static const struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initconst = {
143 PLL_36XX_RATE(491519897, 20, 1, 0, 31457),
147 static const struct samsung_gate_clock topc_gate_clks[] __initconst = {
148 GATE(ACLK_CCORE_133, "aclk_ccore_133", "dout_aclk_ccore_133",
149 ENABLE_ACLK_TOPC0, 4, CLK_IS_CRITICAL, 0),
151 GATE(ACLK_MSCL_532, "aclk_mscl_532", "dout_aclk_mscl_532",
152 ENABLE_ACLK_TOPC1, 20, 0, 0),
154 GATE(ACLK_PERIS_66, "aclk_peris_66", "dout_aclk_peris_66",
155 ENABLE_ACLK_TOPC1, 24, 0, 0),
157 GATE(SCLK_AUD_PLL, "sclk_aud_pll", "dout_sclk_aud_pll",
158 ENABLE_SCLK_TOPC1, 20, 0, 0),
159 GATE(SCLK_MFC_PLL_B, "sclk_mfc_pll_b", "dout_sclk_mfc_pll",
160 ENABLE_SCLK_TOPC1, 17, 0, 0),
161 GATE(SCLK_MFC_PLL_A, "sclk_mfc_pll_a", "dout_sclk_mfc_pll",
162 ENABLE_SCLK_TOPC1, 16, 0, 0),
163 GATE(SCLK_BUS1_PLL_B, "sclk_bus1_pll_b", "dout_sclk_bus1_pll",
164 ENABLE_SCLK_TOPC1, 13, 0, 0),
165 GATE(SCLK_BUS1_PLL_A, "sclk_bus1_pll_a", "dout_sclk_bus1_pll",
166 ENABLE_SCLK_TOPC1, 12, 0, 0),
167 GATE(SCLK_BUS0_PLL_B, "sclk_bus0_pll_b", "dout_sclk_bus0_pll",
168 ENABLE_SCLK_TOPC1, 5, 0, 0),
169 GATE(SCLK_BUS0_PLL_A, "sclk_bus0_pll_a", "dout_sclk_bus0_pll",
170 ENABLE_SCLK_TOPC1, 4, 0, 0),
171 GATE(SCLK_CC_PLL_B, "sclk_cc_pll_b", "dout_sclk_cc_pll",
172 ENABLE_SCLK_TOPC1, 1, 0, 0),
173 GATE(SCLK_CC_PLL_A, "sclk_cc_pll_a", "dout_sclk_cc_pll",
174 ENABLE_SCLK_TOPC1, 0, 0, 0),
177 static const struct samsung_pll_clock topc_pll_clks[] __initconst = {
178 PLL(pll_1451x, 0, "fout_bus0_pll", "fin_pll", BUS0_PLL_LOCK,
179 BUS0_PLL_CON0, NULL),
180 PLL(pll_1452x, 0, "fout_cc_pll", "fin_pll", CC_PLL_LOCK,
182 PLL(pll_1452x, 0, "fout_bus1_pll", "fin_pll", BUS1_DPLL_LOCK,
183 BUS1_DPLL_CON0, NULL),
184 PLL(pll_1452x, 0, "fout_mfc_pll", "fin_pll", MFC_PLL_LOCK,
186 PLL(pll_1460x, FOUT_AUD_PLL, "fout_aud_pll", "fin_pll", AUD_PLL_LOCK,
187 AUD_PLL_CON0, pll1460x_24mhz_tbl),
190 static const struct samsung_cmu_info topc_cmu_info __initconst = {
191 .pll_clks = topc_pll_clks,
192 .nr_pll_clks = ARRAY_SIZE(topc_pll_clks),
193 .mux_clks = topc_mux_clks,
194 .nr_mux_clks = ARRAY_SIZE(topc_mux_clks),
195 .div_clks = topc_div_clks,
196 .nr_div_clks = ARRAY_SIZE(topc_div_clks),
197 .gate_clks = topc_gate_clks,
198 .nr_gate_clks = ARRAY_SIZE(topc_gate_clks),
199 .fixed_factor_clks = topc_fixed_factor_clks,
200 .nr_fixed_factor_clks = ARRAY_SIZE(topc_fixed_factor_clks),
201 .nr_clk_ids = TOPC_NR_CLK,
202 .clk_regs = topc_clk_regs,
203 .nr_clk_regs = ARRAY_SIZE(topc_clk_regs),
206 static void __init exynos7_clk_topc_init(struct device_node *np)
208 samsung_cmu_register_one(np, &topc_cmu_info);
211 CLK_OF_DECLARE(exynos7_clk_topc, "samsung,exynos7-clock-topc",
212 exynos7_clk_topc_init);
214 /* Register Offset definitions for CMU_TOP0 (0x105D0000) */
215 #define MUX_SEL_TOP00 0x0200
216 #define MUX_SEL_TOP01 0x0204
217 #define MUX_SEL_TOP03 0x020C
218 #define MUX_SEL_TOP0_PERIC0 0x0230
219 #define MUX_SEL_TOP0_PERIC1 0x0234
220 #define MUX_SEL_TOP0_PERIC2 0x0238
221 #define MUX_SEL_TOP0_PERIC3 0x023C
222 #define DIV_TOP03 0x060C
223 #define DIV_TOP0_PERIC0 0x0630
224 #define DIV_TOP0_PERIC1 0x0634
225 #define DIV_TOP0_PERIC2 0x0638
226 #define DIV_TOP0_PERIC3 0x063C
227 #define ENABLE_ACLK_TOP03 0x080C
228 #define ENABLE_SCLK_TOP0_PERIC0 0x0A30
229 #define ENABLE_SCLK_TOP0_PERIC1 0x0A34
230 #define ENABLE_SCLK_TOP0_PERIC2 0x0A38
231 #define ENABLE_SCLK_TOP0_PERIC3 0x0A3C
233 /* List of parent clocks for Muxes in CMU_TOP0 */
234 PNAME(mout_top0_bus0_pll_user_p) = { "fin_pll", "sclk_bus0_pll_a" };
235 PNAME(mout_top0_bus1_pll_user_p) = { "fin_pll", "sclk_bus1_pll_a" };
236 PNAME(mout_top0_cc_pll_user_p) = { "fin_pll", "sclk_cc_pll_a" };
237 PNAME(mout_top0_mfc_pll_user_p) = { "fin_pll", "sclk_mfc_pll_a" };
238 PNAME(mout_top0_aud_pll_user_p) = { "fin_pll", "sclk_aud_pll" };
240 PNAME(mout_top0_bus0_pll_half_p) = {"mout_top0_bus0_pll_user",
241 "ffac_top0_bus0_pll_div2"};
242 PNAME(mout_top0_bus1_pll_half_p) = {"mout_top0_bus1_pll_user",
243 "ffac_top0_bus1_pll_div2"};
244 PNAME(mout_top0_cc_pll_half_p) = {"mout_top0_cc_pll_user",
245 "ffac_top0_cc_pll_div2"};
246 PNAME(mout_top0_mfc_pll_half_p) = {"mout_top0_mfc_pll_user",
247 "ffac_top0_mfc_pll_div2"};
249 PNAME(mout_top0_group1) = {"mout_top0_bus0_pll_half",
250 "mout_top0_bus1_pll_half", "mout_top0_cc_pll_half",
251 "mout_top0_mfc_pll_half"};
252 PNAME(mout_top0_group3) = {"ioclk_audiocdclk0",
253 "ioclk_audiocdclk1", "ioclk_spdif_extclk",
254 "mout_top0_aud_pll_user", "mout_top0_bus0_pll_half",
255 "mout_top0_bus1_pll_half"};
256 PNAME(mout_top0_group4) = {"ioclk_audiocdclk1", "mout_top0_aud_pll_user",
257 "mout_top0_bus0_pll_half", "mout_top0_bus1_pll_half"};
259 static const unsigned long top0_clk_regs[] __initconst = {
272 ENABLE_SCLK_TOP0_PERIC0,
273 ENABLE_SCLK_TOP0_PERIC1,
274 ENABLE_SCLK_TOP0_PERIC2,
275 ENABLE_SCLK_TOP0_PERIC3,
278 static const struct samsung_mux_clock top0_mux_clks[] __initconst = {
279 MUX(0, "mout_top0_aud_pll_user", mout_top0_aud_pll_user_p,
280 MUX_SEL_TOP00, 0, 1),
281 MUX(0, "mout_top0_mfc_pll_user", mout_top0_mfc_pll_user_p,
282 MUX_SEL_TOP00, 4, 1),
283 MUX(0, "mout_top0_cc_pll_user", mout_top0_cc_pll_user_p,
284 MUX_SEL_TOP00, 8, 1),
285 MUX(0, "mout_top0_bus1_pll_user", mout_top0_bus1_pll_user_p,
286 MUX_SEL_TOP00, 12, 1),
287 MUX(0, "mout_top0_bus0_pll_user", mout_top0_bus0_pll_user_p,
288 MUX_SEL_TOP00, 16, 1),
290 MUX(0, "mout_top0_mfc_pll_half", mout_top0_mfc_pll_half_p,
291 MUX_SEL_TOP01, 4, 1),
292 MUX(0, "mout_top0_cc_pll_half", mout_top0_cc_pll_half_p,
293 MUX_SEL_TOP01, 8, 1),
294 MUX(0, "mout_top0_bus1_pll_half", mout_top0_bus1_pll_half_p,
295 MUX_SEL_TOP01, 12, 1),
296 MUX(0, "mout_top0_bus0_pll_half", mout_top0_bus0_pll_half_p,
297 MUX_SEL_TOP01, 16, 1),
299 MUX(0, "mout_aclk_peric1_66", mout_top0_group1, MUX_SEL_TOP03, 12, 2),
300 MUX(0, "mout_aclk_peric0_66", mout_top0_group1, MUX_SEL_TOP03, 20, 2),
302 MUX(0, "mout_sclk_spdif", mout_top0_group3, MUX_SEL_TOP0_PERIC0, 4, 3),
303 MUX(0, "mout_sclk_pcm1", mout_top0_group4, MUX_SEL_TOP0_PERIC0, 8, 2),
304 MUX(0, "mout_sclk_i2s1", mout_top0_group4, MUX_SEL_TOP0_PERIC0, 20, 2),
306 MUX(0, "mout_sclk_spi1", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 8, 2),
307 MUX(0, "mout_sclk_spi0", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 20, 2),
309 MUX(0, "mout_sclk_spi3", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 8, 2),
310 MUX(0, "mout_sclk_spi2", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 20, 2),
311 MUX(0, "mout_sclk_uart3", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 4, 2),
312 MUX(0, "mout_sclk_uart2", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 8, 2),
313 MUX(0, "mout_sclk_uart1", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 12, 2),
314 MUX(0, "mout_sclk_uart0", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 16, 2),
315 MUX(0, "mout_sclk_spi4", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 20, 2),
318 static const struct samsung_div_clock top0_div_clks[] __initconst = {
319 DIV(DOUT_ACLK_PERIC1, "dout_aclk_peric1_66", "mout_aclk_peric1_66",
321 DIV(DOUT_ACLK_PERIC0, "dout_aclk_peric0_66", "mout_aclk_peric0_66",
324 DIV(0, "dout_sclk_spdif", "mout_sclk_spdif", DIV_TOP0_PERIC0, 4, 4),
325 DIV(0, "dout_sclk_pcm1", "mout_sclk_pcm1", DIV_TOP0_PERIC0, 8, 12),
326 DIV(0, "dout_sclk_i2s1", "mout_sclk_i2s1", DIV_TOP0_PERIC0, 20, 10),
328 DIV(0, "dout_sclk_spi1", "mout_sclk_spi1", DIV_TOP0_PERIC1, 8, 12),
329 DIV(0, "dout_sclk_spi0", "mout_sclk_spi0", DIV_TOP0_PERIC1, 20, 12),
331 DIV(0, "dout_sclk_spi3", "mout_sclk_spi3", DIV_TOP0_PERIC2, 8, 12),
332 DIV(0, "dout_sclk_spi2", "mout_sclk_spi2", DIV_TOP0_PERIC2, 20, 12),
334 DIV(0, "dout_sclk_uart3", "mout_sclk_uart3", DIV_TOP0_PERIC3, 4, 4),
335 DIV(0, "dout_sclk_uart2", "mout_sclk_uart2", DIV_TOP0_PERIC3, 8, 4),
336 DIV(0, "dout_sclk_uart1", "mout_sclk_uart1", DIV_TOP0_PERIC3, 12, 4),
337 DIV(0, "dout_sclk_uart0", "mout_sclk_uart0", DIV_TOP0_PERIC3, 16, 4),
338 DIV(0, "dout_sclk_spi4", "mout_sclk_spi4", DIV_TOP0_PERIC3, 20, 12),
341 static const struct samsung_gate_clock top0_gate_clks[] __initconst = {
342 GATE(CLK_ACLK_PERIC0_66, "aclk_peric0_66", "dout_aclk_peric0_66",
343 ENABLE_ACLK_TOP03, 20, CLK_SET_RATE_PARENT, 0),
344 GATE(CLK_ACLK_PERIC1_66, "aclk_peric1_66", "dout_aclk_peric1_66",
345 ENABLE_ACLK_TOP03, 12, CLK_SET_RATE_PARENT, 0),
347 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "dout_sclk_spdif",
348 ENABLE_SCLK_TOP0_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
349 GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_sclk_pcm1",
350 ENABLE_SCLK_TOP0_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
351 GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_sclk_i2s1",
352 ENABLE_SCLK_TOP0_PERIC0, 20, CLK_SET_RATE_PARENT, 0),
354 GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_sclk_spi1",
355 ENABLE_SCLK_TOP0_PERIC1, 8, CLK_SET_RATE_PARENT, 0),
356 GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_sclk_spi0",
357 ENABLE_SCLK_TOP0_PERIC1, 20, CLK_SET_RATE_PARENT, 0),
359 GATE(CLK_SCLK_SPI3, "sclk_spi3", "dout_sclk_spi3",
360 ENABLE_SCLK_TOP0_PERIC2, 8, CLK_SET_RATE_PARENT, 0),
361 GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_sclk_spi2",
362 ENABLE_SCLK_TOP0_PERIC2, 20, CLK_SET_RATE_PARENT, 0),
363 GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_sclk_uart3",
364 ENABLE_SCLK_TOP0_PERIC3, 4, 0, 0),
365 GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_sclk_uart2",
366 ENABLE_SCLK_TOP0_PERIC3, 8, 0, 0),
367 GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_sclk_uart1",
368 ENABLE_SCLK_TOP0_PERIC3, 12, 0, 0),
369 GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_sclk_uart0",
370 ENABLE_SCLK_TOP0_PERIC3, 16, 0, 0),
371 GATE(CLK_SCLK_SPI4, "sclk_spi4", "dout_sclk_spi4",
372 ENABLE_SCLK_TOP0_PERIC3, 20, CLK_SET_RATE_PARENT, 0),
375 static const struct samsung_fixed_factor_clock top0_fixed_factor_clks[] __initconst = {
376 FFACTOR(0, "ffac_top0_bus0_pll_div2", "mout_top0_bus0_pll_user",
378 FFACTOR(0, "ffac_top0_bus1_pll_div2", "mout_top0_bus1_pll_user",
380 FFACTOR(0, "ffac_top0_cc_pll_div2", "mout_top0_cc_pll_user", 1, 2, 0),
381 FFACTOR(0, "ffac_top0_mfc_pll_div2", "mout_top0_mfc_pll_user", 1, 2, 0),
384 static const struct samsung_cmu_info top0_cmu_info __initconst = {
385 .mux_clks = top0_mux_clks,
386 .nr_mux_clks = ARRAY_SIZE(top0_mux_clks),
387 .div_clks = top0_div_clks,
388 .nr_div_clks = ARRAY_SIZE(top0_div_clks),
389 .gate_clks = top0_gate_clks,
390 .nr_gate_clks = ARRAY_SIZE(top0_gate_clks),
391 .fixed_factor_clks = top0_fixed_factor_clks,
392 .nr_fixed_factor_clks = ARRAY_SIZE(top0_fixed_factor_clks),
393 .nr_clk_ids = TOP0_NR_CLK,
394 .clk_regs = top0_clk_regs,
395 .nr_clk_regs = ARRAY_SIZE(top0_clk_regs),
398 static void __init exynos7_clk_top0_init(struct device_node *np)
400 samsung_cmu_register_one(np, &top0_cmu_info);
403 CLK_OF_DECLARE(exynos7_clk_top0, "samsung,exynos7-clock-top0",
404 exynos7_clk_top0_init);
406 /* Register Offset definitions for CMU_TOP1 (0x105E0000) */
407 #define MUX_SEL_TOP10 0x0200
408 #define MUX_SEL_TOP11 0x0204
409 #define MUX_SEL_TOP13 0x020C
410 #define MUX_SEL_TOP1_FSYS0 0x0224
411 #define MUX_SEL_TOP1_FSYS1 0x0228
412 #define MUX_SEL_TOP1_FSYS11 0x022C
413 #define DIV_TOP13 0x060C
414 #define DIV_TOP1_FSYS0 0x0624
415 #define DIV_TOP1_FSYS1 0x0628
416 #define DIV_TOP1_FSYS11 0x062C
417 #define ENABLE_ACLK_TOP13 0x080C
418 #define ENABLE_SCLK_TOP1_FSYS0 0x0A24
419 #define ENABLE_SCLK_TOP1_FSYS1 0x0A28
420 #define ENABLE_SCLK_TOP1_FSYS11 0x0A2C
422 /* List of parent clocks for Muxes in CMU_TOP1 */
423 PNAME(mout_top1_bus0_pll_user_p) = { "fin_pll", "sclk_bus0_pll_b" };
424 PNAME(mout_top1_bus1_pll_user_p) = { "fin_pll", "sclk_bus1_pll_b" };
425 PNAME(mout_top1_cc_pll_user_p) = { "fin_pll", "sclk_cc_pll_b" };
426 PNAME(mout_top1_mfc_pll_user_p) = { "fin_pll", "sclk_mfc_pll_b" };
428 PNAME(mout_top1_bus0_pll_half_p) = {"mout_top1_bus0_pll_user",
429 "ffac_top1_bus0_pll_div2"};
430 PNAME(mout_top1_bus1_pll_half_p) = {"mout_top1_bus1_pll_user",
431 "ffac_top1_bus1_pll_div2"};
432 PNAME(mout_top1_cc_pll_half_p) = {"mout_top1_cc_pll_user",
433 "ffac_top1_cc_pll_div2"};
434 PNAME(mout_top1_mfc_pll_half_p) = {"mout_top1_mfc_pll_user",
435 "ffac_top1_mfc_pll_div2"};
437 PNAME(mout_top1_group1) = {"mout_top1_bus0_pll_half",
438 "mout_top1_bus1_pll_half", "mout_top1_cc_pll_half",
439 "mout_top1_mfc_pll_half"};
441 static const unsigned long top1_clk_regs[] __initconst = {
453 ENABLE_SCLK_TOP1_FSYS0,
454 ENABLE_SCLK_TOP1_FSYS1,
455 ENABLE_SCLK_TOP1_FSYS11,
458 static const struct samsung_mux_clock top1_mux_clks[] __initconst = {
459 MUX(0, "mout_top1_mfc_pll_user", mout_top1_mfc_pll_user_p,
460 MUX_SEL_TOP10, 4, 1),
461 MUX(0, "mout_top1_cc_pll_user", mout_top1_cc_pll_user_p,
462 MUX_SEL_TOP10, 8, 1),
463 MUX(0, "mout_top1_bus1_pll_user", mout_top1_bus1_pll_user_p,
464 MUX_SEL_TOP10, 12, 1),
465 MUX(0, "mout_top1_bus0_pll_user", mout_top1_bus0_pll_user_p,
466 MUX_SEL_TOP10, 16, 1),
468 MUX(0, "mout_top1_mfc_pll_half", mout_top1_mfc_pll_half_p,
469 MUX_SEL_TOP11, 4, 1),
470 MUX(0, "mout_top1_cc_pll_half", mout_top1_cc_pll_half_p,
471 MUX_SEL_TOP11, 8, 1),
472 MUX(0, "mout_top1_bus1_pll_half", mout_top1_bus1_pll_half_p,
473 MUX_SEL_TOP11, 12, 1),
474 MUX(0, "mout_top1_bus0_pll_half", mout_top1_bus0_pll_half_p,
475 MUX_SEL_TOP11, 16, 1),
477 MUX(0, "mout_aclk_fsys1_200", mout_top1_group1, MUX_SEL_TOP13, 24, 2),
478 MUX(0, "mout_aclk_fsys0_200", mout_top1_group1, MUX_SEL_TOP13, 28, 2),
480 MUX(0, "mout_sclk_phy_fsys0_26m", mout_top1_group1,
481 MUX_SEL_TOP1_FSYS0, 0, 2),
482 MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 16, 2),
483 MUX(0, "mout_sclk_usbdrd300", mout_top1_group1,
484 MUX_SEL_TOP1_FSYS0, 28, 2),
486 MUX(0, "mout_sclk_phy_fsys1", mout_top1_group1,
487 MUX_SEL_TOP1_FSYS1, 0, 2),
488 MUX(0, "mout_sclk_ufsunipro20", mout_top1_group1,
489 MUX_SEL_TOP1_FSYS1, 16, 2),
491 MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 0, 2),
492 MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 12, 2),
493 MUX(0, "mout_sclk_phy_fsys1_26m", mout_top1_group1,
494 MUX_SEL_TOP1_FSYS11, 24, 2),
497 static const struct samsung_div_clock top1_div_clks[] __initconst = {
498 DIV(DOUT_ACLK_FSYS1_200, "dout_aclk_fsys1_200", "mout_aclk_fsys1_200",
500 DIV(DOUT_ACLK_FSYS0_200, "dout_aclk_fsys0_200", "mout_aclk_fsys0_200",
503 DIV(DOUT_SCLK_PHY_FSYS1, "dout_sclk_phy_fsys1",
504 "mout_sclk_phy_fsys1", DIV_TOP1_FSYS1, 0, 6),
506 DIV(DOUT_SCLK_UFSUNIPRO20, "dout_sclk_ufsunipro20",
507 "mout_sclk_ufsunipro20",
508 DIV_TOP1_FSYS1, 16, 6),
510 DIV(DOUT_SCLK_MMC2, "dout_sclk_mmc2", "mout_sclk_mmc2",
511 DIV_TOP1_FSYS0, 16, 10),
512 DIV(0, "dout_sclk_usbdrd300", "mout_sclk_usbdrd300",
513 DIV_TOP1_FSYS0, 28, 4),
515 DIV(DOUT_SCLK_MMC1, "dout_sclk_mmc1", "mout_sclk_mmc1",
516 DIV_TOP1_FSYS11, 0, 10),
517 DIV(DOUT_SCLK_MMC0, "dout_sclk_mmc0", "mout_sclk_mmc0",
518 DIV_TOP1_FSYS11, 12, 10),
520 DIV(DOUT_SCLK_PHY_FSYS1_26M, "dout_sclk_phy_fsys1_26m",
521 "mout_sclk_phy_fsys1_26m", DIV_TOP1_FSYS11, 24, 6),
524 static const struct samsung_gate_clock top1_gate_clks[] __initconst = {
525 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_sclk_mmc2",
526 ENABLE_SCLK_TOP1_FSYS0, 16, CLK_SET_RATE_PARENT, 0),
527 GATE(0, "sclk_usbdrd300", "dout_sclk_usbdrd300",
528 ENABLE_SCLK_TOP1_FSYS0, 28, 0, 0),
530 GATE(CLK_SCLK_PHY_FSYS1, "sclk_phy_fsys1", "dout_sclk_phy_fsys1",
531 ENABLE_SCLK_TOP1_FSYS1, 0, CLK_SET_RATE_PARENT, 0),
533 GATE(CLK_SCLK_UFSUNIPRO20, "sclk_ufsunipro20", "dout_sclk_ufsunipro20",
534 ENABLE_SCLK_TOP1_FSYS1, 16, CLK_SET_RATE_PARENT, 0),
536 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_sclk_mmc1",
537 ENABLE_SCLK_TOP1_FSYS11, 0, CLK_SET_RATE_PARENT, 0),
538 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_sclk_mmc0",
539 ENABLE_SCLK_TOP1_FSYS11, 12, CLK_SET_RATE_PARENT, 0),
541 GATE(CLK_ACLK_FSYS0_200, "aclk_fsys0_200", "dout_aclk_fsys0_200",
542 ENABLE_ACLK_TOP13, 28, CLK_SET_RATE_PARENT |
545 * This clock is required for the CMU_FSYS1 registers access, keep it
546 * enabled permanently until proper runtime PM support is added.
548 GATE(CLK_ACLK_FSYS1_200, "aclk_fsys1_200", "dout_aclk_fsys1_200",
549 ENABLE_ACLK_TOP13, 24, CLK_SET_RATE_PARENT |
552 GATE(CLK_SCLK_PHY_FSYS1_26M, "sclk_phy_fsys1_26m",
553 "dout_sclk_phy_fsys1_26m", ENABLE_SCLK_TOP1_FSYS11,
554 24, CLK_SET_RATE_PARENT, 0),
557 static const struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initconst = {
558 FFACTOR(0, "ffac_top1_bus0_pll_div2", "mout_top1_bus0_pll_user",
560 FFACTOR(0, "ffac_top1_bus1_pll_div2", "mout_top1_bus1_pll_user",
562 FFACTOR(0, "ffac_top1_cc_pll_div2", "mout_top1_cc_pll_user", 1, 2, 0),
563 FFACTOR(0, "ffac_top1_mfc_pll_div2", "mout_top1_mfc_pll_user", 1, 2, 0),
566 static const struct samsung_cmu_info top1_cmu_info __initconst = {
567 .mux_clks = top1_mux_clks,
568 .nr_mux_clks = ARRAY_SIZE(top1_mux_clks),
569 .div_clks = top1_div_clks,
570 .nr_div_clks = ARRAY_SIZE(top1_div_clks),
571 .gate_clks = top1_gate_clks,
572 .nr_gate_clks = ARRAY_SIZE(top1_gate_clks),
573 .fixed_factor_clks = top1_fixed_factor_clks,
574 .nr_fixed_factor_clks = ARRAY_SIZE(top1_fixed_factor_clks),
575 .nr_clk_ids = TOP1_NR_CLK,
576 .clk_regs = top1_clk_regs,
577 .nr_clk_regs = ARRAY_SIZE(top1_clk_regs),
580 static void __init exynos7_clk_top1_init(struct device_node *np)
582 samsung_cmu_register_one(np, &top1_cmu_info);
585 CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1",
586 exynos7_clk_top1_init);
588 /* Register Offset definitions for CMU_CCORE (0x105B0000) */
589 #define MUX_SEL_CCORE 0x0200
590 #define DIV_CCORE 0x0600
591 #define ENABLE_ACLK_CCORE0 0x0800
592 #define ENABLE_ACLK_CCORE1 0x0804
593 #define ENABLE_PCLK_CCORE 0x0900
596 * List of parent clocks for Muxes in CMU_CCORE
598 PNAME(mout_aclk_ccore_133_user_p) = { "fin_pll", "aclk_ccore_133" };
600 static const unsigned long ccore_clk_regs[] __initconst = {
605 static const struct samsung_mux_clock ccore_mux_clks[] __initconst = {
606 MUX(0, "mout_aclk_ccore_133_user", mout_aclk_ccore_133_user_p,
607 MUX_SEL_CCORE, 1, 1),
610 static const struct samsung_gate_clock ccore_gate_clks[] __initconst = {
611 GATE(PCLK_RTC, "pclk_rtc", "mout_aclk_ccore_133_user",
612 ENABLE_PCLK_CCORE, 8, 0, 0),
615 static const struct samsung_cmu_info ccore_cmu_info __initconst = {
616 .mux_clks = ccore_mux_clks,
617 .nr_mux_clks = ARRAY_SIZE(ccore_mux_clks),
618 .gate_clks = ccore_gate_clks,
619 .nr_gate_clks = ARRAY_SIZE(ccore_gate_clks),
620 .nr_clk_ids = CCORE_NR_CLK,
621 .clk_regs = ccore_clk_regs,
622 .nr_clk_regs = ARRAY_SIZE(ccore_clk_regs),
625 static void __init exynos7_clk_ccore_init(struct device_node *np)
627 samsung_cmu_register_one(np, &ccore_cmu_info);
630 CLK_OF_DECLARE(exynos7_clk_ccore, "samsung,exynos7-clock-ccore",
631 exynos7_clk_ccore_init);
633 /* Register Offset definitions for CMU_PERIC0 (0x13610000) */
634 #define MUX_SEL_PERIC0 0x0200
635 #define ENABLE_PCLK_PERIC0 0x0900
636 #define ENABLE_SCLK_PERIC0 0x0A00
638 /* List of parent clocks for Muxes in CMU_PERIC0 */
639 PNAME(mout_aclk_peric0_66_user_p) = { "fin_pll", "aclk_peric0_66" };
640 PNAME(mout_sclk_uart0_user_p) = { "fin_pll", "sclk_uart0" };
642 static const unsigned long peric0_clk_regs[] __initconst = {
648 static const struct samsung_mux_clock peric0_mux_clks[] __initconst = {
649 MUX(0, "mout_aclk_peric0_66_user", mout_aclk_peric0_66_user_p,
650 MUX_SEL_PERIC0, 0, 1),
651 MUX(0, "mout_sclk_uart0_user", mout_sclk_uart0_user_p,
652 MUX_SEL_PERIC0, 16, 1),
655 static const struct samsung_gate_clock peric0_gate_clks[] __initconst = {
656 GATE(PCLK_HSI2C0, "pclk_hsi2c0", "mout_aclk_peric0_66_user",
657 ENABLE_PCLK_PERIC0, 8, 0, 0),
658 GATE(PCLK_HSI2C1, "pclk_hsi2c1", "mout_aclk_peric0_66_user",
659 ENABLE_PCLK_PERIC0, 9, 0, 0),
660 GATE(PCLK_HSI2C4, "pclk_hsi2c4", "mout_aclk_peric0_66_user",
661 ENABLE_PCLK_PERIC0, 10, 0, 0),
662 GATE(PCLK_HSI2C5, "pclk_hsi2c5", "mout_aclk_peric0_66_user",
663 ENABLE_PCLK_PERIC0, 11, 0, 0),
664 GATE(PCLK_HSI2C9, "pclk_hsi2c9", "mout_aclk_peric0_66_user",
665 ENABLE_PCLK_PERIC0, 12, 0, 0),
666 GATE(PCLK_HSI2C10, "pclk_hsi2c10", "mout_aclk_peric0_66_user",
667 ENABLE_PCLK_PERIC0, 13, 0, 0),
668 GATE(PCLK_HSI2C11, "pclk_hsi2c11", "mout_aclk_peric0_66_user",
669 ENABLE_PCLK_PERIC0, 14, 0, 0),
670 GATE(PCLK_UART0, "pclk_uart0", "mout_aclk_peric0_66_user",
671 ENABLE_PCLK_PERIC0, 16, 0, 0),
672 GATE(PCLK_ADCIF, "pclk_adcif", "mout_aclk_peric0_66_user",
673 ENABLE_PCLK_PERIC0, 20, 0, 0),
674 GATE(PCLK_PWM, "pclk_pwm", "mout_aclk_peric0_66_user",
675 ENABLE_PCLK_PERIC0, 21, 0, 0),
677 GATE(SCLK_UART0, "sclk_uart0_user", "mout_sclk_uart0_user",
678 ENABLE_SCLK_PERIC0, 16, 0, 0),
679 GATE(SCLK_PWM, "sclk_pwm", "fin_pll", ENABLE_SCLK_PERIC0, 21, 0, 0),
682 static const struct samsung_cmu_info peric0_cmu_info __initconst = {
683 .mux_clks = peric0_mux_clks,
684 .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks),
685 .gate_clks = peric0_gate_clks,
686 .nr_gate_clks = ARRAY_SIZE(peric0_gate_clks),
687 .nr_clk_ids = PERIC0_NR_CLK,
688 .clk_regs = peric0_clk_regs,
689 .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs),
692 static void __init exynos7_clk_peric0_init(struct device_node *np)
694 samsung_cmu_register_one(np, &peric0_cmu_info);
697 /* Register Offset definitions for CMU_PERIC1 (0x14C80000) */
698 #define MUX_SEL_PERIC10 0x0200
699 #define MUX_SEL_PERIC11 0x0204
700 #define MUX_SEL_PERIC12 0x0208
701 #define ENABLE_PCLK_PERIC1 0x0900
702 #define ENABLE_SCLK_PERIC10 0x0A00
704 CLK_OF_DECLARE(exynos7_clk_peric0, "samsung,exynos7-clock-peric0",
705 exynos7_clk_peric0_init);
707 /* List of parent clocks for Muxes in CMU_PERIC1 */
708 PNAME(mout_aclk_peric1_66_user_p) = { "fin_pll", "aclk_peric1_66" };
709 PNAME(mout_sclk_uart1_user_p) = { "fin_pll", "sclk_uart1" };
710 PNAME(mout_sclk_uart2_user_p) = { "fin_pll", "sclk_uart2" };
711 PNAME(mout_sclk_uart3_user_p) = { "fin_pll", "sclk_uart3" };
712 PNAME(mout_sclk_spi0_user_p) = { "fin_pll", "sclk_spi0" };
713 PNAME(mout_sclk_spi1_user_p) = { "fin_pll", "sclk_spi1" };
714 PNAME(mout_sclk_spi2_user_p) = { "fin_pll", "sclk_spi2" };
715 PNAME(mout_sclk_spi3_user_p) = { "fin_pll", "sclk_spi3" };
716 PNAME(mout_sclk_spi4_user_p) = { "fin_pll", "sclk_spi4" };
718 static const unsigned long peric1_clk_regs[] __initconst = {
726 static const struct samsung_mux_clock peric1_mux_clks[] __initconst = {
727 MUX(0, "mout_aclk_peric1_66_user", mout_aclk_peric1_66_user_p,
728 MUX_SEL_PERIC10, 0, 1),
730 MUX_F(0, "mout_sclk_spi0_user", mout_sclk_spi0_user_p,
731 MUX_SEL_PERIC11, 0, 1, CLK_SET_RATE_PARENT, 0),
732 MUX_F(0, "mout_sclk_spi1_user", mout_sclk_spi1_user_p,
733 MUX_SEL_PERIC11, 4, 1, CLK_SET_RATE_PARENT, 0),
734 MUX_F(0, "mout_sclk_spi2_user", mout_sclk_spi2_user_p,
735 MUX_SEL_PERIC11, 8, 1, CLK_SET_RATE_PARENT, 0),
736 MUX_F(0, "mout_sclk_spi3_user", mout_sclk_spi3_user_p,
737 MUX_SEL_PERIC11, 12, 1, CLK_SET_RATE_PARENT, 0),
738 MUX_F(0, "mout_sclk_spi4_user", mout_sclk_spi4_user_p,
739 MUX_SEL_PERIC11, 16, 1, CLK_SET_RATE_PARENT, 0),
740 MUX(0, "mout_sclk_uart1_user", mout_sclk_uart1_user_p,
741 MUX_SEL_PERIC11, 20, 1),
742 MUX(0, "mout_sclk_uart2_user", mout_sclk_uart2_user_p,
743 MUX_SEL_PERIC11, 24, 1),
744 MUX(0, "mout_sclk_uart3_user", mout_sclk_uart3_user_p,
745 MUX_SEL_PERIC11, 28, 1),
748 static const struct samsung_gate_clock peric1_gate_clks[] __initconst = {
749 GATE(PCLK_HSI2C2, "pclk_hsi2c2", "mout_aclk_peric1_66_user",
750 ENABLE_PCLK_PERIC1, 4, 0, 0),
751 GATE(PCLK_HSI2C3, "pclk_hsi2c3", "mout_aclk_peric1_66_user",
752 ENABLE_PCLK_PERIC1, 5, 0, 0),
753 GATE(PCLK_HSI2C6, "pclk_hsi2c6", "mout_aclk_peric1_66_user",
754 ENABLE_PCLK_PERIC1, 6, 0, 0),
755 GATE(PCLK_HSI2C7, "pclk_hsi2c7", "mout_aclk_peric1_66_user",
756 ENABLE_PCLK_PERIC1, 7, 0, 0),
757 GATE(PCLK_HSI2C8, "pclk_hsi2c8", "mout_aclk_peric1_66_user",
758 ENABLE_PCLK_PERIC1, 8, 0, 0),
759 GATE(PCLK_UART1, "pclk_uart1", "mout_aclk_peric1_66_user",
760 ENABLE_PCLK_PERIC1, 9, 0, 0),
761 GATE(PCLK_UART2, "pclk_uart2", "mout_aclk_peric1_66_user",
762 ENABLE_PCLK_PERIC1, 10, 0, 0),
763 GATE(PCLK_UART3, "pclk_uart3", "mout_aclk_peric1_66_user",
764 ENABLE_PCLK_PERIC1, 11, 0, 0),
765 GATE(PCLK_SPI0, "pclk_spi0", "mout_aclk_peric1_66_user",
766 ENABLE_PCLK_PERIC1, 12, 0, 0),
767 GATE(PCLK_SPI1, "pclk_spi1", "mout_aclk_peric1_66_user",
768 ENABLE_PCLK_PERIC1, 13, 0, 0),
769 GATE(PCLK_SPI2, "pclk_spi2", "mout_aclk_peric1_66_user",
770 ENABLE_PCLK_PERIC1, 14, 0, 0),
771 GATE(PCLK_SPI3, "pclk_spi3", "mout_aclk_peric1_66_user",
772 ENABLE_PCLK_PERIC1, 15, 0, 0),
773 GATE(PCLK_SPI4, "pclk_spi4", "mout_aclk_peric1_66_user",
774 ENABLE_PCLK_PERIC1, 16, 0, 0),
775 GATE(PCLK_I2S1, "pclk_i2s1", "mout_aclk_peric1_66_user",
776 ENABLE_PCLK_PERIC1, 17, CLK_SET_RATE_PARENT, 0),
777 GATE(PCLK_PCM1, "pclk_pcm1", "mout_aclk_peric1_66_user",
778 ENABLE_PCLK_PERIC1, 18, 0, 0),
779 GATE(PCLK_SPDIF, "pclk_spdif", "mout_aclk_peric1_66_user",
780 ENABLE_PCLK_PERIC1, 19, 0, 0),
782 GATE(SCLK_UART1, "sclk_uart1_user", "mout_sclk_uart1_user",
783 ENABLE_SCLK_PERIC10, 9, 0, 0),
784 GATE(SCLK_UART2, "sclk_uart2_user", "mout_sclk_uart2_user",
785 ENABLE_SCLK_PERIC10, 10, 0, 0),
786 GATE(SCLK_UART3, "sclk_uart3_user", "mout_sclk_uart3_user",
787 ENABLE_SCLK_PERIC10, 11, 0, 0),
788 GATE(SCLK_SPI0, "sclk_spi0_user", "mout_sclk_spi0_user",
789 ENABLE_SCLK_PERIC10, 12, CLK_SET_RATE_PARENT, 0),
790 GATE(SCLK_SPI1, "sclk_spi1_user", "mout_sclk_spi1_user",
791 ENABLE_SCLK_PERIC10, 13, CLK_SET_RATE_PARENT, 0),
792 GATE(SCLK_SPI2, "sclk_spi2_user", "mout_sclk_spi2_user",
793 ENABLE_SCLK_PERIC10, 14, CLK_SET_RATE_PARENT, 0),
794 GATE(SCLK_SPI3, "sclk_spi3_user", "mout_sclk_spi3_user",
795 ENABLE_SCLK_PERIC10, 15, CLK_SET_RATE_PARENT, 0),
796 GATE(SCLK_SPI4, "sclk_spi4_user", "mout_sclk_spi4_user",
797 ENABLE_SCLK_PERIC10, 16, CLK_SET_RATE_PARENT, 0),
798 GATE(SCLK_I2S1, "sclk_i2s1_user", "sclk_i2s1",
799 ENABLE_SCLK_PERIC10, 17, CLK_SET_RATE_PARENT, 0),
800 GATE(SCLK_PCM1, "sclk_pcm1_user", "sclk_pcm1",
801 ENABLE_SCLK_PERIC10, 18, CLK_SET_RATE_PARENT, 0),
802 GATE(SCLK_SPDIF, "sclk_spdif_user", "sclk_spdif",
803 ENABLE_SCLK_PERIC10, 19, CLK_SET_RATE_PARENT, 0),
806 static const struct samsung_cmu_info peric1_cmu_info __initconst = {
807 .mux_clks = peric1_mux_clks,
808 .nr_mux_clks = ARRAY_SIZE(peric1_mux_clks),
809 .gate_clks = peric1_gate_clks,
810 .nr_gate_clks = ARRAY_SIZE(peric1_gate_clks),
811 .nr_clk_ids = PERIC1_NR_CLK,
812 .clk_regs = peric1_clk_regs,
813 .nr_clk_regs = ARRAY_SIZE(peric1_clk_regs),
816 static void __init exynos7_clk_peric1_init(struct device_node *np)
818 samsung_cmu_register_one(np, &peric1_cmu_info);
821 CLK_OF_DECLARE(exynos7_clk_peric1, "samsung,exynos7-clock-peric1",
822 exynos7_clk_peric1_init);
824 /* Register Offset definitions for CMU_PERIS (0x10040000) */
825 #define MUX_SEL_PERIS 0x0200
826 #define ENABLE_PCLK_PERIS 0x0900
827 #define ENABLE_PCLK_PERIS_SECURE_CHIPID 0x0910
828 #define ENABLE_SCLK_PERIS 0x0A00
829 #define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0A10
831 /* List of parent clocks for Muxes in CMU_PERIS */
832 PNAME(mout_aclk_peris_66_user_p) = { "fin_pll", "aclk_peris_66" };
834 static const unsigned long peris_clk_regs[] __initconst = {
837 ENABLE_PCLK_PERIS_SECURE_CHIPID,
839 ENABLE_SCLK_PERIS_SECURE_CHIPID,
842 static const struct samsung_mux_clock peris_mux_clks[] __initconst = {
843 MUX(0, "mout_aclk_peris_66_user",
844 mout_aclk_peris_66_user_p, MUX_SEL_PERIS, 0, 1),
847 static const struct samsung_gate_clock peris_gate_clks[] __initconst = {
848 GATE(PCLK_WDT, "pclk_wdt", "mout_aclk_peris_66_user",
849 ENABLE_PCLK_PERIS, 6, 0, 0),
850 GATE(PCLK_TMU, "pclk_tmu_apbif", "mout_aclk_peris_66_user",
851 ENABLE_PCLK_PERIS, 10, 0, 0),
853 GATE(PCLK_CHIPID, "pclk_chipid", "mout_aclk_peris_66_user",
854 ENABLE_PCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
855 GATE(SCLK_CHIPID, "sclk_chipid", "fin_pll",
856 ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
858 GATE(SCLK_TMU, "sclk_tmu", "fin_pll", ENABLE_SCLK_PERIS, 10, 0, 0),
861 static const struct samsung_cmu_info peris_cmu_info __initconst = {
862 .mux_clks = peris_mux_clks,
863 .nr_mux_clks = ARRAY_SIZE(peris_mux_clks),
864 .gate_clks = peris_gate_clks,
865 .nr_gate_clks = ARRAY_SIZE(peris_gate_clks),
866 .nr_clk_ids = PERIS_NR_CLK,
867 .clk_regs = peris_clk_regs,
868 .nr_clk_regs = ARRAY_SIZE(peris_clk_regs),
871 static void __init exynos7_clk_peris_init(struct device_node *np)
873 samsung_cmu_register_one(np, &peris_cmu_info);
876 CLK_OF_DECLARE(exynos7_clk_peris, "samsung,exynos7-clock-peris",
877 exynos7_clk_peris_init);
879 /* Register Offset definitions for CMU_FSYS0 (0x10E90000) */
880 #define MUX_SEL_FSYS00 0x0200
881 #define MUX_SEL_FSYS01 0x0204
882 #define MUX_SEL_FSYS02 0x0208
883 #define ENABLE_ACLK_FSYS00 0x0800
884 #define ENABLE_ACLK_FSYS01 0x0804
885 #define ENABLE_SCLK_FSYS01 0x0A04
886 #define ENABLE_SCLK_FSYS02 0x0A08
887 #define ENABLE_SCLK_FSYS04 0x0A10
890 * List of parent clocks for Muxes in CMU_FSYS0
892 PNAME(mout_aclk_fsys0_200_user_p) = { "fin_pll", "aclk_fsys0_200" };
893 PNAME(mout_sclk_mmc2_user_p) = { "fin_pll", "sclk_mmc2" };
895 PNAME(mout_sclk_usbdrd300_user_p) = { "fin_pll", "sclk_usbdrd300" };
896 PNAME(mout_phyclk_usbdrd300_udrd30_phyclk_user_p) = { "fin_pll",
897 "phyclk_usbdrd300_udrd30_phyclock" };
898 PNAME(mout_phyclk_usbdrd300_udrd30_pipe_pclk_user_p) = { "fin_pll",
899 "phyclk_usbdrd300_udrd30_pipe_pclk" };
901 /* fixed rate clocks used in the FSYS0 block */
902 static const struct samsung_fixed_rate_clock fixed_rate_clks_fsys0[] __initconst = {
903 FRATE(0, "phyclk_usbdrd300_udrd30_phyclock", NULL, 0, 60000000),
904 FRATE(0, "phyclk_usbdrd300_udrd30_pipe_pclk", NULL, 0, 125000000),
907 static const unsigned long fsys0_clk_regs[] __initconst = {
918 static const struct samsung_mux_clock fsys0_mux_clks[] __initconst = {
919 MUX(0, "mout_aclk_fsys0_200_user", mout_aclk_fsys0_200_user_p,
920 MUX_SEL_FSYS00, 24, 1),
922 MUX(0, "mout_sclk_mmc2_user", mout_sclk_mmc2_user_p,
923 MUX_SEL_FSYS01, 24, 1),
924 MUX(0, "mout_sclk_usbdrd300_user", mout_sclk_usbdrd300_user_p,
925 MUX_SEL_FSYS01, 28, 1),
927 MUX(0, "mout_phyclk_usbdrd300_udrd30_pipe_pclk_user",
928 mout_phyclk_usbdrd300_udrd30_pipe_pclk_user_p,
929 MUX_SEL_FSYS02, 24, 1),
930 MUX(0, "mout_phyclk_usbdrd300_udrd30_phyclk_user",
931 mout_phyclk_usbdrd300_udrd30_phyclk_user_p,
932 MUX_SEL_FSYS02, 28, 1),
935 static const struct samsung_gate_clock fsys0_gate_clks[] __initconst = {
936 GATE(ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys0_200_user",
937 ENABLE_ACLK_FSYS00, 3, 0, 0),
938 GATE(ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys0_200_user",
939 ENABLE_ACLK_FSYS00, 4, 0, 0),
940 GATE(ACLK_AXIUS_USBDRD30X_FSYS0X, "aclk_axius_usbdrd30x_fsys0x",
941 "mout_aclk_fsys0_200_user",
942 ENABLE_ACLK_FSYS00, 19, 0, 0),
944 GATE(ACLK_USBDRD300, "aclk_usbdrd300", "mout_aclk_fsys0_200_user",
945 ENABLE_ACLK_FSYS01, 29, 0, 0),
946 GATE(ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys0_200_user",
947 ENABLE_ACLK_FSYS01, 31, 0, 0),
949 GATE(SCLK_USBDRD300_SUSPENDCLK, "sclk_usbdrd300_suspendclk",
950 "mout_sclk_usbdrd300_user",
951 ENABLE_SCLK_FSYS01, 4, 0, 0),
952 GATE(SCLK_USBDRD300_REFCLK, "sclk_usbdrd300_refclk", "fin_pll",
953 ENABLE_SCLK_FSYS01, 8, 0, 0),
955 GATE(PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER,
956 "phyclk_usbdrd300_udrd30_pipe_pclk_user",
957 "mout_phyclk_usbdrd300_udrd30_pipe_pclk_user",
958 ENABLE_SCLK_FSYS02, 24, 0, 0),
959 GATE(PHYCLK_USBDRD300_UDRD30_PHYCLK_USER,
960 "phyclk_usbdrd300_udrd30_phyclk_user",
961 "mout_phyclk_usbdrd300_udrd30_phyclk_user",
962 ENABLE_SCLK_FSYS02, 28, 0, 0),
964 GATE(OSCCLK_PHY_CLKOUT_USB30_PHY, "oscclk_phy_clkout_usb30_phy",
966 ENABLE_SCLK_FSYS04, 28, 0, 0),
969 static const struct samsung_cmu_info fsys0_cmu_info __initconst = {
970 .fixed_clks = fixed_rate_clks_fsys0,
971 .nr_fixed_clks = ARRAY_SIZE(fixed_rate_clks_fsys0),
972 .mux_clks = fsys0_mux_clks,
973 .nr_mux_clks = ARRAY_SIZE(fsys0_mux_clks),
974 .gate_clks = fsys0_gate_clks,
975 .nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks),
976 .nr_clk_ids = FSYS0_NR_CLK,
977 .clk_regs = fsys0_clk_regs,
978 .nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs),
981 static void __init exynos7_clk_fsys0_init(struct device_node *np)
983 samsung_cmu_register_one(np, &fsys0_cmu_info);
986 CLK_OF_DECLARE(exynos7_clk_fsys0, "samsung,exynos7-clock-fsys0",
987 exynos7_clk_fsys0_init);
989 /* Register Offset definitions for CMU_FSYS1 (0x156E0000) */
990 #define MUX_SEL_FSYS10 0x0200
991 #define MUX_SEL_FSYS11 0x0204
992 #define MUX_SEL_FSYS12 0x0208
993 #define DIV_FSYS1 0x0600
994 #define ENABLE_ACLK_FSYS1 0x0800
995 #define ENABLE_PCLK_FSYS1 0x0900
996 #define ENABLE_SCLK_FSYS11 0x0A04
997 #define ENABLE_SCLK_FSYS12 0x0A08
998 #define ENABLE_SCLK_FSYS13 0x0A0C
1001 * List of parent clocks for Muxes in CMU_FSYS1
1003 PNAME(mout_aclk_fsys1_200_user_p) = { "fin_pll", "aclk_fsys1_200" };
1004 PNAME(mout_fsys1_group_p) = { "fin_pll", "fin_pll_26m",
1005 "sclk_phy_fsys1_26m" };
1006 PNAME(mout_sclk_mmc0_user_p) = { "fin_pll", "sclk_mmc0" };
1007 PNAME(mout_sclk_mmc1_user_p) = { "fin_pll", "sclk_mmc1" };
1008 PNAME(mout_sclk_ufsunipro20_user_p) = { "fin_pll", "sclk_ufsunipro20" };
1009 PNAME(mout_phyclk_ufs20_tx0_user_p) = { "fin_pll", "phyclk_ufs20_tx0_symbol" };
1010 PNAME(mout_phyclk_ufs20_rx0_user_p) = { "fin_pll", "phyclk_ufs20_rx0_symbol" };
1011 PNAME(mout_phyclk_ufs20_rx1_user_p) = { "fin_pll", "phyclk_ufs20_rx1_symbol" };
1013 /* fixed rate clocks used in the FSYS1 block */
1014 static const struct samsung_fixed_rate_clock fixed_rate_clks_fsys1[] __initconst = {
1015 FRATE(PHYCLK_UFS20_TX0_SYMBOL, "phyclk_ufs20_tx0_symbol", NULL,
1017 FRATE(PHYCLK_UFS20_RX0_SYMBOL, "phyclk_ufs20_rx0_symbol", NULL,
1019 FRATE(PHYCLK_UFS20_RX1_SYMBOL, "phyclk_ufs20_rx1_symbol", NULL,
1023 static const unsigned long fsys1_clk_regs[] __initconst = {
1035 static const struct samsung_mux_clock fsys1_mux_clks[] __initconst = {
1036 MUX(MOUT_FSYS1_PHYCLK_SEL1, "mout_fsys1_phyclk_sel1",
1037 mout_fsys1_group_p, MUX_SEL_FSYS10, 16, 2),
1038 MUX(0, "mout_fsys1_phyclk_sel0", mout_fsys1_group_p,
1039 MUX_SEL_FSYS10, 20, 2),
1040 MUX(0, "mout_aclk_fsys1_200_user", mout_aclk_fsys1_200_user_p,
1041 MUX_SEL_FSYS10, 28, 1),
1043 MUX(0, "mout_sclk_mmc1_user", mout_sclk_mmc1_user_p,
1044 MUX_SEL_FSYS11, 24, 1),
1045 MUX(0, "mout_sclk_mmc0_user", mout_sclk_mmc0_user_p,
1046 MUX_SEL_FSYS11, 28, 1),
1047 MUX(0, "mout_sclk_ufsunipro20_user", mout_sclk_ufsunipro20_user_p,
1048 MUX_SEL_FSYS11, 20, 1),
1050 MUX(0, "mout_phyclk_ufs20_rx1_symbol_user",
1051 mout_phyclk_ufs20_rx1_user_p, MUX_SEL_FSYS12, 16, 1),
1052 MUX(0, "mout_phyclk_ufs20_rx0_symbol_user",
1053 mout_phyclk_ufs20_rx0_user_p, MUX_SEL_FSYS12, 24, 1),
1054 MUX(0, "mout_phyclk_ufs20_tx0_symbol_user",
1055 mout_phyclk_ufs20_tx0_user_p, MUX_SEL_FSYS12, 28, 1),
1058 static const struct samsung_div_clock fsys1_div_clks[] __initconst = {
1059 DIV(DOUT_PCLK_FSYS1, "dout_pclk_fsys1", "mout_aclk_fsys1_200_user",
1063 static const struct samsung_gate_clock fsys1_gate_clks[] __initconst = {
1064 GATE(SCLK_UFSUNIPRO20_USER, "sclk_ufsunipro20_user",
1065 "mout_sclk_ufsunipro20_user",
1066 ENABLE_SCLK_FSYS11, 20, 0, 0),
1068 GATE(ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys1_200_user",
1069 ENABLE_ACLK_FSYS1, 29, 0, 0),
1070 GATE(ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys1_200_user",
1071 ENABLE_ACLK_FSYS1, 30, 0, 0),
1073 GATE(ACLK_UFS20_LINK, "aclk_ufs20_link", "dout_pclk_fsys1",
1074 ENABLE_ACLK_FSYS1, 31, 0, 0),
1075 GATE(PCLK_GPIO_FSYS1, "pclk_gpio_fsys1", "mout_aclk_fsys1_200_user",
1076 ENABLE_PCLK_FSYS1, 30, 0, 0),
1078 GATE(PHYCLK_UFS20_RX1_SYMBOL_USER, "phyclk_ufs20_rx1_symbol_user",
1079 "mout_phyclk_ufs20_rx1_symbol_user",
1080 ENABLE_SCLK_FSYS12, 16, 0, 0),
1081 GATE(PHYCLK_UFS20_RX0_SYMBOL_USER, "phyclk_ufs20_rx0_symbol_user",
1082 "mout_phyclk_ufs20_rx0_symbol_user",
1083 ENABLE_SCLK_FSYS12, 24, 0, 0),
1084 GATE(PHYCLK_UFS20_TX0_SYMBOL_USER, "phyclk_ufs20_tx0_symbol_user",
1085 "mout_phyclk_ufs20_tx0_symbol_user",
1086 ENABLE_SCLK_FSYS12, 28, 0, 0),
1088 GATE(OSCCLK_PHY_CLKOUT_EMBEDDED_COMBO_PHY,
1089 "oscclk_phy_clkout_embedded_combo_phy",
1091 ENABLE_SCLK_FSYS12, 4, CLK_IGNORE_UNUSED, 0),
1093 GATE(SCLK_COMBO_PHY_EMBEDDED_26M, "sclk_combo_phy_embedded_26m",
1094 "mout_fsys1_phyclk_sel1",
1095 ENABLE_SCLK_FSYS13, 24, CLK_IGNORE_UNUSED, 0),
1098 static const struct samsung_cmu_info fsys1_cmu_info __initconst = {
1099 .fixed_clks = fixed_rate_clks_fsys1,
1100 .nr_fixed_clks = ARRAY_SIZE(fixed_rate_clks_fsys1),
1101 .mux_clks = fsys1_mux_clks,
1102 .nr_mux_clks = ARRAY_SIZE(fsys1_mux_clks),
1103 .div_clks = fsys1_div_clks,
1104 .nr_div_clks = ARRAY_SIZE(fsys1_div_clks),
1105 .gate_clks = fsys1_gate_clks,
1106 .nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks),
1107 .nr_clk_ids = FSYS1_NR_CLK,
1108 .clk_regs = fsys1_clk_regs,
1109 .nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs),
1112 static void __init exynos7_clk_fsys1_init(struct device_node *np)
1114 samsung_cmu_register_one(np, &fsys1_cmu_info);
1117 CLK_OF_DECLARE(exynos7_clk_fsys1, "samsung,exynos7-clock-fsys1",
1118 exynos7_clk_fsys1_init);
1120 #define MUX_SEL_MSCL 0x0200
1121 #define DIV_MSCL 0x0600
1122 #define ENABLE_ACLK_MSCL 0x0800
1123 #define ENABLE_PCLK_MSCL 0x0900
1125 /* List of parent clocks for Muxes in CMU_MSCL */
1126 PNAME(mout_aclk_mscl_532_user_p) = { "fin_pll", "aclk_mscl_532" };
1128 static const unsigned long mscl_clk_regs[] __initconst = {
1135 static const struct samsung_mux_clock mscl_mux_clks[] __initconst = {
1136 MUX(USERMUX_ACLK_MSCL_532, "usermux_aclk_mscl_532",
1137 mout_aclk_mscl_532_user_p, MUX_SEL_MSCL, 0, 1),
1139 static const struct samsung_div_clock mscl_div_clks[] __initconst = {
1140 DIV(DOUT_PCLK_MSCL, "dout_pclk_mscl", "usermux_aclk_mscl_532",
1143 static const struct samsung_gate_clock mscl_gate_clks[] __initconst = {
1145 GATE(ACLK_MSCL_0, "aclk_mscl_0", "usermux_aclk_mscl_532",
1146 ENABLE_ACLK_MSCL, 31, 0, 0),
1147 GATE(ACLK_MSCL_1, "aclk_mscl_1", "usermux_aclk_mscl_532",
1148 ENABLE_ACLK_MSCL, 30, 0, 0),
1149 GATE(ACLK_JPEG, "aclk_jpeg", "usermux_aclk_mscl_532",
1150 ENABLE_ACLK_MSCL, 29, 0, 0),
1151 GATE(ACLK_G2D, "aclk_g2d", "usermux_aclk_mscl_532",
1152 ENABLE_ACLK_MSCL, 28, 0, 0),
1153 GATE(ACLK_LH_ASYNC_SI_MSCL_0, "aclk_lh_async_si_mscl_0",
1154 "usermux_aclk_mscl_532",
1155 ENABLE_ACLK_MSCL, 27, 0, 0),
1156 GATE(ACLK_LH_ASYNC_SI_MSCL_1, "aclk_lh_async_si_mscl_1",
1157 "usermux_aclk_mscl_532",
1158 ENABLE_ACLK_MSCL, 26, 0, 0),
1159 GATE(ACLK_XIU_MSCLX_0, "aclk_xiu_msclx_0", "usermux_aclk_mscl_532",
1160 ENABLE_ACLK_MSCL, 25, 0, 0),
1161 GATE(ACLK_XIU_MSCLX_1, "aclk_xiu_msclx_1", "usermux_aclk_mscl_532",
1162 ENABLE_ACLK_MSCL, 24, 0, 0),
1163 GATE(ACLK_AXI2ACEL_BRIDGE, "aclk_axi2acel_bridge",
1164 "usermux_aclk_mscl_532",
1165 ENABLE_ACLK_MSCL, 23, 0, 0),
1166 GATE(ACLK_QE_MSCL_0, "aclk_qe_mscl_0", "usermux_aclk_mscl_532",
1167 ENABLE_ACLK_MSCL, 22, 0, 0),
1168 GATE(ACLK_QE_MSCL_1, "aclk_qe_mscl_1", "usermux_aclk_mscl_532",
1169 ENABLE_ACLK_MSCL, 21, 0, 0),
1170 GATE(ACLK_QE_JPEG, "aclk_qe_jpeg", "usermux_aclk_mscl_532",
1171 ENABLE_ACLK_MSCL, 20, 0, 0),
1172 GATE(ACLK_QE_G2D, "aclk_qe_g2d", "usermux_aclk_mscl_532",
1173 ENABLE_ACLK_MSCL, 19, 0, 0),
1174 GATE(ACLK_PPMU_MSCL_0, "aclk_ppmu_mscl_0", "usermux_aclk_mscl_532",
1175 ENABLE_ACLK_MSCL, 18, 0, 0),
1176 GATE(ACLK_PPMU_MSCL_1, "aclk_ppmu_mscl_1", "usermux_aclk_mscl_532",
1177 ENABLE_ACLK_MSCL, 17, 0, 0),
1178 GATE(ACLK_MSCLNP_133, "aclk_msclnp_133", "usermux_aclk_mscl_532",
1179 ENABLE_ACLK_MSCL, 16, 0, 0),
1180 GATE(ACLK_AHB2APB_MSCL0P, "aclk_ahb2apb_mscl0p",
1181 "usermux_aclk_mscl_532",
1182 ENABLE_ACLK_MSCL, 15, 0, 0),
1183 GATE(ACLK_AHB2APB_MSCL1P, "aclk_ahb2apb_mscl1p",
1184 "usermux_aclk_mscl_532",
1185 ENABLE_ACLK_MSCL, 14, 0, 0),
1187 GATE(PCLK_MSCL_0, "pclk_mscl_0", "dout_pclk_mscl",
1188 ENABLE_PCLK_MSCL, 31, 0, 0),
1189 GATE(PCLK_MSCL_1, "pclk_mscl_1", "dout_pclk_mscl",
1190 ENABLE_PCLK_MSCL, 30, 0, 0),
1191 GATE(PCLK_JPEG, "pclk_jpeg", "dout_pclk_mscl",
1192 ENABLE_PCLK_MSCL, 29, 0, 0),
1193 GATE(PCLK_G2D, "pclk_g2d", "dout_pclk_mscl",
1194 ENABLE_PCLK_MSCL, 28, 0, 0),
1195 GATE(PCLK_QE_MSCL_0, "pclk_qe_mscl_0", "dout_pclk_mscl",
1196 ENABLE_PCLK_MSCL, 27, 0, 0),
1197 GATE(PCLK_QE_MSCL_1, "pclk_qe_mscl_1", "dout_pclk_mscl",
1198 ENABLE_PCLK_MSCL, 26, 0, 0),
1199 GATE(PCLK_QE_JPEG, "pclk_qe_jpeg", "dout_pclk_mscl",
1200 ENABLE_PCLK_MSCL, 25, 0, 0),
1201 GATE(PCLK_QE_G2D, "pclk_qe_g2d", "dout_pclk_mscl",
1202 ENABLE_PCLK_MSCL, 24, 0, 0),
1203 GATE(PCLK_PPMU_MSCL_0, "pclk_ppmu_mscl_0", "dout_pclk_mscl",
1204 ENABLE_PCLK_MSCL, 23, 0, 0),
1205 GATE(PCLK_PPMU_MSCL_1, "pclk_ppmu_mscl_1", "dout_pclk_mscl",
1206 ENABLE_PCLK_MSCL, 22, 0, 0),
1207 GATE(PCLK_AXI2ACEL_BRIDGE, "pclk_axi2acel_bridge", "dout_pclk_mscl",
1208 ENABLE_PCLK_MSCL, 21, 0, 0),
1209 GATE(PCLK_PMU_MSCL, "pclk_pmu_mscl", "dout_pclk_mscl",
1210 ENABLE_PCLK_MSCL, 20, 0, 0),
1213 static const struct samsung_cmu_info mscl_cmu_info __initconst = {
1214 .mux_clks = mscl_mux_clks,
1215 .nr_mux_clks = ARRAY_SIZE(mscl_mux_clks),
1216 .div_clks = mscl_div_clks,
1217 .nr_div_clks = ARRAY_SIZE(mscl_div_clks),
1218 .gate_clks = mscl_gate_clks,
1219 .nr_gate_clks = ARRAY_SIZE(mscl_gate_clks),
1220 .nr_clk_ids = MSCL_NR_CLK,
1221 .clk_regs = mscl_clk_regs,
1222 .nr_clk_regs = ARRAY_SIZE(mscl_clk_regs),
1225 static void __init exynos7_clk_mscl_init(struct device_node *np)
1227 samsung_cmu_register_one(np, &mscl_cmu_info);
1230 CLK_OF_DECLARE(exynos7_clk_mscl, "samsung,exynos7-clock-mscl",
1231 exynos7_clk_mscl_init);
1233 /* Register Offset definitions for CMU_AUD (0x114C0000) */
1234 #define MUX_SEL_AUD 0x0200
1235 #define DIV_AUD0 0x0600
1236 #define DIV_AUD1 0x0604
1237 #define ENABLE_ACLK_AUD 0x0800
1238 #define ENABLE_PCLK_AUD 0x0900
1239 #define ENABLE_SCLK_AUD 0x0A00
1242 * List of parent clocks for Muxes in CMU_AUD
1244 PNAME(mout_aud_pll_user_p) = { "fin_pll", "fout_aud_pll" };
1245 PNAME(mout_aud_group_p) = { "dout_aud_cdclk", "ioclk_audiocdclk0" };
1247 static const unsigned long aud_clk_regs[] __initconst = {
1256 static const struct samsung_mux_clock aud_mux_clks[] __initconst = {
1257 MUX(0, "mout_sclk_i2s", mout_aud_group_p, MUX_SEL_AUD, 12, 1),
1258 MUX(0, "mout_sclk_pcm", mout_aud_group_p, MUX_SEL_AUD, 16, 1),
1259 MUX(0, "mout_aud_pll_user", mout_aud_pll_user_p, MUX_SEL_AUD, 20, 1),
1262 static const struct samsung_div_clock aud_div_clks[] __initconst = {
1263 DIV(0, "dout_aud_ca5", "mout_aud_pll_user", DIV_AUD0, 0, 4),
1264 DIV(0, "dout_aclk_aud", "dout_aud_ca5", DIV_AUD0, 4, 4),
1265 DIV(0, "dout_aud_pclk_dbg", "dout_aud_ca5", DIV_AUD0, 8, 4),
1267 DIV(0, "dout_sclk_i2s", "mout_sclk_i2s", DIV_AUD1, 0, 4),
1268 DIV(0, "dout_sclk_pcm", "mout_sclk_pcm", DIV_AUD1, 4, 8),
1269 DIV(0, "dout_sclk_uart", "dout_aud_cdclk", DIV_AUD1, 12, 4),
1270 DIV(0, "dout_sclk_slimbus", "dout_aud_cdclk", DIV_AUD1, 16, 5),
1271 DIV(0, "dout_aud_cdclk", "mout_aud_pll_user", DIV_AUD1, 24, 4),
1274 static const struct samsung_gate_clock aud_gate_clks[] __initconst = {
1275 GATE(SCLK_PCM, "sclk_pcm", "dout_sclk_pcm",
1276 ENABLE_SCLK_AUD, 27, CLK_SET_RATE_PARENT, 0),
1277 GATE(SCLK_I2S, "sclk_i2s", "dout_sclk_i2s",
1278 ENABLE_SCLK_AUD, 28, CLK_SET_RATE_PARENT, 0),
1279 GATE(0, "sclk_uart", "dout_sclk_uart", ENABLE_SCLK_AUD, 29, 0, 0),
1280 GATE(0, "sclk_slimbus", "dout_sclk_slimbus",
1281 ENABLE_SCLK_AUD, 30, 0, 0),
1283 GATE(0, "pclk_dbg_aud", "dout_aud_pclk_dbg", ENABLE_PCLK_AUD, 19, 0, 0),
1284 GATE(0, "pclk_gpio_aud", "dout_aclk_aud", ENABLE_PCLK_AUD, 20, 0, 0),
1285 GATE(0, "pclk_wdt1", "dout_aclk_aud", ENABLE_PCLK_AUD, 22, 0, 0),
1286 GATE(0, "pclk_wdt0", "dout_aclk_aud", ENABLE_PCLK_AUD, 23, 0, 0),
1287 GATE(0, "pclk_slimbus", "dout_aclk_aud", ENABLE_PCLK_AUD, 24, 0, 0),
1288 GATE(0, "pclk_uart", "dout_aclk_aud", ENABLE_PCLK_AUD, 25, 0, 0),
1289 GATE(PCLK_PCM, "pclk_pcm", "dout_aclk_aud",
1290 ENABLE_PCLK_AUD, 26, CLK_SET_RATE_PARENT, 0),
1291 GATE(PCLK_I2S, "pclk_i2s", "dout_aclk_aud",
1292 ENABLE_PCLK_AUD, 27, CLK_SET_RATE_PARENT, 0),
1293 GATE(0, "pclk_timer", "dout_aclk_aud", ENABLE_PCLK_AUD, 28, 0, 0),
1294 GATE(0, "pclk_smmu_aud", "dout_aclk_aud", ENABLE_PCLK_AUD, 31, 0, 0),
1296 GATE(0, "aclk_smmu_aud", "dout_aclk_aud", ENABLE_ACLK_AUD, 27, 0, 0),
1297 GATE(0, "aclk_acel_lh_async_si_top", "dout_aclk_aud",
1298 ENABLE_ACLK_AUD, 28, 0, 0),
1299 GATE(ACLK_ADMA, "aclk_dmac", "dout_aclk_aud", ENABLE_ACLK_AUD, 31, 0, 0),
1302 static const struct samsung_cmu_info aud_cmu_info __initconst = {
1303 .mux_clks = aud_mux_clks,
1304 .nr_mux_clks = ARRAY_SIZE(aud_mux_clks),
1305 .div_clks = aud_div_clks,
1306 .nr_div_clks = ARRAY_SIZE(aud_div_clks),
1307 .gate_clks = aud_gate_clks,
1308 .nr_gate_clks = ARRAY_SIZE(aud_gate_clks),
1309 .nr_clk_ids = AUD_NR_CLK,
1310 .clk_regs = aud_clk_regs,
1311 .nr_clk_regs = ARRAY_SIZE(aud_clk_regs),
1314 static void __init exynos7_clk_aud_init(struct device_node *np)
1316 samsung_cmu_register_one(np, &aud_cmu_info);
1319 CLK_OF_DECLARE(exynos7_clk_aud, "samsung,exynos7-clock-aud",
1320 exynos7_clk_aud_init);