2 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
3 * Author: Chanwoo Choi <cw00.choi@samsung.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * Common Clock Framework support for Exynos5443 SoC.
12 #include <linux/clk-provider.h>
14 #include <linux/of_address.h>
16 #include <dt-bindings/clock/exynos5433.h>
23 * Register offset definitions for CMU_TOP
25 #define ISP_PLL_LOCK 0x0000
26 #define AUD_PLL_LOCK 0x0004
27 #define ISP_PLL_CON0 0x0100
28 #define ISP_PLL_CON1 0x0104
29 #define ISP_PLL_FREQ_DET 0x0108
30 #define AUD_PLL_CON0 0x0110
31 #define AUD_PLL_CON1 0x0114
32 #define AUD_PLL_CON2 0x0118
33 #define AUD_PLL_FREQ_DET 0x011c
34 #define MUX_SEL_TOP0 0x0200
35 #define MUX_SEL_TOP1 0x0204
36 #define MUX_SEL_TOP2 0x0208
37 #define MUX_SEL_TOP3 0x020c
38 #define MUX_SEL_TOP4 0x0210
39 #define MUX_SEL_TOP_MSCL 0x0220
40 #define MUX_SEL_TOP_CAM1 0x0224
41 #define MUX_SEL_TOP_DISP 0x0228
42 #define MUX_SEL_TOP_FSYS0 0x0230
43 #define MUX_SEL_TOP_FSYS1 0x0234
44 #define MUX_SEL_TOP_PERIC0 0x0238
45 #define MUX_SEL_TOP_PERIC1 0x023c
46 #define MUX_ENABLE_TOP0 0x0300
47 #define MUX_ENABLE_TOP1 0x0304
48 #define MUX_ENABLE_TOP2 0x0308
49 #define MUX_ENABLE_TOP3 0x030c
50 #define MUX_ENABLE_TOP4 0x0310
51 #define MUX_ENABLE_TOP_MSCL 0x0320
52 #define MUX_ENABLE_TOP_CAM1 0x0324
53 #define MUX_ENABLE_TOP_DISP 0x0328
54 #define MUX_ENABLE_TOP_FSYS0 0x0330
55 #define MUX_ENABLE_TOP_FSYS1 0x0334
56 #define MUX_ENABLE_TOP_PERIC0 0x0338
57 #define MUX_ENABLE_TOP_PERIC1 0x033c
58 #define MUX_STAT_TOP0 0x0400
59 #define MUX_STAT_TOP1 0x0404
60 #define MUX_STAT_TOP2 0x0408
61 #define MUX_STAT_TOP3 0x040c
62 #define MUX_STAT_TOP4 0x0410
63 #define MUX_STAT_TOP_MSCL 0x0420
64 #define MUX_STAT_TOP_CAM1 0x0424
65 #define MUX_STAT_TOP_FSYS0 0x0430
66 #define MUX_STAT_TOP_FSYS1 0x0434
67 #define MUX_STAT_TOP_PERIC0 0x0438
68 #define MUX_STAT_TOP_PERIC1 0x043c
69 #define DIV_TOP0 0x0600
70 #define DIV_TOP1 0x0604
71 #define DIV_TOP2 0x0608
72 #define DIV_TOP3 0x060c
73 #define DIV_TOP4 0x0610
74 #define DIV_TOP_MSCL 0x0618
75 #define DIV_TOP_CAM10 0x061c
76 #define DIV_TOP_CAM11 0x0620
77 #define DIV_TOP_FSYS0 0x062c
78 #define DIV_TOP_FSYS1 0x0630
79 #define DIV_TOP_FSYS2 0x0634
80 #define DIV_TOP_PERIC0 0x0638
81 #define DIV_TOP_PERIC1 0x063c
82 #define DIV_TOP_PERIC2 0x0640
83 #define DIV_TOP_PERIC3 0x0644
84 #define DIV_TOP_PERIC4 0x0648
85 #define DIV_TOP_PLL_FREQ_DET 0x064c
86 #define DIV_STAT_TOP0 0x0700
87 #define DIV_STAT_TOP1 0x0704
88 #define DIV_STAT_TOP2 0x0708
89 #define DIV_STAT_TOP3 0x070c
90 #define DIV_STAT_TOP4 0x0710
91 #define DIV_STAT_TOP_MSCL 0x0718
92 #define DIV_STAT_TOP_CAM10 0x071c
93 #define DIV_STAT_TOP_CAM11 0x0720
94 #define DIV_STAT_TOP_FSYS0 0x072c
95 #define DIV_STAT_TOP_FSYS1 0x0730
96 #define DIV_STAT_TOP_FSYS2 0x0734
97 #define DIV_STAT_TOP_PERIC0 0x0738
98 #define DIV_STAT_TOP_PERIC1 0x073c
99 #define DIV_STAT_TOP_PERIC2 0x0740
100 #define DIV_STAT_TOP_PERIC3 0x0744
101 #define DIV_STAT_TOP_PLL_FREQ_DET 0x074c
102 #define ENABLE_ACLK_TOP 0x0800
103 #define ENABLE_SCLK_TOP 0x0a00
104 #define ENABLE_SCLK_TOP_MSCL 0x0a04
105 #define ENABLE_SCLK_TOP_CAM1 0x0a08
106 #define ENABLE_SCLK_TOP_DISP 0x0a0c
107 #define ENABLE_SCLK_TOP_FSYS 0x0a10
108 #define ENABLE_SCLK_TOP_PERIC 0x0a14
109 #define ENABLE_IP_TOP 0x0b00
110 #define ENABLE_CMU_TOP 0x0c00
111 #define ENABLE_CMU_TOP_DIV_STAT 0x0c04
113 static const unsigned long top_clk_regs[] __initconst = {
143 MUX_ENABLE_TOP_FSYS0,
144 MUX_ENABLE_TOP_FSYS1,
145 MUX_ENABLE_TOP_PERIC0,
146 MUX_ENABLE_TOP_PERIC1,
163 DIV_TOP_PLL_FREQ_DET,
166 ENABLE_SCLK_TOP_MSCL,
167 ENABLE_SCLK_TOP_CAM1,
168 ENABLE_SCLK_TOP_DISP,
169 ENABLE_SCLK_TOP_FSYS,
170 ENABLE_SCLK_TOP_PERIC,
173 ENABLE_CMU_TOP_DIV_STAT,
176 /* list of all parent clock list */
177 PNAME(mout_aud_pll_p) = { "oscclk", "fout_aud_pll", };
178 PNAME(mout_isp_pll_p) = { "oscclk", "fout_isp_pll", };
179 PNAME(mout_aud_pll_user_p) = { "oscclk", "mout_aud_pll", };
180 PNAME(mout_mphy_pll_user_p) = { "oscclk", "sclk_mphy_pll", };
181 PNAME(mout_mfc_pll_user_p) = { "oscclk", "sclk_mfc_pll", };
182 PNAME(mout_bus_pll_user_p) = { "oscclk", "sclk_bus_pll", };
183 PNAME(mout_bus_pll_user_t_p) = { "oscclk", "mout_bus_pll_user", };
184 PNAME(mout_mphy_pll_user_t_p) = { "oscclk", "mout_mphy_pll_user", };
186 PNAME(mout_bus_mfc_pll_user_p) = { "mout_bus_pll_user", "mout_mfc_pll_user",};
187 PNAME(mout_mfc_bus_pll_user_p) = { "mout_mfc_pll_user", "mout_bus_pll_user",};
188 PNAME(mout_aclk_cam1_552_b_p) = { "mout_aclk_cam1_552_a",
189 "mout_mfc_pll_user", };
190 PNAME(mout_aclk_cam1_552_a_p) = { "mout_isp_pll", "mout_bus_pll_user", };
192 PNAME(mout_aclk_mfc_400_c_p) = { "mout_aclk_mfc_400_b",
193 "mout_mphy_pll_user", };
194 PNAME(mout_aclk_mfc_400_b_p) = { "mout_aclk_mfc_400_a",
195 "mout_bus_pll_user", };
196 PNAME(mout_aclk_mfc_400_a_p) = { "mout_mfc_pll_user", "mout_isp_pll", };
198 PNAME(mout_bus_mphy_pll_user_p) = { "mout_bus_pll_user",
199 "mout_mphy_pll_user", };
200 PNAME(mout_aclk_mscl_b_p) = { "mout_aclk_mscl_400_a",
201 "mout_mphy_pll_user", };
202 PNAME(mout_aclk_g2d_400_b_p) = { "mout_aclk_g2d_400_a",
203 "mout_mphy_pll_user", };
205 PNAME(mout_sclk_jpeg_c_p) = { "mout_sclk_jpeg_b", "mout_mphy_pll_user",};
206 PNAME(mout_sclk_jpeg_b_p) = { "mout_sclk_jpeg_a", "mout_mfc_pll_user", };
208 PNAME(mout_sclk_mmc2_b_p) = { "mout_sclk_mmc2_a", "mout_mfc_pll_user",};
209 PNAME(mout_sclk_mmc1_b_p) = { "mout_sclk_mmc1_a", "mout_mfc_pll_user",};
210 PNAME(mout_sclk_mmc0_d_p) = { "mout_sclk_mmc0_c", "mout_isp_pll", };
211 PNAME(mout_sclk_mmc0_c_p) = { "mout_sclk_mmc0_b", "mout_mphy_pll_user",};
212 PNAME(mout_sclk_mmc0_b_p) = { "mout_sclk_mmc0_a", "mout_mfc_pll_user", };
214 PNAME(mout_sclk_spdif_p) = { "sclk_audio0", "sclk_audio1",
215 "oscclk", "ioclk_spdif_extclk", };
216 PNAME(mout_sclk_audio1_p) = { "ioclk_audiocdclk1", "oscclk",
217 "mout_aud_pll_user_t",};
218 PNAME(mout_sclk_audio0_p) = { "ioclk_audiocdclk0", "oscclk",
219 "mout_aud_pll_user_t",};
221 PNAME(mout_sclk_hdmi_spdif_p) = { "sclk_audio1", "ioclk_spdif_extclk", };
223 static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initconst = {
224 FFACTOR(0, "oscclk_efuse_common", "oscclk", 1, 1, 0),
227 static const struct samsung_fixed_rate_clock top_fixed_clks[] __initconst = {
228 /* Xi2s{0|1}CDCLK input clock for I2S/PCM */
229 FRATE(0, "ioclk_audiocdclk1", NULL, 0, 100000000),
230 FRATE(0, "ioclk_audiocdclk0", NULL, 0, 100000000),
231 /* Xi2s1SDI input clock for SPDIF */
232 FRATE(0, "ioclk_spdif_extclk", NULL, 0, 100000000),
233 /* XspiCLK[4:0] input clock for SPI */
234 FRATE(0, "ioclk_spi4_clk_in", NULL, 0, 50000000),
235 FRATE(0, "ioclk_spi3_clk_in", NULL, 0, 50000000),
236 FRATE(0, "ioclk_spi2_clk_in", NULL, 0, 50000000),
237 FRATE(0, "ioclk_spi1_clk_in", NULL, 0, 50000000),
238 FRATE(0, "ioclk_spi0_clk_in", NULL, 0, 50000000),
239 /* Xi2s1SCLK input clock for I2S1_BCLK */
240 FRATE(0, "ioclk_i2s1_bclk_in", NULL, 0, 12288000),
243 static const struct samsung_mux_clock top_mux_clks[] __initconst = {
245 MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p, MUX_SEL_TOP0,
247 MUX(CLK_MOUT_ISP_PLL, "mout_isp_pll", mout_isp_pll_p, MUX_SEL_TOP0,
251 MUX(CLK_MOUT_AUD_PLL_USER_T, "mout_aud_pll_user_t",
252 mout_aud_pll_user_p, MUX_SEL_TOP1, 12, 1),
253 MUX(CLK_MOUT_MPHY_PLL_USER, "mout_mphy_pll_user", mout_mphy_pll_user_p,
255 MUX(CLK_MOUT_MFC_PLL_USER, "mout_mfc_pll_user", mout_mfc_pll_user_p,
257 MUX(CLK_MOUT_BUS_PLL_USER, "mout_bus_pll_user", mout_bus_pll_user_p,
261 MUX(CLK_MOUT_ACLK_HEVC_400, "mout_aclk_hevc_400",
262 mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 28, 1),
263 MUX(CLK_MOUT_ACLK_CAM1_333, "mout_aclk_cam1_333",
264 mout_mfc_bus_pll_user_p, MUX_SEL_TOP2, 16, 1),
265 MUX(CLK_MOUT_ACLK_CAM1_552_B, "mout_aclk_cam1_552_b",
266 mout_aclk_cam1_552_b_p, MUX_SEL_TOP2, 12, 1),
267 MUX(CLK_MOUT_ACLK_CAM1_552_A, "mout_aclk_cam1_552_a",
268 mout_aclk_cam1_552_a_p, MUX_SEL_TOP2, 8, 1),
269 MUX(CLK_MOUT_ACLK_ISP_DIS_400, "mout_aclk_isp_dis_400",
270 mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 4, 1),
271 MUX(CLK_MOUT_ACLK_ISP_400, "mout_aclk_isp_400",
272 mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 0, 1),
275 MUX(CLK_MOUT_ACLK_BUS0_400, "mout_aclk_bus0_400",
276 mout_bus_mphy_pll_user_p, MUX_SEL_TOP3, 20, 1),
277 MUX(CLK_MOUT_ACLK_MSCL_400_B, "mout_aclk_mscl_400_b",
278 mout_aclk_mscl_b_p, MUX_SEL_TOP3, 16, 1),
279 MUX(CLK_MOUT_ACLK_MSCL_400_A, "mout_aclk_mscl_400_a",
280 mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 12, 1),
281 MUX(CLK_MOUT_ACLK_GSCL_333, "mout_aclk_gscl_333",
282 mout_mfc_bus_pll_user_p, MUX_SEL_TOP3, 8, 1),
283 MUX(CLK_MOUT_ACLK_G2D_400_B, "mout_aclk_g2d_400_b",
284 mout_aclk_g2d_400_b_p, MUX_SEL_TOP3, 4, 1),
285 MUX(CLK_MOUT_ACLK_G2D_400_A, "mout_aclk_g2d_400_a",
286 mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 0, 1),
289 MUX(CLK_MOUT_ACLK_MFC_400_C, "mout_aclk_mfc_400_c",
290 mout_aclk_mfc_400_c_p, MUX_SEL_TOP4, 8, 1),
291 MUX(CLK_MOUT_ACLK_MFC_400_B, "mout_aclk_mfc_400_b",
292 mout_aclk_mfc_400_b_p, MUX_SEL_TOP4, 4, 1),
293 MUX(CLK_MOUT_ACLK_MFC_400_A, "mout_aclk_mfc_400_a",
294 mout_aclk_mfc_400_a_p, MUX_SEL_TOP4, 0, 1),
296 /* MUX_SEL_TOP_MSCL */
297 MUX(CLK_MOUT_SCLK_JPEG_C, "mout_sclk_jpeg_c", mout_sclk_jpeg_c_p,
298 MUX_SEL_TOP_MSCL, 8, 1),
299 MUX(CLK_MOUT_SCLK_JPEG_B, "mout_sclk_jpeg_b", mout_sclk_jpeg_b_p,
300 MUX_SEL_TOP_MSCL, 4, 1),
301 MUX(CLK_MOUT_SCLK_JPEG_A, "mout_sclk_jpeg_a", mout_bus_pll_user_t_p,
302 MUX_SEL_TOP_MSCL, 0, 1),
304 /* MUX_SEL_TOP_CAM1 */
305 MUX(CLK_MOUT_SCLK_ISP_SENSOR2, "mout_sclk_isp_sensor2",
306 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 24, 1),
307 MUX(CLK_MOUT_SCLK_ISP_SENSOR1, "mout_sclk_isp_sensor1",
308 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 20, 1),
309 MUX(CLK_MOUT_SCLK_ISP_SENSOR0, "mout_sclk_isp_sensor0",
310 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 16, 1),
311 MUX(CLK_MOUT_SCLK_ISP_UART, "mout_sclk_isp_uart",
312 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 8, 1),
313 MUX(CLK_MOUT_SCLK_ISP_SPI1, "mout_sclk_isp_spi1",
314 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 4, 1),
315 MUX(CLK_MOUT_SCLK_ISP_SPI0, "mout_sclk_isp_spi0",
316 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 0, 1),
318 /* MUX_SEL_TOP_FSYS0 */
319 MUX(CLK_MOUT_SCLK_MMC2_B, "mout_sclk_mmc2_b", mout_sclk_mmc2_b_p,
320 MUX_SEL_TOP_FSYS0, 28, 1),
321 MUX(CLK_MOUT_SCLK_MMC2_A, "mout_sclk_mmc2_a", mout_bus_pll_user_t_p,
322 MUX_SEL_TOP_FSYS0, 24, 1),
323 MUX(CLK_MOUT_SCLK_MMC1_B, "mout_sclk_mmc1_b", mout_sclk_mmc1_b_p,
324 MUX_SEL_TOP_FSYS0, 20, 1),
325 MUX(CLK_MOUT_SCLK_MMC1_A, "mout_sclk_mmc1_a", mout_bus_pll_user_t_p,
326 MUX_SEL_TOP_FSYS0, 16, 1),
327 MUX(CLK_MOUT_SCLK_MMC0_D, "mout_sclk_mmc0_d", mout_sclk_mmc0_d_p,
328 MUX_SEL_TOP_FSYS0, 12, 1),
329 MUX(CLK_MOUT_SCLK_MMC0_C, "mout_sclk_mmc0_c", mout_sclk_mmc0_c_p,
330 MUX_SEL_TOP_FSYS0, 8, 1),
331 MUX(CLK_MOUT_SCLK_MMC0_B, "mout_sclk_mmc0_b", mout_sclk_mmc0_b_p,
332 MUX_SEL_TOP_FSYS0, 4, 1),
333 MUX(CLK_MOUT_SCLK_MMC0_A, "mout_sclk_mmc0_a", mout_bus_pll_user_t_p,
334 MUX_SEL_TOP_FSYS0, 0, 1),
336 /* MUX_SEL_TOP_FSYS1 */
337 MUX(CLK_MOUT_SCLK_PCIE_100, "mout_sclk_pcie_100", mout_bus_pll_user_t_p,
338 MUX_SEL_TOP_FSYS1, 12, 1),
339 MUX(CLK_MOUT_SCLK_UFSUNIPRO, "mout_sclk_ufsunipro",
340 mout_mphy_pll_user_t_p, MUX_SEL_TOP_FSYS1, 8, 1),
341 MUX(CLK_MOUT_SCLK_USBHOST30, "mout_sclk_usbhost30",
342 mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 4, 1),
343 MUX(CLK_MOUT_SCLK_USBDRD30, "mout_sclk_usbdrd30",
344 mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 0, 1),
346 /* MUX_SEL_TOP_PERIC0 */
347 MUX(CLK_MOUT_SCLK_SPI4, "mout_sclk_spi4", mout_bus_pll_user_t_p,
348 MUX_SEL_TOP_PERIC0, 28, 1),
349 MUX(CLK_MOUT_SCLK_SPI3, "mout_sclk_spi3", mout_bus_pll_user_t_p,
350 MUX_SEL_TOP_PERIC0, 24, 1),
351 MUX(CLK_MOUT_SCLK_UART2, "mout_sclk_uart2", mout_bus_pll_user_t_p,
352 MUX_SEL_TOP_PERIC0, 20, 1),
353 MUX(CLK_MOUT_SCLK_UART1, "mout_sclk_uart1", mout_bus_pll_user_t_p,
354 MUX_SEL_TOP_PERIC0, 16, 1),
355 MUX(CLK_MOUT_SCLK_UART0, "mout_sclk_uart0", mout_bus_pll_user_t_p,
356 MUX_SEL_TOP_PERIC0, 12, 1),
357 MUX(CLK_MOUT_SCLK_SPI2, "mout_sclk_spi2", mout_bus_pll_user_t_p,
358 MUX_SEL_TOP_PERIC0, 8, 1),
359 MUX(CLK_MOUT_SCLK_SPI1, "mout_sclk_spi1", mout_bus_pll_user_t_p,
360 MUX_SEL_TOP_PERIC0, 4, 1),
361 MUX(CLK_MOUT_SCLK_SPI0, "mout_sclk_spi0", mout_bus_pll_user_t_p,
362 MUX_SEL_TOP_PERIC0, 0, 1),
364 /* MUX_SEL_TOP_PERIC1 */
365 MUX(CLK_MOUT_SCLK_SLIMBUS, "mout_sclk_slimbus", mout_aud_pll_user_p,
366 MUX_SEL_TOP_PERIC1, 16, 1),
367 MUX(CLK_MOUT_SCLK_SPDIF, "mout_sclk_spdif", mout_sclk_spdif_p,
368 MUX_SEL_TOP_PERIC1, 12, 2),
369 MUX(CLK_MOUT_SCLK_AUDIO1, "mout_sclk_audio1", mout_sclk_audio1_p,
370 MUX_SEL_TOP_PERIC1, 4, 2),
371 MUX(CLK_MOUT_SCLK_AUDIO0, "mout_sclk_audio0", mout_sclk_audio0_p,
372 MUX_SEL_TOP_PERIC1, 0, 2),
374 /* MUX_SEL_TOP_DISP */
375 MUX(CLK_MOUT_SCLK_HDMI_SPDIF, "mout_sclk_hdmi_spdif",
376 mout_sclk_hdmi_spdif_p, MUX_SEL_TOP_DISP, 0, 1),
379 static const struct samsung_div_clock top_div_clks[] __initconst = {
381 DIV(CLK_DIV_ACLK_CAM1_333, "div_aclk_cam1_333", "mout_aclk_cam1_333",
383 DIV(CLK_DIV_ACLK_CAM1_400, "div_aclk_cam1_400", "mout_bus_pll_user",
385 DIV(CLK_DIV_ACLK_CAM1_552, "div_aclk_cam1_552", "mout_aclk_cam1_552_b",
387 DIV(CLK_DIV_ACLK_CAM0_333, "div_aclk_cam0_333", "mout_mfc_pll_user",
389 DIV(CLK_DIV_ACLK_CAM0_400, "div_aclk_cam0_400", "mout_bus_pll_user",
391 DIV(CLK_DIV_ACLK_CAM0_552, "div_aclk_cam0_552", "mout_isp_pll",
393 DIV(CLK_DIV_ACLK_ISP_DIS_400, "div_aclk_isp_dis_400",
394 "mout_aclk_isp_dis_400", DIV_TOP0, 4, 4),
395 DIV(CLK_DIV_ACLK_ISP_400, "div_aclk_isp_400",
396 "mout_aclk_isp_400", DIV_TOP0, 0, 4),
399 DIV(CLK_DIV_ACLK_GSCL_111, "div_aclk_gscl_111", "mout_aclk_gscl_333",
401 DIV(CLK_DIV_ACLK_GSCL_333, "div_aclk_gscl_333", "mout_aclk_gscl_333",
403 DIV(CLK_DIV_ACLK_HEVC_400, "div_aclk_hevc_400", "mout_aclk_hevc_400",
405 DIV(CLK_DIV_ACLK_MFC_400, "div_aclk_mfc_400", "mout_aclk_mfc_400_c",
407 DIV(CLK_DIV_ACLK_G2D_266, "div_aclk_g2d_266", "mout_bus_pll_user",
409 DIV(CLK_DIV_ACLK_G2D_400, "div_aclk_g2d_400", "mout_aclk_g2d_400_b",
413 DIV(CLK_DIV_ACLK_MSCL_400, "div_aclk_mscl_400", "mout_aclk_mscl_400_b",
415 DIV(CLK_DIV_ACLK_FSYS_200, "div_aclk_fsys_200", "mout_bus_pll_user",
419 DIV(CLK_DIV_ACLK_IMEM_SSSX_266, "div_aclk_imem_sssx_266",
420 "mout_bus_pll_user", DIV_TOP3, 24, 3),
421 DIV(CLK_DIV_ACLK_IMEM_200, "div_aclk_imem_200",
422 "mout_bus_pll_user", DIV_TOP3, 20, 3),
423 DIV(CLK_DIV_ACLK_IMEM_266, "div_aclk_imem_266",
424 "mout_bus_pll_user", DIV_TOP3, 16, 3),
425 DIV(CLK_DIV_ACLK_PERIC_66_B, "div_aclk_peric_66_b",
426 "div_aclk_peric_66_a", DIV_TOP3, 12, 3),
427 DIV(CLK_DIV_ACLK_PERIC_66_A, "div_aclk_peric_66_a",
428 "mout_bus_pll_user", DIV_TOP3, 8, 3),
429 DIV(CLK_DIV_ACLK_PERIS_66_B, "div_aclk_peris_66_b",
430 "div_aclk_peris_66_a", DIV_TOP3, 4, 3),
431 DIV(CLK_DIV_ACLK_PERIS_66_A, "div_aclk_peris_66_a",
432 "mout_bus_pll_user", DIV_TOP3, 0, 3),
435 DIV(CLK_DIV_ACLK_G3D_400, "div_aclk_g3d_400", "mout_bus_pll_user",
437 DIV(CLK_DIV_ACLK_BUS0_400, "div_aclk_bus0_400", "mout_aclk_bus0_400",
439 DIV(CLK_DIV_ACLK_BUS1_400, "div_aclk_bus1_400", "mout_bus_pll_user",
443 DIV(CLK_DIV_SCLK_JPEG, "div_sclk_jpeg", "mout_sclk_jpeg_c",
447 DIV(CLK_DIV_SCLK_ISP_UART, "div_sclk_isp_uart", "mout_sclk_isp_uart",
448 DIV_TOP_CAM10, 24, 5),
449 DIV(CLK_DIV_SCLK_ISP_SPI1_B, "div_sclk_isp_spi1_b",
450 "div_sclk_isp_spi1_a", DIV_TOP_CAM10, 16, 8),
451 DIV(CLK_DIV_SCLK_ISP_SPI1_A, "div_sclk_isp_spi1_a",
452 "mout_sclk_isp_spi1", DIV_TOP_CAM10, 12, 4),
453 DIV(CLK_DIV_SCLK_ISP_SPI0_B, "div_sclk_isp_spi0_b",
454 "div_sclk_isp_spi0_a", DIV_TOP_CAM10, 4, 8),
455 DIV(CLK_DIV_SCLK_ISP_SPI0_A, "div_sclk_isp_spi0_a",
456 "mout_sclk_isp_spi0", DIV_TOP_CAM10, 0, 4),
459 DIV(CLK_DIV_SCLK_ISP_SENSOR2_B, "div_sclk_isp_sensor2_b",
460 "div_sclk_isp_sensor2_a", DIV_TOP_CAM11, 20, 4),
461 DIV(CLK_DIV_SCLK_ISP_SENSOR2_A, "div_sclk_isp_sensor2_a",
462 "mout_sclk_isp_sensor2", DIV_TOP_CAM11, 16, 4),
463 DIV(CLK_DIV_SCLK_ISP_SENSOR1_B, "div_sclk_isp_sensor1_b",
464 "div_sclk_isp_sensor1_a", DIV_TOP_CAM11, 12, 4),
465 DIV(CLK_DIV_SCLK_ISP_SENSOR1_A, "div_sclk_isp_sensor1_a",
466 "mout_sclk_isp_sensor1", DIV_TOP_CAM11, 8, 4),
467 DIV(CLK_DIV_SCLK_ISP_SENSOR0_B, "div_sclk_isp_sensor0_b",
468 "div_sclk_isp_sensor0_a", DIV_TOP_CAM11, 4, 4),
469 DIV(CLK_DIV_SCLK_ISP_SENSOR0_A, "div_sclk_isp_sensor0_a",
470 "mout_sclk_isp_sensor0", DIV_TOP_CAM11, 0, 4),
473 DIV(CLK_DIV_SCLK_MMC1_B, "div_sclk_mmc1_b", "div_sclk_mmc1_a",
474 DIV_TOP_FSYS0, 16, 8),
475 DIV(CLK_DIV_SCLK_MMC1_A, "div_sclk_mmc1_a", "mout_sclk_mmc1_b",
476 DIV_TOP_FSYS0, 12, 4),
477 DIV_F(CLK_DIV_SCLK_MMC0_B, "div_sclk_mmc0_b", "div_sclk_mmc0_a",
478 DIV_TOP_FSYS0, 4, 8, CLK_SET_RATE_PARENT, 0),
479 DIV_F(CLK_DIV_SCLK_MMC0_A, "div_sclk_mmc0_a", "mout_sclk_mmc0_d",
480 DIV_TOP_FSYS0, 0, 4, CLK_SET_RATE_PARENT, 0),
483 DIV(CLK_DIV_SCLK_MMC2_B, "div_sclk_mmc2_b", "div_sclk_mmc2_a",
484 DIV_TOP_FSYS1, 4, 8),
485 DIV(CLK_DIV_SCLK_MMC2_A, "div_sclk_mmc2_a", "mout_sclk_mmc2_b",
486 DIV_TOP_FSYS1, 0, 4),
489 DIV(CLK_DIV_SCLK_PCIE_100, "div_sclk_pcie_100", "mout_sclk_pcie_100",
490 DIV_TOP_FSYS2, 12, 3),
491 DIV(CLK_DIV_SCLK_USBHOST30, "div_sclk_usbhost30",
492 "mout_sclk_usbhost30", DIV_TOP_FSYS2, 8, 4),
493 DIV(CLK_DIV_SCLK_UFSUNIPRO, "div_sclk_ufsunipro",
494 "mout_sclk_ufsunipro", DIV_TOP_FSYS2, 4, 4),
495 DIV(CLK_DIV_SCLK_USBDRD30, "div_sclk_usbdrd30", "mout_sclk_usbdrd30",
496 DIV_TOP_FSYS2, 0, 4),
499 DIV(CLK_DIV_SCLK_SPI1_B, "div_sclk_spi1_b", "div_sclk_spi1_a",
500 DIV_TOP_PERIC0, 16, 8),
501 DIV(CLK_DIV_SCLK_SPI1_A, "div_sclk_spi1_a", "mout_sclk_spi1",
502 DIV_TOP_PERIC0, 12, 4),
503 DIV(CLK_DIV_SCLK_SPI0_B, "div_sclk_spi0_b", "div_sclk_spi0_a",
504 DIV_TOP_PERIC0, 4, 8),
505 DIV(CLK_DIV_SCLK_SPI0_A, "div_sclk_spi0_a", "mout_sclk_spi0",
506 DIV_TOP_PERIC0, 0, 4),
509 DIV(CLK_DIV_SCLK_SPI2_B, "div_sclk_spi2_b", "div_sclk_spi2_a",
510 DIV_TOP_PERIC1, 4, 8),
511 DIV(CLK_DIV_SCLK_SPI2_A, "div_sclk_spi2_a", "mout_sclk_spi2",
512 DIV_TOP_PERIC1, 0, 4),
515 DIV(CLK_DIV_SCLK_UART2, "div_sclk_uart2", "mout_sclk_uart2",
516 DIV_TOP_PERIC2, 8, 4),
517 DIV(CLK_DIV_SCLK_UART1, "div_sclk_uart1", "mout_sclk_uart0",
518 DIV_TOP_PERIC2, 4, 4),
519 DIV(CLK_DIV_SCLK_UART0, "div_sclk_uart0", "mout_sclk_uart1",
520 DIV_TOP_PERIC2, 0, 4),
523 DIV(CLK_DIV_SCLK_I2S1, "div_sclk_i2s1", "sclk_audio1",
524 DIV_TOP_PERIC3, 16, 6),
525 DIV(CLK_DIV_SCLK_PCM1, "div_sclk_pcm1", "sclk_audio1",
526 DIV_TOP_PERIC3, 8, 8),
527 DIV(CLK_DIV_SCLK_AUDIO1, "div_sclk_audio1", "mout_sclk_audio1",
528 DIV_TOP_PERIC3, 4, 4),
529 DIV(CLK_DIV_SCLK_AUDIO0, "div_sclk_audio0", "mout_sclk_audio0",
530 DIV_TOP_PERIC3, 0, 4),
533 DIV(CLK_DIV_SCLK_SPI4_B, "div_sclk_spi4_b", "div_sclk_spi4_a",
534 DIV_TOP_PERIC4, 16, 8),
535 DIV(CLK_DIV_SCLK_SPI4_A, "div_sclk_spi4_a", "mout_sclk_spi4",
536 DIV_TOP_PERIC4, 12, 4),
537 DIV(CLK_DIV_SCLK_SPI3_B, "div_sclk_spi3_b", "div_sclk_spi3_a",
538 DIV_TOP_PERIC4, 4, 8),
539 DIV(CLK_DIV_SCLK_SPI3_A, "div_sclk_spi3_a", "mout_sclk_spi3",
540 DIV_TOP_PERIC4, 0, 4),
543 static const struct samsung_gate_clock top_gate_clks[] __initconst = {
544 /* ENABLE_ACLK_TOP */
545 GATE(CLK_ACLK_G3D_400, "aclk_g3d_400", "div_aclk_g3d_400",
546 ENABLE_ACLK_TOP, 30, 0, 0),
547 GATE(CLK_ACLK_IMEM_SSX_266, "aclk_imem_ssx_266",
548 "div_aclk_imem_sssx_266", ENABLE_ACLK_TOP,
549 29, CLK_IGNORE_UNUSED, 0),
550 GATE(CLK_ACLK_BUS0_400, "aclk_bus0_400", "div_aclk_bus0_400",
552 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
553 GATE(CLK_ACLK_BUS1_400, "aclk_bus1_400", "div_aclk_bus1_400",
555 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
556 GATE(CLK_ACLK_IMEM_200, "aclk_imem_200", "div_aclk_imem_266",
558 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
559 GATE(CLK_ACLK_IMEM_266, "aclk_imem_266", "div_aclk_imem_200",
561 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
562 GATE(CLK_ACLK_PERIC_66, "aclk_peric_66", "div_aclk_peric_66_b",
564 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
565 GATE(CLK_ACLK_PERIS_66, "aclk_peris_66", "div_aclk_peris_66_b",
567 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
568 GATE(CLK_ACLK_MSCL_400, "aclk_mscl_400", "div_aclk_mscl_400",
570 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
571 GATE(CLK_ACLK_FSYS_200, "aclk_fsys_200", "div_aclk_fsys_200",
573 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
574 GATE(CLK_ACLK_GSCL_111, "aclk_gscl_111", "div_aclk_gscl_111",
576 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
577 GATE(CLK_ACLK_GSCL_333, "aclk_gscl_333", "div_aclk_gscl_333",
579 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
580 GATE(CLK_ACLK_CAM1_333, "aclk_cam1_333", "div_aclk_cam1_333",
582 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
583 GATE(CLK_ACLK_CAM1_400, "aclk_cam1_400", "div_aclk_cam1_400",
585 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
586 GATE(CLK_ACLK_CAM1_552, "aclk_cam1_552", "div_aclk_cam1_552",
588 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
589 GATE(CLK_ACLK_CAM0_333, "aclk_cam0_333", "div_aclk_cam0_333",
591 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
592 GATE(CLK_ACLK_CAM0_400, "aclk_cam0_400", "div_aclk_cam0_400",
594 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
595 GATE(CLK_ACLK_CAM0_552, "aclk_cam0_552", "div_aclk_cam0_552",
597 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
598 GATE(CLK_ACLK_ISP_DIS_400, "aclk_isp_dis_400", "div_aclk_isp_dis_400",
600 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
601 GATE(CLK_ACLK_ISP_400, "aclk_isp_400", "div_aclk_isp_400",
603 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
604 GATE(CLK_ACLK_HEVC_400, "aclk_hevc_400", "div_aclk_hevc_400",
606 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
607 GATE(CLK_ACLK_MFC_400, "aclk_mfc_400", "div_aclk_mfc_400",
609 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
610 GATE(CLK_ACLK_G2D_266, "aclk_g2d_266", "div_aclk_g2d_266",
612 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
613 GATE(CLK_ACLK_G2D_400, "aclk_g2d_400", "div_aclk_g2d_400",
615 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
617 /* ENABLE_SCLK_TOP_MSCL */
618 GATE(CLK_SCLK_JPEG_MSCL, "sclk_jpeg_mscl", "div_sclk_jpeg",
619 ENABLE_SCLK_TOP_MSCL, 0, 0, 0),
621 /* ENABLE_SCLK_TOP_CAM1 */
622 GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "div_sclk_isp_sensor2_b",
623 ENABLE_SCLK_TOP_CAM1, 7, 0, 0),
624 GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "div_sclk_isp_sensor1_b",
625 ENABLE_SCLK_TOP_CAM1, 6, 0, 0),
626 GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "div_sclk_isp_sensor0_b",
627 ENABLE_SCLK_TOP_CAM1, 5, 0, 0),
628 GATE(CLK_SCLK_ISP_MCTADC_CAM1, "sclk_isp_mctadc_cam1", "oscclk",
629 ENABLE_SCLK_TOP_CAM1, 4, 0, 0),
630 GATE(CLK_SCLK_ISP_UART_CAM1, "sclk_isp_uart_cam1", "div_sclk_isp_uart",
631 ENABLE_SCLK_TOP_CAM1, 2, 0, 0),
632 GATE(CLK_SCLK_ISP_SPI1_CAM1, "sclk_isp_spi1_cam1", "div_sclk_isp_spi1_b",
633 ENABLE_SCLK_TOP_CAM1, 1, 0, 0),
634 GATE(CLK_SCLK_ISP_SPI0_CAM1, "sclk_isp_spi0_cam1", "div_sclk_isp_spi0_b",
635 ENABLE_SCLK_TOP_CAM1, 0, 0, 0),
637 /* ENABLE_SCLK_TOP_DISP */
638 GATE(CLK_SCLK_HDMI_SPDIF_DISP, "sclk_hdmi_spdif_disp",
639 "mout_sclk_hdmi_spdif", ENABLE_SCLK_TOP_DISP, 0,
640 CLK_IGNORE_UNUSED, 0),
642 /* ENABLE_SCLK_TOP_FSYS */
643 GATE(CLK_SCLK_PCIE_100_FSYS, "sclk_pcie_100_fsys", "div_sclk_pcie_100",
644 ENABLE_SCLK_TOP_FSYS, 7, CLK_IGNORE_UNUSED, 0),
645 GATE(CLK_SCLK_MMC2_FSYS, "sclk_mmc2_fsys", "div_sclk_mmc2_b",
646 ENABLE_SCLK_TOP_FSYS, 6, CLK_SET_RATE_PARENT, 0),
647 GATE(CLK_SCLK_MMC1_FSYS, "sclk_mmc1_fsys", "div_sclk_mmc1_b",
648 ENABLE_SCLK_TOP_FSYS, 5, CLK_SET_RATE_PARENT, 0),
649 GATE(CLK_SCLK_MMC0_FSYS, "sclk_mmc0_fsys", "div_sclk_mmc0_b",
650 ENABLE_SCLK_TOP_FSYS, 4, CLK_SET_RATE_PARENT, 0),
651 GATE(CLK_SCLK_UFSUNIPRO_FSYS, "sclk_ufsunipro_fsys",
652 "div_sclk_ufsunipro", ENABLE_SCLK_TOP_FSYS,
653 3, CLK_SET_RATE_PARENT, 0),
654 GATE(CLK_SCLK_USBHOST30_FSYS, "sclk_usbhost30_fsys",
655 "div_sclk_usbhost30", ENABLE_SCLK_TOP_FSYS,
656 1, CLK_SET_RATE_PARENT, 0),
657 GATE(CLK_SCLK_USBDRD30_FSYS, "sclk_usbdrd30_fsys",
658 "div_sclk_usbdrd30", ENABLE_SCLK_TOP_FSYS,
659 0, CLK_SET_RATE_PARENT, 0),
661 /* ENABLE_SCLK_TOP_PERIC */
662 GATE(CLK_SCLK_SPI4_PERIC, "sclk_spi4_peric", "div_sclk_spi4_b",
663 ENABLE_SCLK_TOP_PERIC, 12, CLK_SET_RATE_PARENT, 0),
664 GATE(CLK_SCLK_SPI3_PERIC, "sclk_spi3_peric", "div_sclk_spi3_b",
665 ENABLE_SCLK_TOP_PERIC, 11, CLK_SET_RATE_PARENT, 0),
666 GATE(CLK_SCLK_SPDIF_PERIC, "sclk_spdif_peric", "mout_sclk_spdif",
667 ENABLE_SCLK_TOP_PERIC, 9, CLK_SET_RATE_PARENT, 0),
668 GATE(CLK_SCLK_I2S1_PERIC, "sclk_i2s1_peric", "div_sclk_i2s1",
669 ENABLE_SCLK_TOP_PERIC, 8, CLK_SET_RATE_PARENT, 0),
670 GATE(CLK_SCLK_PCM1_PERIC, "sclk_pcm1_peric", "div_sclk_pcm1",
671 ENABLE_SCLK_TOP_PERIC, 7, CLK_SET_RATE_PARENT, 0),
672 GATE(CLK_SCLK_UART2_PERIC, "sclk_uart2_peric", "div_sclk_uart2",
673 ENABLE_SCLK_TOP_PERIC, 5, CLK_SET_RATE_PARENT |
674 CLK_IGNORE_UNUSED, 0),
675 GATE(CLK_SCLK_UART1_PERIC, "sclk_uart1_peric", "div_sclk_uart1",
676 ENABLE_SCLK_TOP_PERIC, 4, CLK_SET_RATE_PARENT |
677 CLK_IGNORE_UNUSED, 0),
678 GATE(CLK_SCLK_UART0_PERIC, "sclk_uart0_peric", "div_sclk_uart0",
679 ENABLE_SCLK_TOP_PERIC, 3, CLK_SET_RATE_PARENT |
680 CLK_IGNORE_UNUSED, 0),
681 GATE(CLK_SCLK_SPI2_PERIC, "sclk_spi2_peric", "div_sclk_spi2_b",
682 ENABLE_SCLK_TOP_PERIC, 2, CLK_SET_RATE_PARENT, 0),
683 GATE(CLK_SCLK_SPI1_PERIC, "sclk_spi1_peric", "div_sclk_spi1_b",
684 ENABLE_SCLK_TOP_PERIC, 1, CLK_SET_RATE_PARENT, 0),
685 GATE(CLK_SCLK_SPI0_PERIC, "sclk_spi0_peric", "div_sclk_spi0_b",
686 ENABLE_SCLK_TOP_PERIC, 0, CLK_SET_RATE_PARENT, 0),
688 /* MUX_ENABLE_TOP_PERIC1 */
689 GATE(CLK_SCLK_SLIMBUS, "sclk_slimbus", "mout_sclk_slimbus",
690 MUX_ENABLE_TOP_PERIC1, 16, 0, 0),
691 GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_sclk_audio1",
692 MUX_ENABLE_TOP_PERIC1, 4, 0, 0),
693 GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_sclk_audio0",
694 MUX_ENABLE_TOP_PERIC1, 0, 0, 0),
698 * ATLAS_PLL & APOLLO_PLL & MEM0_PLL & MEM1_PLL & BUS_PLL & MFC_PLL
699 * & MPHY_PLL & G3D_PLL & DISP_PLL & ISP_PLL
701 static const struct samsung_pll_rate_table exynos5443_pll_rates[] __initconst = {
702 PLL_35XX_RATE(2500000000U, 625, 6, 0),
703 PLL_35XX_RATE(2400000000U, 500, 5, 0),
704 PLL_35XX_RATE(2300000000U, 575, 6, 0),
705 PLL_35XX_RATE(2200000000U, 550, 6, 0),
706 PLL_35XX_RATE(2100000000U, 350, 4, 0),
707 PLL_35XX_RATE(2000000000U, 500, 6, 0),
708 PLL_35XX_RATE(1900000000U, 475, 6, 0),
709 PLL_35XX_RATE(1800000000U, 375, 5, 0),
710 PLL_35XX_RATE(1700000000U, 425, 6, 0),
711 PLL_35XX_RATE(1600000000U, 400, 6, 0),
712 PLL_35XX_RATE(1500000000U, 250, 4, 0),
713 PLL_35XX_RATE(1400000000U, 350, 6, 0),
714 PLL_35XX_RATE(1332000000U, 222, 4, 0),
715 PLL_35XX_RATE(1300000000U, 325, 6, 0),
716 PLL_35XX_RATE(1200000000U, 500, 5, 1),
717 PLL_35XX_RATE(1100000000U, 550, 6, 1),
718 PLL_35XX_RATE(1086000000U, 362, 4, 1),
719 PLL_35XX_RATE(1066000000U, 533, 6, 1),
720 PLL_35XX_RATE(1000000000U, 500, 6, 1),
721 PLL_35XX_RATE(933000000U, 311, 4, 1),
722 PLL_35XX_RATE(921000000U, 307, 4, 1),
723 PLL_35XX_RATE(900000000U, 375, 5, 1),
724 PLL_35XX_RATE(825000000U, 275, 4, 1),
725 PLL_35XX_RATE(800000000U, 400, 6, 1),
726 PLL_35XX_RATE(733000000U, 733, 12, 1),
727 PLL_35XX_RATE(700000000U, 175, 3, 1),
728 PLL_35XX_RATE(666000000U, 222, 4, 1),
729 PLL_35XX_RATE(633000000U, 211, 4, 1),
730 PLL_35XX_RATE(600000000U, 500, 5, 2),
731 PLL_35XX_RATE(552000000U, 460, 5, 2),
732 PLL_35XX_RATE(550000000U, 550, 6, 2),
733 PLL_35XX_RATE(543000000U, 362, 4, 2),
734 PLL_35XX_RATE(533000000U, 533, 6, 2),
735 PLL_35XX_RATE(500000000U, 500, 6, 2),
736 PLL_35XX_RATE(444000000U, 370, 5, 2),
737 PLL_35XX_RATE(420000000U, 350, 5, 2),
738 PLL_35XX_RATE(400000000U, 400, 6, 2),
739 PLL_35XX_RATE(350000000U, 350, 6, 2),
740 PLL_35XX_RATE(333000000U, 222, 4, 2),
741 PLL_35XX_RATE(300000000U, 500, 5, 3),
742 PLL_35XX_RATE(266000000U, 532, 6, 3),
743 PLL_35XX_RATE(200000000U, 400, 6, 3),
744 PLL_35XX_RATE(166000000U, 332, 6, 3),
745 PLL_35XX_RATE(160000000U, 320, 6, 3),
746 PLL_35XX_RATE(133000000U, 532, 6, 4),
747 PLL_35XX_RATE(100000000U, 400, 6, 4),
752 static const struct samsung_pll_rate_table exynos5443_aud_pll_rates[] __initconst = {
753 PLL_36XX_RATE(400000000U, 200, 3, 2, 0),
754 PLL_36XX_RATE(393216003U, 197, 3, 2, -25690),
755 PLL_36XX_RATE(384000000U, 128, 2, 2, 0),
756 PLL_36XX_RATE(368639991U, 246, 4, 2, -15729),
757 PLL_36XX_RATE(361507202U, 181, 3, 2, -16148),
758 PLL_36XX_RATE(338687988U, 113, 2, 2, -6816),
759 PLL_36XX_RATE(294912002U, 98, 1, 3, 19923),
760 PLL_36XX_RATE(288000000U, 96, 1, 3, 0),
761 PLL_36XX_RATE(252000000U, 84, 1, 3, 0),
765 static const struct samsung_pll_clock top_pll_clks[] __initconst = {
766 PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "oscclk",
767 ISP_PLL_LOCK, ISP_PLL_CON0, exynos5443_pll_rates),
768 PLL(pll_36xx, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk",
769 AUD_PLL_LOCK, AUD_PLL_CON0, exynos5443_aud_pll_rates),
772 static const struct samsung_cmu_info top_cmu_info __initconst = {
773 .pll_clks = top_pll_clks,
774 .nr_pll_clks = ARRAY_SIZE(top_pll_clks),
775 .mux_clks = top_mux_clks,
776 .nr_mux_clks = ARRAY_SIZE(top_mux_clks),
777 .div_clks = top_div_clks,
778 .nr_div_clks = ARRAY_SIZE(top_div_clks),
779 .gate_clks = top_gate_clks,
780 .nr_gate_clks = ARRAY_SIZE(top_gate_clks),
781 .fixed_clks = top_fixed_clks,
782 .nr_fixed_clks = ARRAY_SIZE(top_fixed_clks),
783 .fixed_factor_clks = top_fixed_factor_clks,
784 .nr_fixed_factor_clks = ARRAY_SIZE(top_fixed_factor_clks),
785 .nr_clk_ids = TOP_NR_CLK,
786 .clk_regs = top_clk_regs,
787 .nr_clk_regs = ARRAY_SIZE(top_clk_regs),
790 static void __init exynos5433_cmu_top_init(struct device_node *np)
792 samsung_cmu_register_one(np, &top_cmu_info);
794 CLK_OF_DECLARE(exynos5433_cmu_top, "samsung,exynos5433-cmu-top",
795 exynos5433_cmu_top_init);
798 * Register offset definitions for CMU_CPIF
800 #define MPHY_PLL_LOCK 0x0000
801 #define MPHY_PLL_CON0 0x0100
802 #define MPHY_PLL_CON1 0x0104
803 #define MPHY_PLL_FREQ_DET 0x010c
804 #define MUX_SEL_CPIF0 0x0200
805 #define DIV_CPIF 0x0600
806 #define ENABLE_SCLK_CPIF 0x0a00
808 static const unsigned long cpif_clk_regs[] __initconst = {
818 /* list of all parent clock list */
819 PNAME(mout_mphy_pll_p) = { "oscclk", "fout_mphy_pll", };
821 static const struct samsung_pll_clock cpif_pll_clks[] __initconst = {
822 PLL(pll_35xx, CLK_FOUT_MPHY_PLL, "fout_mphy_pll", "oscclk",
823 MPHY_PLL_LOCK, MPHY_PLL_CON0, exynos5443_pll_rates),
826 static const struct samsung_mux_clock cpif_mux_clks[] __initconst = {
828 MUX(CLK_MOUT_MPHY_PLL, "mout_mphy_pll", mout_mphy_pll_p, MUX_SEL_CPIF0,
832 static const struct samsung_div_clock cpif_div_clks[] __initconst = {
834 DIV(CLK_DIV_SCLK_MPHY, "div_sclk_mphy", "mout_mphy_pll", DIV_CPIF,
838 static const struct samsung_gate_clock cpif_gate_clks[] __initconst = {
839 /* ENABLE_SCLK_CPIF */
840 GATE(CLK_SCLK_MPHY_PLL, "sclk_mphy_pll", "mout_mphy_pll",
841 ENABLE_SCLK_CPIF, 9, CLK_IGNORE_UNUSED, 0),
842 GATE(CLK_SCLK_UFS_MPHY, "sclk_ufs_mphy", "div_sclk_mphy",
843 ENABLE_SCLK_CPIF, 4, 0, 0),
846 static const struct samsung_cmu_info cpif_cmu_info __initconst = {
847 .pll_clks = cpif_pll_clks,
848 .nr_pll_clks = ARRAY_SIZE(cpif_pll_clks),
849 .mux_clks = cpif_mux_clks,
850 .nr_mux_clks = ARRAY_SIZE(cpif_mux_clks),
851 .div_clks = cpif_div_clks,
852 .nr_div_clks = ARRAY_SIZE(cpif_div_clks),
853 .gate_clks = cpif_gate_clks,
854 .nr_gate_clks = ARRAY_SIZE(cpif_gate_clks),
855 .nr_clk_ids = CPIF_NR_CLK,
856 .clk_regs = cpif_clk_regs,
857 .nr_clk_regs = ARRAY_SIZE(cpif_clk_regs),
860 static void __init exynos5433_cmu_cpif_init(struct device_node *np)
862 samsung_cmu_register_one(np, &cpif_cmu_info);
864 CLK_OF_DECLARE(exynos5433_cmu_cpif, "samsung,exynos5433-cmu-cpif",
865 exynos5433_cmu_cpif_init);
868 * Register offset definitions for CMU_MIF
870 #define MEM0_PLL_LOCK 0x0000
871 #define MEM1_PLL_LOCK 0x0004
872 #define BUS_PLL_LOCK 0x0008
873 #define MFC_PLL_LOCK 0x000c
874 #define MEM0_PLL_CON0 0x0100
875 #define MEM0_PLL_CON1 0x0104
876 #define MEM0_PLL_FREQ_DET 0x010c
877 #define MEM1_PLL_CON0 0x0110
878 #define MEM1_PLL_CON1 0x0114
879 #define MEM1_PLL_FREQ_DET 0x011c
880 #define BUS_PLL_CON0 0x0120
881 #define BUS_PLL_CON1 0x0124
882 #define BUS_PLL_FREQ_DET 0x012c
883 #define MFC_PLL_CON0 0x0130
884 #define MFC_PLL_CON1 0x0134
885 #define MFC_PLL_FREQ_DET 0x013c
886 #define MUX_SEL_MIF0 0x0200
887 #define MUX_SEL_MIF1 0x0204
888 #define MUX_SEL_MIF2 0x0208
889 #define MUX_SEL_MIF3 0x020c
890 #define MUX_SEL_MIF4 0x0210
891 #define MUX_SEL_MIF5 0x0214
892 #define MUX_SEL_MIF6 0x0218
893 #define MUX_SEL_MIF7 0x021c
894 #define MUX_ENABLE_MIF0 0x0300
895 #define MUX_ENABLE_MIF1 0x0304
896 #define MUX_ENABLE_MIF2 0x0308
897 #define MUX_ENABLE_MIF3 0x030c
898 #define MUX_ENABLE_MIF4 0x0310
899 #define MUX_ENABLE_MIF5 0x0314
900 #define MUX_ENABLE_MIF6 0x0318
901 #define MUX_ENABLE_MIF7 0x031c
902 #define MUX_STAT_MIF0 0x0400
903 #define MUX_STAT_MIF1 0x0404
904 #define MUX_STAT_MIF2 0x0408
905 #define MUX_STAT_MIF3 0x040c
906 #define MUX_STAT_MIF4 0x0410
907 #define MUX_STAT_MIF5 0x0414
908 #define MUX_STAT_MIF6 0x0418
909 #define MUX_STAT_MIF7 0x041c
910 #define DIV_MIF1 0x0604
911 #define DIV_MIF2 0x0608
912 #define DIV_MIF3 0x060c
913 #define DIV_MIF4 0x0610
914 #define DIV_MIF5 0x0614
915 #define DIV_MIF_PLL_FREQ_DET 0x0618
916 #define DIV_STAT_MIF1 0x0704
917 #define DIV_STAT_MIF2 0x0708
918 #define DIV_STAT_MIF3 0x070c
919 #define DIV_STAT_MIF4 0x0710
920 #define DIV_STAT_MIF5 0x0714
921 #define DIV_STAT_MIF_PLL_FREQ_DET 0x0718
922 #define ENABLE_ACLK_MIF0 0x0800
923 #define ENABLE_ACLK_MIF1 0x0804
924 #define ENABLE_ACLK_MIF2 0x0808
925 #define ENABLE_ACLK_MIF3 0x080c
926 #define ENABLE_PCLK_MIF 0x0900
927 #define ENABLE_PCLK_MIF_SECURE_DREX0_TZ 0x0904
928 #define ENABLE_PCLK_MIF_SECURE_DREX1_TZ 0x0908
929 #define ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT 0x090c
930 #define ENABLE_PCLK_MIF_SECURE_RTC 0x0910
931 #define ENABLE_SCLK_MIF 0x0a00
932 #define ENABLE_IP_MIF0 0x0b00
933 #define ENABLE_IP_MIF1 0x0b04
934 #define ENABLE_IP_MIF2 0x0b08
935 #define ENABLE_IP_MIF3 0x0b0c
936 #define ENABLE_IP_MIF_SECURE_DREX0_TZ 0x0b10
937 #define ENABLE_IP_MIF_SECURE_DREX1_TZ 0x0b14
938 #define ENABLE_IP_MIF_SECURE_MONOTONIC_CNT 0x0b18
939 #define ENABLE_IP_MIF_SECURE_RTC 0x0b1c
940 #define CLKOUT_CMU_MIF 0x0c00
941 #define CLKOUT_CMU_MIF_DIV_STAT 0x0c04
942 #define DREX_FREQ_CTRL0 0x1000
943 #define DREX_FREQ_CTRL1 0x1004
945 #define DDRPHY_LOCK_CTRL 0x100c
947 static const unsigned long mif_clk_regs[] __initconst = {
985 DIV_MIF_PLL_FREQ_DET,
991 ENABLE_PCLK_MIF_SECURE_DREX0_TZ,
992 ENABLE_PCLK_MIF_SECURE_DREX1_TZ,
993 ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT,
994 ENABLE_PCLK_MIF_SECURE_RTC,
1000 ENABLE_IP_MIF_SECURE_DREX0_TZ,
1001 ENABLE_IP_MIF_SECURE_DREX1_TZ,
1002 ENABLE_IP_MIF_SECURE_MONOTONIC_CNT,
1003 ENABLE_IP_MIF_SECURE_RTC,
1005 CLKOUT_CMU_MIF_DIV_STAT,
1012 static const struct samsung_pll_clock mif_pll_clks[] __initconst = {
1013 PLL(pll_35xx, CLK_FOUT_MEM0_PLL, "fout_mem0_pll", "oscclk",
1014 MEM0_PLL_LOCK, MEM0_PLL_CON0, exynos5443_pll_rates),
1015 PLL(pll_35xx, CLK_FOUT_MEM1_PLL, "fout_mem1_pll", "oscclk",
1016 MEM1_PLL_LOCK, MEM1_PLL_CON0, exynos5443_pll_rates),
1017 PLL(pll_35xx, CLK_FOUT_BUS_PLL, "fout_bus_pll", "oscclk",
1018 BUS_PLL_LOCK, BUS_PLL_CON0, exynos5443_pll_rates),
1019 PLL(pll_35xx, CLK_FOUT_MFC_PLL, "fout_mfc_pll", "oscclk",
1020 MFC_PLL_LOCK, MFC_PLL_CON0, exynos5443_pll_rates),
1023 /* list of all parent clock list */
1024 PNAME(mout_mfc_pll_div2_p) = { "mout_mfc_pll", "dout_mfc_pll", };
1025 PNAME(mout_bus_pll_div2_p) = { "mout_bus_pll", "dout_bus_pll", };
1026 PNAME(mout_mem1_pll_div2_p) = { "mout_mem1_pll", "dout_mem1_pll", };
1027 PNAME(mout_mem0_pll_div2_p) = { "mout_mem0_pll", "dout_mem0_pll", };
1028 PNAME(mout_mfc_pll_p) = { "oscclk", "fout_mfc_pll", };
1029 PNAME(mout_bus_pll_p) = { "oscclk", "fout_bus_pll", };
1030 PNAME(mout_mem1_pll_p) = { "oscclk", "fout_mem1_pll", };
1031 PNAME(mout_mem0_pll_p) = { "oscclk", "fout_mem0_pll", };
1033 PNAME(mout_clk2x_phy_c_p) = { "mout_mem0_pll_div2", "mout_clkm_phy_b", };
1034 PNAME(mout_clk2x_phy_b_p) = { "mout_bus_pll_div2", "mout_clkm_phy_a", };
1035 PNAME(mout_clk2x_phy_a_p) = { "mout_bus_pll_div2", "mout_mfc_pll_div2", };
1036 PNAME(mout_clkm_phy_b_p) = { "mout_mem1_pll_div2", "mout_clkm_phy_a", };
1038 PNAME(mout_aclk_mifnm_200_p) = { "mout_mem0_pll_div2", "div_mif_pre", };
1039 PNAME(mout_aclk_mifnm_400_p) = { "mout_mem1_pll_div2", "mout_bus_pll_div2",};
1041 PNAME(mout_aclk_disp_333_b_p) = { "mout_aclk_disp_333_a",
1042 "mout_bus_pll_div2", };
1043 PNAME(mout_aclk_disp_333_a_p) = { "mout_mfc_pll_div2", "sclk_mphy_pll", };
1045 PNAME(mout_sclk_decon_vclk_c_p) = { "mout_sclk_decon_vclk_b",
1047 PNAME(mout_sclk_decon_vclk_b_p) = { "mout_sclk_decon_vclk_a",
1048 "mout_mfc_pll_div2", };
1049 PNAME(mout_sclk_decon_p) = { "oscclk", "mout_bus_pll_div2", };
1050 PNAME(mout_sclk_decon_eclk_c_p) = { "mout_sclk_decon_eclk_b",
1052 PNAME(mout_sclk_decon_eclk_b_p) = { "mout_sclk_decon_eclk_a",
1053 "mout_mfc_pll_div2", };
1055 PNAME(mout_sclk_decon_tv_eclk_c_p) = { "mout_sclk_decon_tv_eclk_b",
1057 PNAME(mout_sclk_decon_tv_eclk_b_p) = { "mout_sclk_decon_tv_eclk_a",
1058 "mout_mfc_pll_div2", };
1059 PNAME(mout_sclk_dsd_c_p) = { "mout_sclk_dsd_b", "mout_bus_pll_div2", };
1060 PNAME(mout_sclk_dsd_b_p) = { "mout_sclk_dsd_a", "sclk_mphy_pll", };
1061 PNAME(mout_sclk_dsd_a_p) = { "oscclk", "mout_mfc_pll_div2", };
1063 PNAME(mout_sclk_dsim0_c_p) = { "mout_sclk_dsim0_b", "sclk_mphy_pll", };
1064 PNAME(mout_sclk_dsim0_b_p) = { "mout_sclk_dsim0_a", "mout_mfc_pll_div2" };
1066 PNAME(mout_sclk_decon_tv_vclk_c_p) = { "mout_sclk_decon_tv_vclk_b",
1068 PNAME(mout_sclk_decon_tv_vclk_b_p) = { "mout_sclk_decon_tv_vclk_a",
1069 "mout_mfc_pll_div2", };
1070 PNAME(mout_sclk_dsim1_c_p) = { "mout_sclk_dsim1_b", "sclk_mphy_pll", };
1071 PNAME(mout_sclk_dsim1_b_p) = { "mout_sclk_dsim1_a", "mout_mfc_pll_div2",};
1073 static const struct samsung_fixed_factor_clock mif_fixed_factor_clks[] __initconst = {
1074 /* dout_{mfc|bus|mem1|mem0}_pll is half fixed rate from parent mux */
1075 FFACTOR(CLK_DOUT_MFC_PLL, "dout_mfc_pll", "mout_mfc_pll", 1, 1, 0),
1076 FFACTOR(CLK_DOUT_BUS_PLL, "dout_bus_pll", "mout_bus_pll", 1, 1, 0),
1077 FFACTOR(CLK_DOUT_MEM1_PLL, "dout_mem1_pll", "mout_mem1_pll", 1, 1, 0),
1078 FFACTOR(CLK_DOUT_MEM0_PLL, "dout_mem0_pll", "mout_mem0_pll", 1, 1, 0),
1081 static const struct samsung_mux_clock mif_mux_clks[] __initconst = {
1083 MUX(CLK_MOUT_MFC_PLL_DIV2, "mout_mfc_pll_div2", mout_mfc_pll_div2_p,
1084 MUX_SEL_MIF0, 28, 1),
1085 MUX(CLK_MOUT_BUS_PLL_DIV2, "mout_bus_pll_div2", mout_bus_pll_div2_p,
1086 MUX_SEL_MIF0, 24, 1),
1087 MUX(CLK_MOUT_MEM1_PLL_DIV2, "mout_mem1_pll_div2", mout_mem1_pll_div2_p,
1088 MUX_SEL_MIF0, 20, 1),
1089 MUX(CLK_MOUT_MEM0_PLL_DIV2, "mout_mem0_pll_div2", mout_mem0_pll_div2_p,
1090 MUX_SEL_MIF0, 16, 1),
1091 MUX(CLK_MOUT_MFC_PLL, "mout_mfc_pll", mout_mfc_pll_p, MUX_SEL_MIF0,
1093 MUX(CLK_MOUT_BUS_PLL, "mout_bus_pll", mout_bus_pll_p, MUX_SEL_MIF0,
1095 MUX(CLK_MOUT_MEM1_PLL, "mout_mem1_pll", mout_mem1_pll_p, MUX_SEL_MIF0,
1097 MUX(CLK_MOUT_MEM0_PLL, "mout_mem0_pll", mout_mem0_pll_p, MUX_SEL_MIF0,
1101 MUX(CLK_MOUT_CLK2X_PHY_C, "mout_clk2x_phy_c", mout_clk2x_phy_c_p,
1102 MUX_SEL_MIF1, 24, 1),
1103 MUX(CLK_MOUT_CLK2X_PHY_B, "mout_clk2x_phy_b", mout_clk2x_phy_b_p,
1104 MUX_SEL_MIF1, 20, 1),
1105 MUX(CLK_MOUT_CLK2X_PHY_A, "mout_clk2x_phy_a", mout_clk2x_phy_a_p,
1106 MUX_SEL_MIF1, 16, 1),
1107 MUX(CLK_MOUT_CLKM_PHY_C, "mout_clkm_phy_c", mout_clk2x_phy_c_p,
1108 MUX_SEL_MIF1, 12, 1),
1109 MUX(CLK_MOUT_CLKM_PHY_B, "mout_clkm_phy_b", mout_clkm_phy_b_p,
1110 MUX_SEL_MIF1, 8, 1),
1111 MUX(CLK_MOUT_CLKM_PHY_A, "mout_clkm_phy_a", mout_clk2x_phy_a_p,
1112 MUX_SEL_MIF1, 4, 1),
1115 MUX(CLK_MOUT_ACLK_MIFNM_200, "mout_aclk_mifnm_200",
1116 mout_aclk_mifnm_200_p, MUX_SEL_MIF2, 8, 1),
1117 MUX(CLK_MOUT_ACLK_MIFNM_400, "mout_aclk_mifnm_400",
1118 mout_aclk_mifnm_400_p, MUX_SEL_MIF2, 0, 1),
1121 MUX(CLK_MOUT_ACLK_DISP_333_B, "mout_aclk_disp_333_b",
1122 mout_aclk_disp_333_b_p, MUX_SEL_MIF3, 4, 1),
1123 MUX(CLK_MOUT_ACLK_DISP_333_A, "mout_aclk_disp_333_a",
1124 mout_aclk_disp_333_a_p, MUX_SEL_MIF3, 0, 1),
1127 MUX(CLK_MOUT_SCLK_DECON_VCLK_C, "mout_sclk_decon_vclk_c",
1128 mout_sclk_decon_vclk_c_p, MUX_SEL_MIF4, 24, 1),
1129 MUX(CLK_MOUT_SCLK_DECON_VCLK_B, "mout_sclk_decon_vclk_b",
1130 mout_sclk_decon_vclk_b_p, MUX_SEL_MIF4, 20, 1),
1131 MUX(CLK_MOUT_SCLK_DECON_VCLK_A, "mout_sclk_decon_vclk_a",
1132 mout_sclk_decon_p, MUX_SEL_MIF4, 16, 1),
1133 MUX(CLK_MOUT_SCLK_DECON_ECLK_C, "mout_sclk_decon_eclk_c",
1134 mout_sclk_decon_eclk_c_p, MUX_SEL_MIF4, 8, 1),
1135 MUX(CLK_MOUT_SCLK_DECON_ECLK_B, "mout_sclk_decon_eclk_b",
1136 mout_sclk_decon_eclk_b_p, MUX_SEL_MIF4, 4, 1),
1137 MUX(CLK_MOUT_SCLK_DECON_ECLK_A, "mout_sclk_decon_eclk_a",
1138 mout_sclk_decon_p, MUX_SEL_MIF4, 0, 1),
1141 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_C, "mout_sclk_decon_tv_eclk_c",
1142 mout_sclk_decon_tv_eclk_c_p, MUX_SEL_MIF5, 24, 1),
1143 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_B, "mout_sclk_decon_tv_eclk_b",
1144 mout_sclk_decon_tv_eclk_b_p, MUX_SEL_MIF5, 20, 1),
1145 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_A, "mout_sclk_decon_tv_eclk_a",
1146 mout_sclk_decon_p, MUX_SEL_MIF5, 16, 1),
1147 MUX(CLK_MOUT_SCLK_DSD_C, "mout_sclk_dsd_c", mout_sclk_dsd_c_p,
1148 MUX_SEL_MIF5, 8, 1),
1149 MUX(CLK_MOUT_SCLK_DSD_B, "mout_sclk_dsd_b", mout_sclk_dsd_b_p,
1150 MUX_SEL_MIF5, 4, 1),
1151 MUX(CLK_MOUT_SCLK_DSD_A, "mout_sclk_dsd_a", mout_sclk_dsd_a_p,
1152 MUX_SEL_MIF5, 0, 1),
1155 MUX(CLK_MOUT_SCLK_DSIM0_C, "mout_sclk_dsim0_c", mout_sclk_dsim0_c_p,
1156 MUX_SEL_MIF6, 8, 1),
1157 MUX(CLK_MOUT_SCLK_DSIM0_B, "mout_sclk_dsim0_b", mout_sclk_dsim0_b_p,
1158 MUX_SEL_MIF6, 4, 1),
1159 MUX(CLK_MOUT_SCLK_DSIM0_A, "mout_sclk_dsim0_a", mout_sclk_decon_p,
1160 MUX_SEL_MIF6, 0, 1),
1163 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C, "mout_sclk_decon_tv_vclk_c",
1164 mout_sclk_decon_tv_vclk_c_p, MUX_SEL_MIF7, 24, 1),
1165 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B, "mout_sclk_decon_tv_vclk_b",
1166 mout_sclk_decon_tv_vclk_b_p, MUX_SEL_MIF7, 20, 1),
1167 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A, "mout_sclk_decon_tv_vclk_a",
1168 mout_sclk_decon_p, MUX_SEL_MIF7, 16, 1),
1169 MUX(CLK_MOUT_SCLK_DSIM1_C, "mout_sclk_dsim1_c", mout_sclk_dsim1_c_p,
1170 MUX_SEL_MIF7, 8, 1),
1171 MUX(CLK_MOUT_SCLK_DSIM1_B, "mout_sclk_dsim1_b", mout_sclk_dsim1_b_p,
1172 MUX_SEL_MIF7, 4, 1),
1173 MUX(CLK_MOUT_SCLK_DSIM1_A, "mout_sclk_dsim1_a", mout_sclk_decon_p,
1174 MUX_SEL_MIF7, 0, 1),
1177 static const struct samsung_div_clock mif_div_clks[] __initconst = {
1179 DIV(CLK_DIV_SCLK_HPM_MIF, "div_sclk_hpm_mif", "div_clk2x_phy",
1181 DIV(CLK_DIV_ACLK_DREX1, "div_aclk_drex1", "div_clk2x_phy", DIV_MIF1,
1183 DIV(CLK_DIV_ACLK_DREX0, "div_aclk_drex0", "div_clk2x_phy", DIV_MIF1,
1185 DIV(CLK_DIV_CLK2XPHY, "div_clk2x_phy", "mout_clk2x_phy_c", DIV_MIF1,
1189 DIV(CLK_DIV_ACLK_MIF_266, "div_aclk_mif_266", "mout_bus_pll_div2",
1191 DIV(CLK_DIV_ACLK_MIFND_133, "div_aclk_mifnd_133", "div_mif_pre",
1193 DIV(CLK_DIV_ACLK_MIF_133, "div_aclk_mif_133", "div_mif_pre",
1195 DIV(CLK_DIV_ACLK_MIFNM_200, "div_aclk_mifnm_200",
1196 "mout_aclk_mifnm_200", DIV_MIF2, 8, 3),
1197 DIV(CLK_DIV_ACLK_MIF_200, "div_aclk_mif_200", "div_aclk_mif_400",
1199 DIV(CLK_DIV_ACLK_MIF_400, "div_aclk_mif_400", "mout_aclk_mifnm_400",
1203 DIV(CLK_DIV_ACLK_BUS2_400, "div_aclk_bus2_400", "div_mif_pre",
1205 DIV(CLK_DIV_ACLK_DISP_333, "div_aclk_disp_333", "mout_aclk_disp_333_b",
1207 DIV(CLK_DIV_ACLK_CPIF_200, "div_aclk_cpif_200", "mout_aclk_mifnm_200",
1211 DIV(CLK_DIV_SCLK_DSIM1, "div_sclk_dsim1", "mout_sclk_dsim1_c",
1213 DIV(CLK_DIV_SCLK_DECON_TV_VCLK, "div_sclk_decon_tv_vclk",
1214 "mout_sclk_decon_tv_vclk_c", DIV_MIF4, 20, 4),
1215 DIV(CLK_DIV_SCLK_DSIM0, "div_sclk_dsim0", "mout_sclk_dsim0_c",
1217 DIV(CLK_DIV_SCLK_DSD, "div_sclk_dsd", "mout_sclk_dsd_c",
1219 DIV(CLK_DIV_SCLK_DECON_TV_ECLK, "div_sclk_decon_tv_eclk",
1220 "mout_sclk_decon_tv_eclk_c", DIV_MIF4, 8, 4),
1221 DIV(CLK_DIV_SCLK_DECON_VCLK, "div_sclk_decon_vclk",
1222 "mout_sclk_decon_vclk_c", DIV_MIF4, 4, 4),
1223 DIV(CLK_DIV_SCLK_DECON_ECLK, "div_sclk_decon_eclk",
1224 "mout_sclk_decon_eclk_c", DIV_MIF4, 0, 4),
1227 DIV(CLK_DIV_MIF_PRE, "div_mif_pre", "mout_bus_pll_div2", DIV_MIF5,
1231 static const struct samsung_gate_clock mif_gate_clks[] __initconst = {
1232 /* ENABLE_ACLK_MIF0 */
1233 GATE(CLK_CLK2X_PHY1, "clk2k_phy1", "div_clk2x_phy", ENABLE_ACLK_MIF0,
1234 19, CLK_IGNORE_UNUSED, 0),
1235 GATE(CLK_CLK2X_PHY0, "clk2x_phy0", "div_clk2x_phy", ENABLE_ACLK_MIF0,
1236 18, CLK_IGNORE_UNUSED, 0),
1237 GATE(CLK_CLKM_PHY1, "clkm_phy1", "mout_clkm_phy_c", ENABLE_ACLK_MIF0,
1238 17, CLK_IGNORE_UNUSED, 0),
1239 GATE(CLK_CLKM_PHY0, "clkm_phy0", "mout_clkm_phy_c", ENABLE_ACLK_MIF0,
1240 16, CLK_IGNORE_UNUSED, 0),
1241 GATE(CLK_RCLK_DREX1, "rclk_drex1", "oscclk", ENABLE_ACLK_MIF0,
1242 15, CLK_IGNORE_UNUSED, 0),
1243 GATE(CLK_RCLK_DREX0, "rclk_drex0", "oscclk", ENABLE_ACLK_MIF0,
1244 14, CLK_IGNORE_UNUSED, 0),
1245 GATE(CLK_ACLK_DREX1_TZ, "aclk_drex1_tz", "div_aclk_drex1",
1246 ENABLE_ACLK_MIF0, 13, CLK_IGNORE_UNUSED, 0),
1247 GATE(CLK_ACLK_DREX0_TZ, "aclk_drex0_tz", "div_aclk_drex0",
1248 ENABLE_ACLK_MIF0, 12, CLK_IGNORE_UNUSED, 0),
1249 GATE(CLK_ACLK_DREX1_PEREV, "aclk_drex1_perev", "div_aclk_drex1",
1250 ENABLE_ACLK_MIF0, 11, CLK_IGNORE_UNUSED, 0),
1251 GATE(CLK_ACLK_DREX0_PEREV, "aclk_drex0_perev", "div_aclk_drex0",
1252 ENABLE_ACLK_MIF0, 10, CLK_IGNORE_UNUSED, 0),
1253 GATE(CLK_ACLK_DREX1_MEMIF, "aclk_drex1_memif", "div_aclk_drex1",
1254 ENABLE_ACLK_MIF0, 9, CLK_IGNORE_UNUSED, 0),
1255 GATE(CLK_ACLK_DREX0_MEMIF, "aclk_drex0_memif", "div_aclk_drex0",
1256 ENABLE_ACLK_MIF0, 8, CLK_IGNORE_UNUSED, 0),
1257 GATE(CLK_ACLK_DREX1_SCH, "aclk_drex1_sch", "div_aclk_drex1",
1258 ENABLE_ACLK_MIF0, 7, CLK_IGNORE_UNUSED, 0),
1259 GATE(CLK_ACLK_DREX0_SCH, "aclk_drex0_sch", "div_aclk_drex0",
1260 ENABLE_ACLK_MIF0, 6, CLK_IGNORE_UNUSED, 0),
1261 GATE(CLK_ACLK_DREX1_BUSIF, "aclk_drex1_busif", "div_aclk_drex1",
1262 ENABLE_ACLK_MIF0, 5, CLK_IGNORE_UNUSED, 0),
1263 GATE(CLK_ACLK_DREX0_BUSIF, "aclk_drex0_busif", "div_aclk_drex0",
1264 ENABLE_ACLK_MIF0, 4, CLK_IGNORE_UNUSED, 0),
1265 GATE(CLK_ACLK_DREX1_BUSIF_RD, "aclk_drex1_busif_rd", "div_aclk_drex1",
1266 ENABLE_ACLK_MIF0, 3, CLK_IGNORE_UNUSED, 0),
1267 GATE(CLK_ACLK_DREX0_BUSIF_RD, "aclk_drex0_busif_rd", "div_aclk_drex0",
1268 ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0),
1269 GATE(CLK_ACLK_DREX1, "aclk_drex1", "div_aclk_drex1",
1270 ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0),
1271 GATE(CLK_ACLK_DREX0, "aclk_drex0", "div_aclk_drex0",
1272 ENABLE_ACLK_MIF0, 1, CLK_IGNORE_UNUSED, 0),
1274 /* ENABLE_ACLK_MIF1 */
1275 GATE(CLK_ACLK_ASYNCAXIS_MIF_IMEM, "aclk_asyncaxis_mif_imem",
1276 "div_aclk_mif_200", ENABLE_ACLK_MIF1, 28,
1277 CLK_IGNORE_UNUSED, 0),
1278 GATE(CLK_ACLK_ASYNCAXIS_NOC_P_CCI, "aclk_asyncaxis_noc_p_cci",
1279 "div_aclk_mif_200", ENABLE_ACLK_MIF1,
1280 27, CLK_IGNORE_UNUSED, 0),
1281 GATE(CLK_ACLK_ASYNCAXIM_NOC_P_CCI, "aclk_asyncaxim_noc_p_cci",
1282 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1283 26, CLK_IGNORE_UNUSED, 0),
1284 GATE(CLK_ACLK_ASYNCAXIS_CP1, "aclk_asyncaxis_cp1",
1285 "div_aclk_mifnm_200", ENABLE_ACLK_MIF1,
1286 25, CLK_IGNORE_UNUSED, 0),
1287 GATE(CLK_ACLK_ASYNCAXIM_CP1, "aclk_asyncaxim_cp1",
1288 "div_aclk_drex1", ENABLE_ACLK_MIF1,
1289 24, CLK_IGNORE_UNUSED, 0),
1290 GATE(CLK_ACLK_ASYNCAXIS_CP0, "aclk_asyncaxis_cp0",
1291 "div_aclk_mifnm_200", ENABLE_ACLK_MIF1,
1292 23, CLK_IGNORE_UNUSED, 0),
1293 GATE(CLK_ACLK_ASYNCAXIM_CP0, "aclk_asyncaxim_cp0",
1294 "div_aclk_drex0", ENABLE_ACLK_MIF1,
1295 22, CLK_IGNORE_UNUSED, 0),
1296 GATE(CLK_ACLK_ASYNCAXIS_DREX1_3, "aclk_asyncaxis_drex1_3",
1297 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1298 21, CLK_IGNORE_UNUSED, 0),
1299 GATE(CLK_ACLK_ASYNCAXIM_DREX1_3, "aclk_asyncaxim_drex1_3",
1300 "div_aclk_drex1", ENABLE_ACLK_MIF1,
1301 20, CLK_IGNORE_UNUSED, 0),
1302 GATE(CLK_ACLK_ASYNCAXIS_DREX1_1, "aclk_asyncaxis_drex1_1",
1303 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1304 19, CLK_IGNORE_UNUSED, 0),
1305 GATE(CLK_ACLK_ASYNCAXIM_DREX1_1, "aclk_asyncaxim_drex1_1",
1306 "div_aclk_drex1", ENABLE_ACLK_MIF1,
1307 18, CLK_IGNORE_UNUSED, 0),
1308 GATE(CLK_ACLK_ASYNCAXIS_DREX1_0, "aclk_asyncaxis_drex1_0",
1309 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1310 17, CLK_IGNORE_UNUSED, 0),
1311 GATE(CLK_ACLK_ASYNCAXIM_DREX1_0, "aclk_asyncaxim_drex1_0",
1312 "div_aclk_drex1", ENABLE_ACLK_MIF1,
1313 16, CLK_IGNORE_UNUSED, 0),
1314 GATE(CLK_ACLK_ASYNCAXIS_DREX0_3, "aclk_asyncaxis_drex0_3",
1315 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1316 15, CLK_IGNORE_UNUSED, 0),
1317 GATE(CLK_ACLK_ASYNCAXIM_DREX0_3, "aclk_asyncaxim_drex0_3",
1318 "div_aclk_drex0", ENABLE_ACLK_MIF1,
1319 14, CLK_IGNORE_UNUSED, 0),
1320 GATE(CLK_ACLK_ASYNCAXIS_DREX0_1, "aclk_asyncaxis_drex0_1",
1321 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1322 13, CLK_IGNORE_UNUSED, 0),
1323 GATE(CLK_ACLK_ASYNCAXIM_DREX0_1, "aclk_asyncaxim_drex0_1",
1324 "div_aclk_drex0", ENABLE_ACLK_MIF1,
1325 12, CLK_IGNORE_UNUSED, 0),
1326 GATE(CLK_ACLK_ASYNCAXIS_DREX0_0, "aclk_asyncaxis_drex0_0",
1327 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1328 11, CLK_IGNORE_UNUSED, 0),
1329 GATE(CLK_ACLK_ASYNCAXIM_DREX0_0, "aclk_asyncaxim_drex0_0",
1330 "div_aclk_drex0", ENABLE_ACLK_MIF1,
1331 10, CLK_IGNORE_UNUSED, 0),
1332 GATE(CLK_ACLK_AHB2APB_MIF2P, "aclk_ahb2apb_mif2p", "div_aclk_mif_133",
1333 ENABLE_ACLK_MIF1, 9, CLK_IGNORE_UNUSED, 0),
1334 GATE(CLK_ACLK_AHB2APB_MIF1P, "aclk_ahb2apb_mif1p", "div_aclk_mif_133",
1335 ENABLE_ACLK_MIF1, 8, CLK_IGNORE_UNUSED, 0),
1336 GATE(CLK_ACLK_AHB2APB_MIF0P, "aclk_ahb2apb_mif0p", "div_aclk_mif_133",
1337 ENABLE_ACLK_MIF1, 7, CLK_IGNORE_UNUSED, 0),
1338 GATE(CLK_ACLK_IXIU_CCI, "aclk_ixiu_cci", "div_aclk_mif_400",
1339 ENABLE_ACLK_MIF1, 6, CLK_IGNORE_UNUSED, 0),
1340 GATE(CLK_ACLK_XIU_MIFSFRX, "aclk_xiu_mifsfrx", "div_aclk_mif_200",
1341 ENABLE_ACLK_MIF1, 5, CLK_IGNORE_UNUSED, 0),
1342 GATE(CLK_ACLK_MIFNP_133, "aclk_mifnp_133", "div_aclk_mif_133",
1343 ENABLE_ACLK_MIF1, 4, CLK_IGNORE_UNUSED, 0),
1344 GATE(CLK_ACLK_MIFNM_200, "aclk_mifnm_200", "div_aclk_mifnm_200",
1345 ENABLE_ACLK_MIF1, 3, CLK_IGNORE_UNUSED, 0),
1346 GATE(CLK_ACLK_MIFND_133, "aclk_mifnd_133", "div_aclk_mifnd_133",
1347 ENABLE_ACLK_MIF1, 2, CLK_IGNORE_UNUSED, 0),
1348 GATE(CLK_ACLK_MIFND_400, "aclk_mifnd_400", "div_aclk_mif_400",
1349 ENABLE_ACLK_MIF1, 1, CLK_IGNORE_UNUSED, 0),
1350 GATE(CLK_ACLK_CCI, "aclk_cci", "div_aclk_mif_400", ENABLE_ACLK_MIF1,
1351 0, CLK_IGNORE_UNUSED, 0),
1353 /* ENABLE_ACLK_MIF2 */
1354 GATE(CLK_ACLK_MIFND_266, "aclk_mifnd_266", "div_aclk_mif_266",
1355 ENABLE_ACLK_MIF2, 20, CLK_IGNORE_UNUSED, 0),
1356 GATE(CLK_ACLK_PPMU_DREX1S3, "aclk_ppmu_drex1s3", "div_aclk_drex1",
1357 ENABLE_ACLK_MIF2, 17, CLK_IGNORE_UNUSED, 0),
1358 GATE(CLK_ACLK_PPMU_DREX1S1, "aclk_ppmu_drex1s1", "div_aclk_drex1",
1359 ENABLE_ACLK_MIF2, 16, CLK_IGNORE_UNUSED, 0),
1360 GATE(CLK_ACLK_PPMU_DREX1S0, "aclk_ppmu_drex1s0", "div_aclk_drex1",
1361 ENABLE_ACLK_MIF2, 15, CLK_IGNORE_UNUSED, 0),
1362 GATE(CLK_ACLK_PPMU_DREX0S3, "aclk_ppmu_drex0s3", "div_aclk_drex0",
1363 ENABLE_ACLK_MIF2, 14, CLK_IGNORE_UNUSED, 0),
1364 GATE(CLK_ACLK_PPMU_DREX0S1, "aclk_ppmu_drex0s1", "div_aclk_drex0",
1365 ENABLE_ACLK_MIF2, 13, CLK_IGNORE_UNUSED, 0),
1366 GATE(CLK_ACLK_PPMU_DREX0S0, "aclk_ppmu_drex0s0", "div_aclk_drex0",
1367 ENABLE_ACLK_MIF2, 12, CLK_IGNORE_UNUSED, 0),
1368 GATE(CLK_ACLK_AXIDS_CCI_MIFSFRX, "aclk_axids_cci_mifsfrx",
1369 "div_aclk_mif_200", ENABLE_ACLK_MIF2, 7,
1370 CLK_IGNORE_UNUSED, 0),
1371 GATE(CLK_ACLK_AXISYNCDNS_CCI, "aclk_axisyncdns_cci",
1372 "div_aclk_mif_400", ENABLE_ACLK_MIF2,
1373 5, CLK_IGNORE_UNUSED, 0),
1374 GATE(CLK_ACLK_AXISYNCDN_CCI, "aclk_axisyncdn_cci", "div_aclk_mif_400",
1375 ENABLE_ACLK_MIF2, 4, CLK_IGNORE_UNUSED, 0),
1376 GATE(CLK_ACLK_AXISYNCDN_NOC_D, "aclk_axisyncdn_noc_d",
1377 "div_aclk_mif_200", ENABLE_ACLK_MIF2,
1378 3, CLK_IGNORE_UNUSED, 0),
1379 GATE(CLK_ACLK_ASYNCAPBS_MIF_CSSYS, "aclk_asyncapbs_mif_cssys",
1380 "div_aclk_mifnd_133", ENABLE_ACLK_MIF2, 0, 0, 0),
1382 /* ENABLE_ACLK_MIF3 */
1383 GATE(CLK_ACLK_BUS2_400, "aclk_bus2_400", "div_aclk_bus2_400",
1384 ENABLE_ACLK_MIF3, 4,
1385 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1386 GATE(CLK_ACLK_DISP_333, "aclk_disp_333", "div_aclk_disp_333",
1387 ENABLE_ACLK_MIF3, 1,
1388 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1389 GATE(CLK_ACLK_CPIF_200, "aclk_cpif_200", "div_aclk_cpif_200",
1390 ENABLE_ACLK_MIF3, 0,
1391 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1393 /* ENABLE_PCLK_MIF */
1394 GATE(CLK_PCLK_PPMU_DREX1S3, "pclk_ppmu_drex1s3", "div_aclk_drex1",
1395 ENABLE_PCLK_MIF, 29, CLK_IGNORE_UNUSED, 0),
1396 GATE(CLK_PCLK_PPMU_DREX1S1, "pclk_ppmu_drex1s1", "div_aclk_drex1",
1397 ENABLE_PCLK_MIF, 28, CLK_IGNORE_UNUSED, 0),
1398 GATE(CLK_PCLK_PPMU_DREX1S0, "pclk_ppmu_drex1s0", "div_aclk_drex1",
1399 ENABLE_PCLK_MIF, 27, CLK_IGNORE_UNUSED, 0),
1400 GATE(CLK_PCLK_PPMU_DREX0S3, "pclk_ppmu_drex0s3", "div_aclk_drex0",
1401 ENABLE_PCLK_MIF, 26, CLK_IGNORE_UNUSED, 0),
1402 GATE(CLK_PCLK_PPMU_DREX0S1, "pclk_ppmu_drex0s1", "div_aclk_drex0",
1403 ENABLE_PCLK_MIF, 25, CLK_IGNORE_UNUSED, 0),
1404 GATE(CLK_PCLK_PPMU_DREX0S0, "pclk_ppmu_drex0s0", "div_aclk_drex0",
1405 ENABLE_PCLK_MIF, 24, CLK_IGNORE_UNUSED, 0),
1406 GATE(CLK_PCLK_ASYNCAXI_NOC_P_CCI, "pclk_asyncaxi_noc_p_cci",
1407 "div_aclk_mif_133", ENABLE_PCLK_MIF, 21,
1408 CLK_IGNORE_UNUSED, 0),
1409 GATE(CLK_PCLK_ASYNCAXI_CP1, "pclk_asyncaxi_cp1", "div_aclk_mif_133",
1410 ENABLE_PCLK_MIF, 19, 0, 0),
1411 GATE(CLK_PCLK_ASYNCAXI_CP0, "pclk_asyncaxi_cp0", "div_aclk_mif_133",
1412 ENABLE_PCLK_MIF, 18, 0, 0),
1413 GATE(CLK_PCLK_ASYNCAXI_DREX1_3, "pclk_asyncaxi_drex1_3",
1414 "div_aclk_mif_133", ENABLE_PCLK_MIF, 17, 0, 0),
1415 GATE(CLK_PCLK_ASYNCAXI_DREX1_1, "pclk_asyncaxi_drex1_1",
1416 "div_aclk_mif_133", ENABLE_PCLK_MIF, 16, 0, 0),
1417 GATE(CLK_PCLK_ASYNCAXI_DREX1_0, "pclk_asyncaxi_drex1_0",
1418 "div_aclk_mif_133", ENABLE_PCLK_MIF, 15, 0, 0),
1419 GATE(CLK_PCLK_ASYNCAXI_DREX0_3, "pclk_asyncaxi_drex0_3",
1420 "div_aclk_mif_133", ENABLE_PCLK_MIF, 14, 0, 0),
1421 GATE(CLK_PCLK_ASYNCAXI_DREX0_1, "pclk_asyncaxi_drex0_1",
1422 "div_aclk_mif_133", ENABLE_PCLK_MIF, 13, 0, 0),
1423 GATE(CLK_PCLK_ASYNCAXI_DREX0_0, "pclk_asyncaxi_drex0_0",
1424 "div_aclk_mif_133", ENABLE_PCLK_MIF, 12, 0, 0),
1425 GATE(CLK_PCLK_MIFSRVND_133, "pclk_mifsrvnd_133", "div_aclk_mif_133",
1426 ENABLE_PCLK_MIF, 11, 0, 0),
1427 GATE(CLK_PCLK_PMU_MIF, "pclk_pmu_mif", "div_aclk_mif_133",
1428 ENABLE_PCLK_MIF, 10, CLK_IGNORE_UNUSED, 0),
1429 GATE(CLK_PCLK_SYSREG_MIF, "pclk_sysreg_mif", "div_aclk_mif_133",
1430 ENABLE_PCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
1431 GATE(CLK_PCLK_GPIO_ALIVE, "pclk_gpio_alive", "div_aclk_mif_133",
1432 ENABLE_PCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
1433 GATE(CLK_PCLK_ABB, "pclk_abb", "div_aclk_mif_133",
1434 ENABLE_PCLK_MIF, 7, 0, 0),
1435 GATE(CLK_PCLK_PMU_APBIF, "pclk_pmu_apbif", "div_aclk_mif_133",
1436 ENABLE_PCLK_MIF, 6, CLK_IGNORE_UNUSED, 0),
1437 GATE(CLK_PCLK_DDR_PHY1, "pclk_ddr_phy1", "div_aclk_mif_133",
1438 ENABLE_PCLK_MIF, 5, 0, 0),
1439 GATE(CLK_PCLK_DREX1, "pclk_drex1", "div_aclk_mif_133",
1440 ENABLE_PCLK_MIF, 3, CLK_IGNORE_UNUSED, 0),
1441 GATE(CLK_PCLK_DDR_PHY0, "pclk_ddr_phy0", "div_aclk_mif_133",
1442 ENABLE_PCLK_MIF, 2, 0, 0),
1443 GATE(CLK_PCLK_DREX0, "pclk_drex0", "div_aclk_mif_133",
1444 ENABLE_PCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
1446 /* ENABLE_PCLK_MIF_SECURE_DREX0_TZ */
1447 GATE(CLK_PCLK_DREX0_TZ, "pclk_drex0_tz", "div_aclk_mif_133",
1448 ENABLE_PCLK_MIF_SECURE_DREX0_TZ, 0,
1449 CLK_IGNORE_UNUSED, 0),
1451 /* ENABLE_PCLK_MIF_SECURE_DREX1_TZ */
1452 GATE(CLK_PCLK_DREX1_TZ, "pclk_drex1_tz", "div_aclk_mif_133",
1453 ENABLE_PCLK_MIF_SECURE_DREX1_TZ, 0,
1454 CLK_IGNORE_UNUSED, 0),
1456 /* ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT */
1457 GATE(CLK_PCLK_MONOTONIC_CNT, "pclk_monotonic_cnt", "div_aclk_mif_133",
1458 ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT, 0, 0, 0),
1460 /* ENABLE_PCLK_MIF_SECURE_RTC */
1461 GATE(CLK_PCLK_RTC, "pclk_rtc", "div_aclk_mif_133",
1462 ENABLE_PCLK_MIF_SECURE_RTC, 0, 0, 0),
1464 /* ENABLE_SCLK_MIF */
1465 GATE(CLK_SCLK_DSIM1_DISP, "sclk_dsim1_disp", "div_sclk_dsim1",
1466 ENABLE_SCLK_MIF, 15, CLK_IGNORE_UNUSED, 0),
1467 GATE(CLK_SCLK_DECON_TV_VCLK_DISP, "sclk_decon_tv_vclk_disp",
1468 "div_sclk_decon_tv_vclk", ENABLE_SCLK_MIF,
1469 14, CLK_IGNORE_UNUSED, 0),
1470 GATE(CLK_SCLK_DSIM0_DISP, "sclk_dsim0_disp", "div_sclk_dsim0",
1471 ENABLE_SCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
1472 GATE(CLK_SCLK_DSD_DISP, "sclk_dsd_disp", "div_sclk_dsd",
1473 ENABLE_SCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
1474 GATE(CLK_SCLK_DECON_TV_ECLK_DISP, "sclk_decon_tv_eclk_disp",
1475 "div_sclk_decon_tv_eclk", ENABLE_SCLK_MIF,
1476 7, CLK_IGNORE_UNUSED, 0),
1477 GATE(CLK_SCLK_DECON_VCLK_DISP, "sclk_decon_vclk_disp",
1478 "div_sclk_decon_vclk", ENABLE_SCLK_MIF,
1479 6, CLK_IGNORE_UNUSED, 0),
1480 GATE(CLK_SCLK_DECON_ECLK_DISP, "sclk_decon_eclk_disp",
1481 "div_sclk_decon_eclk", ENABLE_SCLK_MIF,
1482 5, CLK_IGNORE_UNUSED, 0),
1483 GATE(CLK_SCLK_HPM_MIF, "sclk_hpm_mif", "div_sclk_hpm_mif",
1485 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1486 GATE(CLK_SCLK_MFC_PLL, "sclk_mfc_pll", "mout_mfc_pll_div2",
1487 ENABLE_SCLK_MIF, 3, CLK_IGNORE_UNUSED, 0),
1488 GATE(CLK_SCLK_BUS_PLL, "sclk_bus_pll", "mout_bus_pll_div2",
1489 ENABLE_SCLK_MIF, 2, CLK_IGNORE_UNUSED, 0),
1490 GATE(CLK_SCLK_BUS_PLL_APOLLO, "sclk_bus_pll_apollo", "sclk_bus_pll",
1491 ENABLE_SCLK_MIF, 1, CLK_IGNORE_UNUSED, 0),
1492 GATE(CLK_SCLK_BUS_PLL_ATLAS, "sclk_bus_pll_atlas", "sclk_bus_pll",
1493 ENABLE_SCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
1496 static const struct samsung_cmu_info mif_cmu_info __initconst = {
1497 .pll_clks = mif_pll_clks,
1498 .nr_pll_clks = ARRAY_SIZE(mif_pll_clks),
1499 .mux_clks = mif_mux_clks,
1500 .nr_mux_clks = ARRAY_SIZE(mif_mux_clks),
1501 .div_clks = mif_div_clks,
1502 .nr_div_clks = ARRAY_SIZE(mif_div_clks),
1503 .gate_clks = mif_gate_clks,
1504 .nr_gate_clks = ARRAY_SIZE(mif_gate_clks),
1505 .fixed_factor_clks = mif_fixed_factor_clks,
1506 .nr_fixed_factor_clks = ARRAY_SIZE(mif_fixed_factor_clks),
1507 .nr_clk_ids = MIF_NR_CLK,
1508 .clk_regs = mif_clk_regs,
1509 .nr_clk_regs = ARRAY_SIZE(mif_clk_regs),
1512 static void __init exynos5433_cmu_mif_init(struct device_node *np)
1514 samsung_cmu_register_one(np, &mif_cmu_info);
1516 CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif",
1517 exynos5433_cmu_mif_init);
1520 * Register offset definitions for CMU_PERIC
1522 #define DIV_PERIC 0x0600
1523 #define DIV_STAT_PERIC 0x0700
1524 #define ENABLE_ACLK_PERIC 0x0800
1525 #define ENABLE_PCLK_PERIC0 0x0900
1526 #define ENABLE_PCLK_PERIC1 0x0904
1527 #define ENABLE_SCLK_PERIC 0x0A00
1528 #define ENABLE_IP_PERIC0 0x0B00
1529 #define ENABLE_IP_PERIC1 0x0B04
1530 #define ENABLE_IP_PERIC2 0x0B08
1532 static const unsigned long peric_clk_regs[] __initconst = {
1543 static const struct samsung_div_clock peric_div_clks[] __initconst = {
1545 DIV(CLK_DIV_SCLK_SCI, "div_sclk_sci", "oscclk", DIV_PERIC, 4, 4),
1546 DIV(CLK_DIV_SCLK_SC_IN, "div_sclk_sc_in", "oscclk", DIV_PERIC, 0, 4),
1549 static const struct samsung_gate_clock peric_gate_clks[] __initconst = {
1550 /* ENABLE_ACLK_PERIC */
1551 GATE(CLK_ACLK_AHB2APB_PERIC2P, "aclk_ahb2apb_peric2p", "aclk_peric_66",
1552 ENABLE_ACLK_PERIC, 3, CLK_IGNORE_UNUSED, 0),
1553 GATE(CLK_ACLK_AHB2APB_PERIC1P, "aclk_ahb2apb_peric1p", "aclk_peric_66",
1554 ENABLE_ACLK_PERIC, 2, CLK_IGNORE_UNUSED, 0),
1555 GATE(CLK_ACLK_AHB2APB_PERIC0P, "aclk_ahb2apb_peric0p", "aclk_peric_66",
1556 ENABLE_ACLK_PERIC, 1, CLK_IGNORE_UNUSED, 0),
1557 GATE(CLK_ACLK_PERICNP_66, "aclk_pericnp_66", "aclk_peric_66",
1558 ENABLE_ACLK_PERIC, 0, CLK_IGNORE_UNUSED, 0),
1560 /* ENABLE_PCLK_PERIC0 */
1561 GATE(CLK_PCLK_SCI, "pclk_sci", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1562 31, CLK_SET_RATE_PARENT, 0),
1563 GATE(CLK_PCLK_GPIO_FINGER, "pclk_gpio_finger", "aclk_peric_66",
1564 ENABLE_PCLK_PERIC0, 30, CLK_IGNORE_UNUSED, 0),
1565 GATE(CLK_PCLK_GPIO_ESE, "pclk_gpio_ese", "aclk_peric_66",
1566 ENABLE_PCLK_PERIC0, 29, CLK_IGNORE_UNUSED, 0),
1567 GATE(CLK_PCLK_PWM, "pclk_pwm", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1568 28, CLK_SET_RATE_PARENT, 0),
1569 GATE(CLK_PCLK_SPDIF, "pclk_spdif", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1570 26, CLK_SET_RATE_PARENT, 0),
1571 GATE(CLK_PCLK_PCM1, "pclk_pcm1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1572 25, CLK_SET_RATE_PARENT, 0),
1573 GATE(CLK_PCLK_I2S1, "pclk_i2s", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1574 24, CLK_SET_RATE_PARENT, 0),
1575 GATE(CLK_PCLK_SPI2, "pclk_spi2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1576 23, CLK_SET_RATE_PARENT, 0),
1577 GATE(CLK_PCLK_SPI1, "pclk_spi1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1578 22, CLK_SET_RATE_PARENT, 0),
1579 GATE(CLK_PCLK_SPI0, "pclk_spi0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1580 21, CLK_SET_RATE_PARENT, 0),
1581 GATE(CLK_PCLK_ADCIF, "pclk_adcif", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1582 20, CLK_SET_RATE_PARENT, 0),
1583 GATE(CLK_PCLK_GPIO_TOUCH, "pclk_gpio_touch", "aclk_peric_66",
1584 ENABLE_PCLK_PERIC0, 19, CLK_IGNORE_UNUSED, 0),
1585 GATE(CLK_PCLK_GPIO_NFC, "pclk_gpio_nfc", "aclk_peric_66",
1586 ENABLE_PCLK_PERIC0, 18, CLK_IGNORE_UNUSED, 0),
1587 GATE(CLK_PCLK_GPIO_PERIC, "pclk_gpio_peric", "aclk_peric_66",
1588 ENABLE_PCLK_PERIC0, 17, CLK_IGNORE_UNUSED, 0),
1589 GATE(CLK_PCLK_PMU_PERIC, "pclk_pmu_peric", "aclk_peric_66",
1590 ENABLE_PCLK_PERIC0, 16, CLK_SET_RATE_PARENT, 0),
1591 GATE(CLK_PCLK_SYSREG_PERIC, "pclk_sysreg_peric", "aclk_peric_66",
1592 ENABLE_PCLK_PERIC0, 15,
1593 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1594 GATE(CLK_PCLK_UART2, "pclk_uart2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1595 14, CLK_SET_RATE_PARENT, 0),
1596 GATE(CLK_PCLK_UART1, "pclk_uart1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1597 13, CLK_SET_RATE_PARENT, 0),
1598 GATE(CLK_PCLK_UART0, "pclk_uart0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1599 12, CLK_SET_RATE_PARENT, 0),
1600 GATE(CLK_PCLK_HSI2C3, "pclk_hsi2c3", "aclk_peric_66",
1601 ENABLE_PCLK_PERIC0, 11, CLK_SET_RATE_PARENT, 0),
1602 GATE(CLK_PCLK_HSI2C2, "pclk_hsi2c2", "aclk_peric_66",
1603 ENABLE_PCLK_PERIC0, 10, CLK_SET_RATE_PARENT, 0),
1604 GATE(CLK_PCLK_HSI2C1, "pclk_hsi2c1", "aclk_peric_66",
1605 ENABLE_PCLK_PERIC0, 9, CLK_SET_RATE_PARENT, 0),
1606 GATE(CLK_PCLK_HSI2C0, "pclk_hsi2c0", "aclk_peric_66",
1607 ENABLE_PCLK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
1608 GATE(CLK_PCLK_I2C7, "pclk_i2c7", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1609 7, CLK_SET_RATE_PARENT, 0),
1610 GATE(CLK_PCLK_I2C6, "pclk_i2c6", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1611 6, CLK_SET_RATE_PARENT, 0),
1612 GATE(CLK_PCLK_I2C5, "pclk_i2c5", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1613 5, CLK_SET_RATE_PARENT, 0),
1614 GATE(CLK_PCLK_I2C4, "pclk_i2c4", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1615 4, CLK_SET_RATE_PARENT, 0),
1616 GATE(CLK_PCLK_I2C3, "pclk_i2c3", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1617 3, CLK_SET_RATE_PARENT, 0),
1618 GATE(CLK_PCLK_I2C2, "pclk_i2c2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1619 2, CLK_SET_RATE_PARENT, 0),
1620 GATE(CLK_PCLK_I2C1, "pclk_i2c1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1621 1, CLK_SET_RATE_PARENT, 0),
1622 GATE(CLK_PCLK_I2C0, "pclk_i2c0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1623 0, CLK_SET_RATE_PARENT, 0),
1625 /* ENABLE_PCLK_PERIC1 */
1626 GATE(CLK_PCLK_SPI4, "pclk_spi4", "aclk_peric_66", ENABLE_PCLK_PERIC1,
1627 9, CLK_SET_RATE_PARENT, 0),
1628 GATE(CLK_PCLK_SPI3, "pclk_spi3", "aclk_peric_66", ENABLE_PCLK_PERIC1,
1629 8, CLK_SET_RATE_PARENT, 0),
1630 GATE(CLK_PCLK_HSI2C11, "pclk_hsi2c11", "aclk_peric_66",
1631 ENABLE_PCLK_PERIC1, 7, CLK_SET_RATE_PARENT, 0),
1632 GATE(CLK_PCLK_HSI2C10, "pclk_hsi2c10", "aclk_peric_66",
1633 ENABLE_PCLK_PERIC1, 6, CLK_SET_RATE_PARENT, 0),
1634 GATE(CLK_PCLK_HSI2C9, "pclk_hsi2c9", "aclk_peric_66",
1635 ENABLE_PCLK_PERIC1, 5, CLK_SET_RATE_PARENT, 0),
1636 GATE(CLK_PCLK_HSI2C8, "pclk_hsi2c8", "aclk_peric_66",
1637 ENABLE_PCLK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
1638 GATE(CLK_PCLK_HSI2C7, "pclk_hsi2c7", "aclk_peric_66",
1639 ENABLE_PCLK_PERIC1, 3, CLK_SET_RATE_PARENT, 0),
1640 GATE(CLK_PCLK_HSI2C6, "pclk_hsi2c6", "aclk_peric_66",
1641 ENABLE_PCLK_PERIC1, 2, CLK_SET_RATE_PARENT, 0),
1642 GATE(CLK_PCLK_HSI2C5, "pclk_hsi2c5", "aclk_peric_66",
1643 ENABLE_PCLK_PERIC1, 1, CLK_SET_RATE_PARENT, 0),
1644 GATE(CLK_PCLK_HSI2C4, "pclk_hsi2c4", "aclk_peric_66",
1645 ENABLE_PCLK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),
1647 /* ENABLE_SCLK_PERIC */
1648 GATE(CLK_SCLK_IOCLK_SPI4, "sclk_ioclk_spi4", "ioclk_spi4_clk_in",
1649 ENABLE_SCLK_PERIC, 21, CLK_SET_RATE_PARENT, 0),
1650 GATE(CLK_SCLK_IOCLK_SPI3, "sclk_ioclk_spi3", "ioclk_spi3_clk_in",
1651 ENABLE_SCLK_PERIC, 20, CLK_SET_RATE_PARENT, 0),
1652 GATE(CLK_SCLK_SPI4, "sclk_spi4", "sclk_spi4_peric", ENABLE_SCLK_PERIC,
1653 19, CLK_SET_RATE_PARENT, 0),
1654 GATE(CLK_SCLK_SPI3, "sclk_spi3", "sclk_spi3_peric", ENABLE_SCLK_PERIC,
1655 18, CLK_SET_RATE_PARENT, 0),
1656 GATE(CLK_SCLK_SCI, "sclk_sci", "div_sclk_sci", ENABLE_SCLK_PERIC,
1658 GATE(CLK_SCLK_SC_IN, "sclk_sc_in", "div_sclk_sc_in", ENABLE_SCLK_PERIC,
1660 GATE(CLK_SCLK_PWM, "sclk_pwm", "oscclk", ENABLE_SCLK_PERIC, 15, 0, 0),
1661 GATE(CLK_SCLK_IOCLK_SPI2, "sclk_ioclk_spi2", "ioclk_spi2_clk_in",
1662 ENABLE_SCLK_PERIC, 13, CLK_SET_RATE_PARENT, 0),
1663 GATE(CLK_SCLK_IOCLK_SPI1, "sclk_ioclk_spi1", "ioclk_spi1_clk_in",
1664 ENABLE_SCLK_PERIC, 12, CLK_SET_RATE_PARENT, 0),
1665 GATE(CLK_SCLK_IOCLK_SPI0, "sclk_ioclk_spi0", "ioclk_spi0_clk_in",
1666 ENABLE_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
1667 GATE(CLK_SCLK_IOCLK_I2S1_BCLK, "sclk_ioclk_i2s1_bclk",
1668 "ioclk_i2s1_bclk_in", ENABLE_SCLK_PERIC, 10,
1669 CLK_SET_RATE_PARENT, 0),
1670 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "sclk_spdif_peric",
1671 ENABLE_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
1672 GATE(CLK_SCLK_PCM1, "sclk_pcm1", "sclk_pcm1_peric",
1673 ENABLE_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
1674 GATE(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_i2s1_peric",
1675 ENABLE_SCLK_PERIC, 6,
1676 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1677 GATE(CLK_SCLK_SPI2, "sclk_spi2", "sclk_spi2_peric", ENABLE_SCLK_PERIC,
1678 5, CLK_SET_RATE_PARENT, 0),
1679 GATE(CLK_SCLK_SPI1, "sclk_spi1", "sclk_spi1_peric", ENABLE_SCLK_PERIC,
1680 4, CLK_SET_RATE_PARENT, 0),
1681 GATE(CLK_SCLK_SPI0, "sclk_spi0", "sclk_spi0_peric", ENABLE_SCLK_PERIC,
1682 3, CLK_SET_RATE_PARENT, 0),
1683 GATE(CLK_SCLK_UART2, "sclk_uart2", "sclk_uart2_peric",
1684 ENABLE_SCLK_PERIC, 2,
1685 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1686 GATE(CLK_SCLK_UART1, "sclk_uart1", "sclk_uart1_peric",
1687 ENABLE_SCLK_PERIC, 1,
1688 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1689 GATE(CLK_SCLK_UART0, "sclk_uart0", "sclk_uart0_peric",
1690 ENABLE_SCLK_PERIC, 0,
1691 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1694 static const struct samsung_cmu_info peric_cmu_info __initconst = {
1695 .div_clks = peric_div_clks,
1696 .nr_div_clks = ARRAY_SIZE(peric_div_clks),
1697 .gate_clks = peric_gate_clks,
1698 .nr_gate_clks = ARRAY_SIZE(peric_gate_clks),
1699 .nr_clk_ids = PERIC_NR_CLK,
1700 .clk_regs = peric_clk_regs,
1701 .nr_clk_regs = ARRAY_SIZE(peric_clk_regs),
1704 static void __init exynos5433_cmu_peric_init(struct device_node *np)
1706 samsung_cmu_register_one(np, &peric_cmu_info);
1709 CLK_OF_DECLARE(exynos5433_cmu_peric, "samsung,exynos5433-cmu-peric",
1710 exynos5433_cmu_peric_init);
1713 * Register offset definitions for CMU_PERIS
1715 #define ENABLE_ACLK_PERIS 0x0800
1716 #define ENABLE_PCLK_PERIS 0x0900
1717 #define ENABLE_PCLK_PERIS_SECURE_TZPC 0x0904
1718 #define ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF 0x0908
1719 #define ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF 0x090c
1720 #define ENABLE_PCLK_PERIS_SECURE_TOPRTC 0x0910
1721 #define ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF 0x0914
1722 #define ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF 0x0918
1723 #define ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF 0x091c
1724 #define ENABLE_SCLK_PERIS 0x0a00
1725 #define ENABLE_SCLK_PERIS_SECURE_SECKEY 0x0a04
1726 #define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0a08
1727 #define ENABLE_SCLK_PERIS_SECURE_TOPRTC 0x0a0c
1728 #define ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE 0x0a10
1729 #define ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT 0x0a14
1730 #define ENABLE_SCLK_PERIS_SECURE_OTP_CON 0x0a18
1731 #define ENABLE_IP_PERIS0 0x0b00
1732 #define ENABLE_IP_PERIS1 0x0b04
1733 #define ENABLE_IP_PERIS_SECURE_TZPC 0x0b08
1734 #define ENABLE_IP_PERIS_SECURE_SECKEY 0x0b0c
1735 #define ENABLE_IP_PERIS_SECURE_CHIPID 0x0b10
1736 #define ENABLE_IP_PERIS_SECURE_TOPRTC 0x0b14
1737 #define ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE 0x0b18
1738 #define ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT 0x0b1c
1739 #define ENABLE_IP_PERIS_SECURE_OTP_CON 0x0b20
1741 static const unsigned long peris_clk_regs[] __initconst = {
1744 ENABLE_PCLK_PERIS_SECURE_TZPC,
1745 ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF,
1746 ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF,
1747 ENABLE_PCLK_PERIS_SECURE_TOPRTC,
1748 ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF,
1749 ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF,
1750 ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF,
1752 ENABLE_SCLK_PERIS_SECURE_SECKEY,
1753 ENABLE_SCLK_PERIS_SECURE_CHIPID,
1754 ENABLE_SCLK_PERIS_SECURE_TOPRTC,
1755 ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE,
1756 ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT,
1757 ENABLE_SCLK_PERIS_SECURE_OTP_CON,
1760 ENABLE_IP_PERIS_SECURE_TZPC,
1761 ENABLE_IP_PERIS_SECURE_SECKEY,
1762 ENABLE_IP_PERIS_SECURE_CHIPID,
1763 ENABLE_IP_PERIS_SECURE_TOPRTC,
1764 ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE,
1765 ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT,
1766 ENABLE_IP_PERIS_SECURE_OTP_CON,
1769 static const struct samsung_gate_clock peris_gate_clks[] __initconst = {
1770 /* ENABLE_ACLK_PERIS */
1771 GATE(CLK_ACLK_AHB2APB_PERIS1P, "aclk_ahb2apb_peris1p", "aclk_peris_66",
1772 ENABLE_ACLK_PERIS, 2, CLK_IGNORE_UNUSED, 0),
1773 GATE(CLK_ACLK_AHB2APB_PERIS0P, "aclk_ahb2apb_peris0p", "aclk_peris_66",
1774 ENABLE_ACLK_PERIS, 1, CLK_IGNORE_UNUSED, 0),
1775 GATE(CLK_ACLK_PERISNP_66, "aclk_perisnp_66", "aclk_peris_66",
1776 ENABLE_ACLK_PERIS, 0, CLK_IGNORE_UNUSED, 0),
1778 /* ENABLE_PCLK_PERIS */
1779 GATE(CLK_PCLK_HPM_APBIF, "pclk_hpm_apbif", "aclk_peris_66",
1780 ENABLE_PCLK_PERIS, 30, CLK_IGNORE_UNUSED, 0),
1781 GATE(CLK_PCLK_TMU1_APBIF, "pclk_tmu1_apbif", "aclk_peris_66",
1782 ENABLE_PCLK_PERIS, 24, CLK_IGNORE_UNUSED, 0),
1783 GATE(CLK_PCLK_TMU0_APBIF, "pclk_tmu0_apbif", "aclk_peris_66",
1784 ENABLE_PCLK_PERIS, 23, CLK_IGNORE_UNUSED, 0),
1785 GATE(CLK_PCLK_PMU_PERIS, "pclk_pmu_peris", "aclk_peris_66",
1786 ENABLE_PCLK_PERIS, 22, CLK_IGNORE_UNUSED, 0),
1787 GATE(CLK_PCLK_SYSREG_PERIS, "pclk_sysreg_peris", "aclk_peris_66",
1788 ENABLE_PCLK_PERIS, 21, CLK_IGNORE_UNUSED, 0),
1789 GATE(CLK_PCLK_CMU_TOP_APBIF, "pclk_cmu_top_apbif", "aclk_peris_66",
1790 ENABLE_PCLK_PERIS, 20, CLK_IGNORE_UNUSED, 0),
1791 GATE(CLK_PCLK_WDT_APOLLO, "pclk_wdt_apollo", "aclk_peris_66",
1792 ENABLE_PCLK_PERIS, 17, CLK_IGNORE_UNUSED, 0),
1793 GATE(CLK_PCLK_WDT_ATLAS, "pclk_wdt_atlas", "aclk_peris_66",
1794 ENABLE_PCLK_PERIS, 16, CLK_IGNORE_UNUSED, 0),
1795 GATE(CLK_PCLK_MCT, "pclk_mct", "aclk_peris_66",
1796 ENABLE_PCLK_PERIS, 15, CLK_IGNORE_UNUSED, 0),
1797 GATE(CLK_PCLK_HDMI_CEC, "pclk_hdmi_cec", "aclk_peris_66",
1798 ENABLE_PCLK_PERIS, 14, CLK_IGNORE_UNUSED, 0),
1800 /* ENABLE_PCLK_PERIS_SECURE_TZPC */
1801 GATE(CLK_PCLK_TZPC12, "pclk_tzpc12", "aclk_peris_66",
1802 ENABLE_PCLK_PERIS_SECURE_TZPC, 12, CLK_IGNORE_UNUSED, 0),
1803 GATE(CLK_PCLK_TZPC11, "pclk_tzpc11", "aclk_peris_66",
1804 ENABLE_PCLK_PERIS_SECURE_TZPC, 11, CLK_IGNORE_UNUSED, 0),
1805 GATE(CLK_PCLK_TZPC10, "pclk_tzpc10", "aclk_peris_66",
1806 ENABLE_PCLK_PERIS_SECURE_TZPC, 10, CLK_IGNORE_UNUSED, 0),
1807 GATE(CLK_PCLK_TZPC9, "pclk_tzpc9", "aclk_peris_66",
1808 ENABLE_PCLK_PERIS_SECURE_TZPC, 9, CLK_IGNORE_UNUSED, 0),
1809 GATE(CLK_PCLK_TZPC8, "pclk_tzpc8", "aclk_peris_66",
1810 ENABLE_PCLK_PERIS_SECURE_TZPC, 8, CLK_IGNORE_UNUSED, 0),
1811 GATE(CLK_PCLK_TZPC7, "pclk_tzpc7", "aclk_peris_66",
1812 ENABLE_PCLK_PERIS_SECURE_TZPC, 7, CLK_IGNORE_UNUSED, 0),
1813 GATE(CLK_PCLK_TZPC6, "pclk_tzpc6", "aclk_peris_66",
1814 ENABLE_PCLK_PERIS_SECURE_TZPC, 6, CLK_IGNORE_UNUSED, 0),
1815 GATE(CLK_PCLK_TZPC5, "pclk_tzpc5", "aclk_peris_66",
1816 ENABLE_PCLK_PERIS_SECURE_TZPC, 5, CLK_IGNORE_UNUSED, 0),
1817 GATE(CLK_PCLK_TZPC4, "pclk_tzpc4", "aclk_peris_66",
1818 ENABLE_PCLK_PERIS_SECURE_TZPC, 4, CLK_IGNORE_UNUSED, 0),
1819 GATE(CLK_PCLK_TZPC3, "pclk_tzpc3", "aclk_peris_66",
1820 ENABLE_PCLK_PERIS_SECURE_TZPC, 3, CLK_IGNORE_UNUSED, 0),
1821 GATE(CLK_PCLK_TZPC2, "pclk_tzpc2", "aclk_peris_66",
1822 ENABLE_PCLK_PERIS_SECURE_TZPC, 2, CLK_IGNORE_UNUSED, 0),
1823 GATE(CLK_PCLK_TZPC1, "pclk_tzpc1", "aclk_peris_66",
1824 ENABLE_PCLK_PERIS_SECURE_TZPC, 1, CLK_IGNORE_UNUSED, 0),
1825 GATE(CLK_PCLK_TZPC0, "pclk_tzpc0", "aclk_peris_66",
1826 ENABLE_PCLK_PERIS_SECURE_TZPC, 0, CLK_IGNORE_UNUSED, 0),
1828 /* ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF */
1829 GATE(CLK_PCLK_SECKEY_APBIF, "pclk_seckey_apbif", "aclk_peris_66",
1830 ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF, 0, CLK_IGNORE_UNUSED, 0),
1832 /* ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF */
1833 GATE(CLK_PCLK_CHIPID_APBIF, "pclk_chipid_apbif", "aclk_peris_66",
1834 ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF, 0, CLK_IGNORE_UNUSED, 0),
1836 /* ENABLE_PCLK_PERIS_SECURE_TOPRTC */
1837 GATE(CLK_PCLK_TOPRTC, "pclk_toprtc", "aclk_peris_66",
1838 ENABLE_PCLK_PERIS_SECURE_TOPRTC, 0, 0, 0),
1840 /* ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF */
1841 GATE(CLK_PCLK_CUSTOM_EFUSE_APBIF, "pclk_custom_efuse_apbif",
1843 ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF, 0, 0, 0),
1845 /* ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF */
1846 GATE(CLK_PCLK_ANTIRBK_CNT_APBIF, "pclk_antirbk_cnt_apbif",
1848 ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF, 0, 0, 0),
1850 /* ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF */
1851 GATE(CLK_PCLK_OTP_CON_APBIF, "pclk_otp_con_apbif",
1853 ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF, 0, 0, 0),
1855 /* ENABLE_SCLK_PERIS */
1856 GATE(CLK_SCLK_ASV_TB, "sclk_asv_tb", "oscclk_efuse_common",
1857 ENABLE_SCLK_PERIS, 10, 0, 0),
1858 GATE(CLK_SCLK_TMU1, "sclk_tmu1", "oscclk_efuse_common",
1859 ENABLE_SCLK_PERIS, 4, 0, 0),
1860 GATE(CLK_SCLK_TMU0, "sclk_tmu0", "oscclk_efuse_common",
1861 ENABLE_SCLK_PERIS, 3, 0, 0),
1863 /* ENABLE_SCLK_PERIS_SECURE_SECKEY */
1864 GATE(CLK_SCLK_SECKEY, "sclk_seckey", "oscclk_efuse_common",
1865 ENABLE_SCLK_PERIS_SECURE_SECKEY, 0, CLK_IGNORE_UNUSED, 0),
1867 /* ENABLE_SCLK_PERIS_SECURE_CHIPID */
1868 GATE(CLK_SCLK_CHIPID, "sclk_chipid", "oscclk_efuse_common",
1869 ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, CLK_IGNORE_UNUSED, 0),
1871 /* ENABLE_SCLK_PERIS_SECURE_TOPRTC */
1872 GATE(CLK_SCLK_TOPRTC, "sclk_toprtc", "oscclk_efuse_common",
1873 ENABLE_SCLK_PERIS_SECURE_TOPRTC, 0, 0, 0),
1875 /* ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE */
1876 GATE(CLK_SCLK_CUSTOM_EFUSE, "sclk_custom_efuse", "oscclk_efuse_common",
1877 ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE, 0, 0, 0),
1879 /* ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT */
1880 GATE(CLK_SCLK_ANTIRBK_CNT, "sclk_antirbk_cnt", "oscclk_efuse_common",
1881 ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT, 0, 0, 0),
1883 /* ENABLE_SCLK_PERIS_SECURE_OTP_CON */
1884 GATE(CLK_SCLK_OTP_CON, "sclk_otp_con", "oscclk_efuse_common",
1885 ENABLE_SCLK_PERIS_SECURE_OTP_CON, 0, 0, 0),
1888 static const struct samsung_cmu_info peris_cmu_info __initconst = {
1889 .gate_clks = peris_gate_clks,
1890 .nr_gate_clks = ARRAY_SIZE(peris_gate_clks),
1891 .nr_clk_ids = PERIS_NR_CLK,
1892 .clk_regs = peris_clk_regs,
1893 .nr_clk_regs = ARRAY_SIZE(peris_clk_regs),
1896 static void __init exynos5433_cmu_peris_init(struct device_node *np)
1898 samsung_cmu_register_one(np, &peris_cmu_info);
1901 CLK_OF_DECLARE(exynos5433_cmu_peris, "samsung,exynos5433-cmu-peris",
1902 exynos5433_cmu_peris_init);
1905 * Register offset definitions for CMU_FSYS
1907 #define MUX_SEL_FSYS0 0x0200
1908 #define MUX_SEL_FSYS1 0x0204
1909 #define MUX_SEL_FSYS2 0x0208
1910 #define MUX_SEL_FSYS3 0x020c
1911 #define MUX_SEL_FSYS4 0x0210
1912 #define MUX_ENABLE_FSYS0 0x0300
1913 #define MUX_ENABLE_FSYS1 0x0304
1914 #define MUX_ENABLE_FSYS2 0x0308
1915 #define MUX_ENABLE_FSYS3 0x030c
1916 #define MUX_ENABLE_FSYS4 0x0310
1917 #define MUX_STAT_FSYS0 0x0400
1918 #define MUX_STAT_FSYS1 0x0404
1919 #define MUX_STAT_FSYS2 0x0408
1920 #define MUX_STAT_FSYS3 0x040c
1921 #define MUX_STAT_FSYS4 0x0410
1922 #define MUX_IGNORE_FSYS2 0x0508
1923 #define MUX_IGNORE_FSYS3 0x050c
1924 #define ENABLE_ACLK_FSYS0 0x0800
1925 #define ENABLE_ACLK_FSYS1 0x0804
1926 #define ENABLE_PCLK_FSYS 0x0900
1927 #define ENABLE_SCLK_FSYS 0x0a00
1928 #define ENABLE_IP_FSYS0 0x0b00
1929 #define ENABLE_IP_FSYS1 0x0b04
1931 /* list of all parent clock list */
1932 PNAME(mout_sclk_ufs_mphy_user_p) = { "oscclk", "sclk_ufs_mphy", };
1933 PNAME(mout_aclk_fsys_200_user_p) = { "oscclk", "div_aclk_fsys_200", };
1934 PNAME(mout_sclk_pcie_100_user_p) = { "oscclk", "sclk_pcie_100_fsys",};
1935 PNAME(mout_sclk_ufsunipro_user_p) = { "oscclk", "sclk_ufsunipro_fsys",};
1936 PNAME(mout_sclk_mmc2_user_p) = { "oscclk", "sclk_mmc2_fsys", };
1937 PNAME(mout_sclk_mmc1_user_p) = { "oscclk", "sclk_mmc1_fsys", };
1938 PNAME(mout_sclk_mmc0_user_p) = { "oscclk", "sclk_mmc0_fsys", };
1939 PNAME(mout_sclk_usbhost30_user_p) = { "oscclk", "sclk_usbhost30_fsys",};
1940 PNAME(mout_sclk_usbdrd30_user_p) = { "oscclk", "sclk_usbdrd30_fsys", };
1942 PNAME(mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p)
1943 = { "oscclk", "phyclk_usbhost30_uhost30_pipe_pclk_phy", };
1944 PNAME(mout_phyclk_usbhost30_uhost30_phyclock_user_p)
1945 = { "oscclk", "phyclk_usbhost30_uhost30_phyclock_phy", };
1946 PNAME(mout_phyclk_usbhost20_phy_hsic1_p)
1947 = { "oscclk", "phyclk_usbhost20_phy_hsic1_phy", };
1948 PNAME(mout_phyclk_usbhost20_phy_clk48mohci_user_p)
1949 = { "oscclk", "phyclk_usbhost20_phy_clk48mohci_phy", };
1950 PNAME(mout_phyclk_usbhost20_phy_phyclock_user_p)
1951 = { "oscclk", "phyclk_usbhost20_phy_phyclock_phy", };
1952 PNAME(mout_phyclk_usbhost20_phy_freeclk_user_p)
1953 = { "oscclk", "phyclk_usbhost20_phy_freeclk_phy", };
1954 PNAME(mout_phyclk_usbdrd30_udrd30_pipe_pclk_p)
1955 = { "oscclk", "phyclk_usbdrd30_udrd30_pipe_pclk_phy", };
1956 PNAME(mout_phyclk_usbdrd30_udrd30_phyclock_user_p)
1957 = { "oscclk", "phyclk_usbdrd30_udrd30_phyclock_phy", };
1958 PNAME(mout_phyclk_ufs_rx1_symbol_user_p)
1959 = { "oscclk", "phyclk_ufs_rx1_symbol_phy", };
1960 PNAME(mout_phyclk_ufs_rx0_symbol_user_p)
1961 = { "oscclk", "phyclk_ufs_rx0_symbol_phy", };
1962 PNAME(mout_phyclk_ufs_tx1_symbol_user_p)
1963 = { "oscclk", "phyclk_ufs_tx1_symbol_phy", };
1964 PNAME(mout_phyclk_ufs_tx0_symbol_user_p)
1965 = { "oscclk", "phyclk_ufs_tx0_symbol_phy", };
1966 PNAME(mout_phyclk_lli_mphy_to_ufs_user_p)
1967 = { "oscclk", "phyclk_lli_mphy_to_ufs_phy", };
1968 PNAME(mout_sclk_mphy_p)
1969 = { "mout_sclk_ufs_mphy_user",
1970 "mout_phyclk_lli_mphy_to_ufs_user", };
1972 static const unsigned long fsys_clk_regs[] __initconst = {
1993 static const struct samsung_fixed_rate_clock fsys_fixed_clks[] __initconst = {
1994 /* PHY clocks from USBDRD30_PHY */
1995 FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY,
1996 "phyclk_usbdrd30_udrd30_phyclock_phy", NULL,
1998 FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY,
1999 "phyclk_usbdrd30_udrd30_pipe_pclk_phy", NULL,
2001 /* PHY clocks from USBHOST30_PHY */
2002 FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY,
2003 "phyclk_usbhost30_uhost30_phyclock_phy", NULL,
2005 FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY,
2006 "phyclk_usbhost30_uhost30_pipe_pclk_phy", NULL,
2008 /* PHY clocks from USBHOST20_PHY */
2009 FRATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK_PHY,
2010 "phyclk_usbhost20_phy_freeclk_phy", NULL, 0, 60000000),
2011 FRATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK_PHY,
2012 "phyclk_usbhost20_phy_phyclock_phy", NULL, 0, 60000000),
2013 FRATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI_PHY,
2014 "phyclk_usbhost20_phy_clk48mohci_phy", NULL,
2016 FRATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1_PHY,
2017 "phyclk_usbhost20_phy_hsic1_phy", NULL, 0,
2019 /* PHY clocks from UFS_PHY */
2020 FRATE(CLK_PHYCLK_UFS_TX0_SYMBOL_PHY, "phyclk_ufs_tx0_symbol_phy",
2021 NULL, 0, 300000000),
2022 FRATE(CLK_PHYCLK_UFS_RX0_SYMBOL_PHY, "phyclk_ufs_rx0_symbol_phy",
2023 NULL, 0, 300000000),
2024 FRATE(CLK_PHYCLK_UFS_TX1_SYMBOL_PHY, "phyclk_ufs_tx1_symbol_phy",
2025 NULL, 0, 300000000),
2026 FRATE(CLK_PHYCLK_UFS_RX1_SYMBOL_PHY, "phyclk_ufs_rx1_symbol_phy",
2027 NULL, 0, 300000000),
2028 /* PHY clocks from LLI_PHY */
2029 FRATE(CLK_PHYCLK_LLI_MPHY_TO_UFS_PHY, "phyclk_lli_mphy_to_ufs_phy",
2033 static const struct samsung_mux_clock fsys_mux_clks[] __initconst = {
2035 MUX(CLK_MOUT_SCLK_UFS_MPHY_USER, "mout_sclk_ufs_mphy_user",
2036 mout_sclk_ufs_mphy_user_p, MUX_SEL_FSYS0, 4, 1),
2037 MUX(CLK_MOUT_ACLK_FSYS_200_USER, "mout_aclk_fsys_200_user",
2038 mout_aclk_fsys_200_user_p, MUX_SEL_FSYS0, 0, 1),
2041 MUX(CLK_MOUT_SCLK_PCIE_100_USER, "mout_sclk_pcie_100_user",
2042 mout_sclk_pcie_100_user_p, MUX_SEL_FSYS1, 28, 1),
2043 MUX(CLK_MOUT_SCLK_UFSUNIPRO_USER, "mout_sclk_ufsunipro_user",
2044 mout_sclk_ufsunipro_user_p, MUX_SEL_FSYS1, 24, 1),
2045 MUX(CLK_MOUT_SCLK_MMC2_USER, "mout_sclk_mmc2_user",
2046 mout_sclk_mmc2_user_p, MUX_SEL_FSYS1, 20, 1),
2047 MUX(CLK_MOUT_SCLK_MMC1_USER, "mout_sclk_mmc1_user",
2048 mout_sclk_mmc1_user_p, MUX_SEL_FSYS1, 16, 1),
2049 MUX(CLK_MOUT_SCLK_MMC0_USER, "mout_sclk_mmc0_user",
2050 mout_sclk_mmc0_user_p, MUX_SEL_FSYS1, 12, 1),
2051 MUX(CLK_MOUT_SCLK_USBHOST30_USER, "mout_sclk_usbhost30_user",
2052 mout_sclk_usbhost30_user_p, MUX_SEL_FSYS1, 4, 1),
2053 MUX(CLK_MOUT_SCLK_USBDRD30_USER, "mout_sclk_usbdrd30_user",
2054 mout_sclk_usbdrd30_user_p, MUX_SEL_FSYS1, 0, 1),
2057 MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER,
2058 "mout_phyclk_usbhost30_uhost30_pipe_pclk_user",
2059 mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p,
2060 MUX_SEL_FSYS2, 28, 1),
2061 MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER,
2062 "mout_phyclk_usbhost30_uhost30_phyclock_user",
2063 mout_phyclk_usbhost30_uhost30_phyclock_user_p,
2064 MUX_SEL_FSYS2, 24, 1),
2065 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER,
2066 "mout_phyclk_usbhost20_phy_hsic1",
2067 mout_phyclk_usbhost20_phy_hsic1_p,
2068 MUX_SEL_FSYS2, 20, 1),
2069 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER,
2070 "mout_phyclk_usbhost20_phy_clk48mohci_user",
2071 mout_phyclk_usbhost20_phy_clk48mohci_user_p,
2072 MUX_SEL_FSYS2, 16, 1),
2073 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER,
2074 "mout_phyclk_usbhost20_phy_phyclock_user",
2075 mout_phyclk_usbhost20_phy_phyclock_user_p,
2076 MUX_SEL_FSYS2, 12, 1),
2077 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER,
2078 "mout_phyclk_usbhost20_phy_freeclk_user",
2079 mout_phyclk_usbhost20_phy_freeclk_user_p,
2080 MUX_SEL_FSYS2, 8, 1),
2081 MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER,
2082 "mout_phyclk_usbdrd30_udrd30_pipe_pclk_user",
2083 mout_phyclk_usbdrd30_udrd30_pipe_pclk_p,
2084 MUX_SEL_FSYS2, 4, 1),
2085 MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER,
2086 "mout_phyclk_usbdrd30_udrd30_phyclock_user",
2087 mout_phyclk_usbdrd30_udrd30_phyclock_user_p,
2088 MUX_SEL_FSYS2, 0, 1),
2091 MUX(CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER,
2092 "mout_phyclk_ufs_rx1_symbol_user",
2093 mout_phyclk_ufs_rx1_symbol_user_p,
2094 MUX_SEL_FSYS3, 16, 1),
2095 MUX(CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER,
2096 "mout_phyclk_ufs_rx0_symbol_user",
2097 mout_phyclk_ufs_rx0_symbol_user_p,
2098 MUX_SEL_FSYS3, 12, 1),
2099 MUX(CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER,
2100 "mout_phyclk_ufs_tx1_symbol_user",
2101 mout_phyclk_ufs_tx1_symbol_user_p,
2102 MUX_SEL_FSYS3, 8, 1),
2103 MUX(CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER,
2104 "mout_phyclk_ufs_tx0_symbol_user",
2105 mout_phyclk_ufs_tx0_symbol_user_p,
2106 MUX_SEL_FSYS3, 4, 1),
2107 MUX(CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER,
2108 "mout_phyclk_lli_mphy_to_ufs_user",
2109 mout_phyclk_lli_mphy_to_ufs_user_p,
2110 MUX_SEL_FSYS3, 0, 1),
2113 MUX(CLK_MOUT_SCLK_MPHY, "mout_sclk_mphy", mout_sclk_mphy_p,
2114 MUX_SEL_FSYS4, 0, 1),
2117 static const struct samsung_gate_clock fsys_gate_clks[] __initconst = {
2118 /* ENABLE_ACLK_FSYS0 */
2119 GATE(CLK_ACLK_PCIE, "aclk_pcie", "mout_aclk_fsys_200_user",
2120 ENABLE_ACLK_FSYS0, 13, CLK_IGNORE_UNUSED, 0),
2121 GATE(CLK_ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys_200_user",
2122 ENABLE_ACLK_FSYS0, 11, CLK_IGNORE_UNUSED, 0),
2123 GATE(CLK_ACLK_TSI, "aclk_tsi", "mout_aclk_fsys_200_user",
2124 ENABLE_ACLK_FSYS0, 10, CLK_IGNORE_UNUSED, 0),
2125 GATE(CLK_ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys_200_user",
2126 ENABLE_ACLK_FSYS0, 8, CLK_IGNORE_UNUSED, 0),
2127 GATE(CLK_ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys_200_user",
2128 ENABLE_ACLK_FSYS0, 7, CLK_IGNORE_UNUSED, 0),
2129 GATE(CLK_ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys_200_user",
2130 ENABLE_ACLK_FSYS0, 6, CLK_IGNORE_UNUSED, 0),
2131 GATE(CLK_ACLK_UFS, "aclk_ufs", "mout_aclk_fsys_200_user",
2132 ENABLE_ACLK_FSYS0, 5, CLK_IGNORE_UNUSED, 0),
2133 GATE(CLK_ACLK_USBHOST20, "aclk_usbhost20", "mout_aclk_fsys_200_user",
2134 ENABLE_ACLK_FSYS0, 3, CLK_IGNORE_UNUSED, 0),
2135 GATE(CLK_ACLK_USBHOST30, "aclk_usbhost30", "mout_aclk_fsys_200_user",
2136 ENABLE_ACLK_FSYS0, 2, CLK_IGNORE_UNUSED, 0),
2137 GATE(CLK_ACLK_USBDRD30, "aclk_usbdrd30", "mout_aclk_fsys_200_user",
2138 ENABLE_ACLK_FSYS0, 1, CLK_IGNORE_UNUSED, 0),
2139 GATE(CLK_ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys_200_user",
2140 ENABLE_ACLK_FSYS0, 0, CLK_IGNORE_UNUSED, 0),
2142 /* ENABLE_ACLK_FSYS1 */
2143 GATE(CLK_ACLK_XIU_FSYSPX, "aclk_xiu_fsyspx", "mout_aclk_fsys_200_user",
2144 ENABLE_ACLK_FSYS1, 27, CLK_IGNORE_UNUSED, 0),
2145 GATE(CLK_ACLK_AHB_USBLINKH1, "aclk_ahb_usblinkh1",
2146 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2147 26, CLK_IGNORE_UNUSED, 0),
2148 GATE(CLK_ACLK_SMMU_PDMA1, "aclk_smmu_pdma1", "mout_aclk_fsys_200_user",
2149 ENABLE_ACLK_FSYS1, 25, CLK_IGNORE_UNUSED, 0),
2150 GATE(CLK_ACLK_BTS_PCIE, "aclk_bts_pcie", "mout_aclk_fsys_200_user",
2151 ENABLE_ACLK_FSYS1, 24, CLK_IGNORE_UNUSED, 0),
2152 GATE(CLK_ACLK_AXIUS_PDMA1, "aclk_axius_pdma1",
2153 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2154 22, CLK_IGNORE_UNUSED, 0),
2155 GATE(CLK_ACLK_SMMU_PDMA0, "aclk_smmu_pdma0", "mout_aclk_fsys_200_user",
2156 ENABLE_ACLK_FSYS1, 17, CLK_IGNORE_UNUSED, 0),
2157 GATE(CLK_ACLK_BTS_UFS, "aclk_bts_ufs", "mout_aclk_fsys_200_user",
2158 ENABLE_ACLK_FSYS1, 14, CLK_IGNORE_UNUSED, 0),
2159 GATE(CLK_ACLK_BTS_USBHOST30, "aclk_bts_usbhost30",
2160 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2162 GATE(CLK_ACLK_BTS_USBDRD30, "aclk_bts_usbdrd30",
2163 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2165 GATE(CLK_ACLK_AXIUS_PDMA0, "aclk_axius_pdma0",
2166 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2167 11, CLK_IGNORE_UNUSED, 0),
2168 GATE(CLK_ACLK_AXIUS_USBHS, "aclk_axius_usbhs",
2169 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2170 10, CLK_IGNORE_UNUSED, 0),
2171 GATE(CLK_ACLK_AXIUS_FSYSSX, "aclk_axius_fsyssx",
2172 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2173 9, CLK_IGNORE_UNUSED, 0),
2174 GATE(CLK_ACLK_AHB2APB_FSYSP, "aclk_ahb2apb_fsysp",
2175 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2176 8, CLK_IGNORE_UNUSED, 0),
2177 GATE(CLK_ACLK_AHB2AXI_USBHS, "aclk_ahb2axi_usbhs",
2178 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2179 7, CLK_IGNORE_UNUSED, 0),
2180 GATE(CLK_ACLK_AHB_USBLINKH0, "aclk_ahb_usblinkh0",
2181 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2182 6, CLK_IGNORE_UNUSED, 0),
2183 GATE(CLK_ACLK_AHB_USBHS, "aclk_ahb_usbhs", "mout_aclk_fsys_200_user",
2184 ENABLE_ACLK_FSYS1, 5, CLK_IGNORE_UNUSED, 0),
2185 GATE(CLK_ACLK_AHB_FSYSH, "aclk_ahb_fsysh", "mout_aclk_fsys_200_user",
2186 ENABLE_ACLK_FSYS1, 4, CLK_IGNORE_UNUSED, 0),
2187 GATE(CLK_ACLK_XIU_FSYSX, "aclk_xiu_fsysx", "mout_aclk_fsys_200_user",
2188 ENABLE_ACLK_FSYS1, 3, CLK_IGNORE_UNUSED, 0),
2189 GATE(CLK_ACLK_XIU_FSYSSX, "aclk_xiu_fsyssx", "mout_aclk_fsys_200_user",
2190 ENABLE_ACLK_FSYS1, 2, CLK_IGNORE_UNUSED, 0),
2191 GATE(CLK_ACLK_FSYSNP_200, "aclk_fsysnp_200", "mout_aclk_fsys_200_user",
2192 ENABLE_ACLK_FSYS1, 1, CLK_IGNORE_UNUSED, 0),
2193 GATE(CLK_ACLK_FSYSND_200, "aclk_fsysnd_200", "mout_aclk_fsys_200_user",
2194 ENABLE_ACLK_FSYS1, 0, CLK_IGNORE_UNUSED, 0),
2196 /* ENABLE_PCLK_FSYS */
2197 GATE(CLK_PCLK_PCIE_CTRL, "pclk_pcie_ctrl", "mout_aclk_fsys_200_user",
2198 ENABLE_PCLK_FSYS, 17, CLK_IGNORE_UNUSED, 0),
2199 GATE(CLK_PCLK_SMMU_PDMA1, "pclk_smmu_pdma1", "mout_aclk_fsys_200_user",
2200 ENABLE_PCLK_FSYS, 16, CLK_IGNORE_UNUSED, 0),
2201 GATE(CLK_PCLK_PCIE_PHY, "pclk_pcie_phy", "mout_aclk_fsys_200_user",
2202 ENABLE_PCLK_FSYS, 14, CLK_IGNORE_UNUSED, 0),
2203 GATE(CLK_PCLK_BTS_PCIE, "pclk_bts_pcie", "mout_aclk_fsys_200_user",
2204 ENABLE_PCLK_FSYS, 13, CLK_IGNORE_UNUSED, 0),
2205 GATE(CLK_PCLK_SMMU_PDMA0, "pclk_smmu_pdma0", "mout_aclk_fsys_200_user",
2206 ENABLE_PCLK_FSYS, 8, CLK_IGNORE_UNUSED, 0),
2207 GATE(CLK_PCLK_BTS_UFS, "pclk_bts_ufs", "mout_aclk_fsys_200_user",
2208 ENABLE_PCLK_FSYS, 5, 0, 0),
2209 GATE(CLK_PCLK_BTS_USBHOST30, "pclk_bts_usbhost30",
2210 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 4, 0, 0),
2211 GATE(CLK_PCLK_BTS_USBDRD30, "pclk_bts_usbdrd30",
2212 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 3, 0, 0),
2213 GATE(CLK_PCLK_GPIO_FSYS, "pclk_gpio_fsys", "mout_aclk_fsys_200_user",
2214 ENABLE_PCLK_FSYS, 2, CLK_IGNORE_UNUSED, 0),
2215 GATE(CLK_PCLK_PMU_FSYS, "pclk_pmu_fsys", "mout_aclk_fsys_200_user",
2216 ENABLE_PCLK_FSYS, 1, CLK_IGNORE_UNUSED, 0),
2217 GATE(CLK_PCLK_SYSREG_FSYS, "pclk_sysreg_fsys",
2218 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS,
2219 0, CLK_IGNORE_UNUSED, 0),
2221 /* ENABLE_SCLK_FSYS */
2222 GATE(CLK_SCLK_PCIE_100, "sclk_pcie_100", "mout_sclk_pcie_100_user",
2223 ENABLE_SCLK_FSYS, 21, 0, 0),
2224 GATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK,
2225 "phyclk_usbhost30_uhost30_pipe_pclk",
2226 "mout_phyclk_usbhost30_uhost30_pipe_pclk_user",
2227 ENABLE_SCLK_FSYS, 18, 0, 0),
2228 GATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK,
2229 "phyclk_usbhost30_uhost30_phyclock",
2230 "mout_phyclk_usbhost30_uhost30_phyclock_user",
2231 ENABLE_SCLK_FSYS, 17, 0, 0),
2232 GATE(CLK_PHYCLK_UFS_RX1_SYMBOL, "phyclk_ufs_rx1_symbol",
2233 "mout_phyclk_ufs_rx1_symbol_user", ENABLE_SCLK_FSYS,
2235 GATE(CLK_PHYCLK_UFS_RX0_SYMBOL, "phyclk_ufs_rx0_symbol",
2236 "mout_phyclk_ufs_rx0_symbol_user", ENABLE_SCLK_FSYS,
2238 GATE(CLK_PHYCLK_UFS_TX1_SYMBOL, "phyclk_ufs_tx1_symbol",
2239 "mout_phyclk_ufs_tx1_symbol_user", ENABLE_SCLK_FSYS,
2241 GATE(CLK_PHYCLK_UFS_TX0_SYMBOL, "phyclk_ufs_tx0_symbol",
2242 "mout_phyclk_ufs_tx0_symbol_user", ENABLE_SCLK_FSYS,
2244 GATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1, "phyclk_usbhost20_phy_hsic1",
2245 "mout_phyclk_usbhost20_phy_hsic1", ENABLE_SCLK_FSYS,
2247 GATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI,
2248 "phyclk_usbhost20_phy_clk48mohci",
2249 "mout_phyclk_usbhost20_phy_clk48mohci_user",
2250 ENABLE_SCLK_FSYS, 11, 0, 0),
2251 GATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK,
2252 "phyclk_usbhost20_phy_phyclock",
2253 "mout_phyclk_usbhost20_phy_phyclock_user",
2254 ENABLE_SCLK_FSYS, 10, 0, 0),
2255 GATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK,
2256 "phyclk_usbhost20_phy_freeclk",
2257 "mout_phyclk_usbhost20_phy_freeclk_user",
2258 ENABLE_SCLK_FSYS, 9, 0, 0),
2259 GATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK,
2260 "phyclk_usbdrd30_udrd30_pipe_pclk",
2261 "mout_phyclk_usbdrd30_udrd30_pipe_pclk_user",
2262 ENABLE_SCLK_FSYS, 8, 0, 0),
2263 GATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK,
2264 "phyclk_usbdrd30_udrd30_phyclock",
2265 "mout_phyclk_usbdrd30_udrd30_phyclock_user",
2266 ENABLE_SCLK_FSYS, 7, 0, 0),
2267 GATE(CLK_SCLK_MPHY, "sclk_mphy", "mout_sclk_mphy",
2268 ENABLE_SCLK_FSYS, 6, 0, 0),
2269 GATE(CLK_SCLK_UFSUNIPRO, "sclk_ufsunipro", "mout_sclk_ufsunipro_user",
2270 ENABLE_SCLK_FSYS, 5, 0, 0),
2271 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "mout_sclk_mmc2_user",
2272 ENABLE_SCLK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
2273 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "mout_sclk_mmc1_user",
2274 ENABLE_SCLK_FSYS, 3, CLK_SET_RATE_PARENT, 0),
2275 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "mout_sclk_mmc0_user",
2276 ENABLE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
2277 GATE(CLK_SCLK_USBHOST30, "sclk_usbhost30", "mout_sclk_usbhost30_user",
2278 ENABLE_SCLK_FSYS, 1, 0, 0),
2279 GATE(CLK_SCLK_USBDRD30, "sclk_usbdrd30", "mout_sclk_usbdrd30_user",
2280 ENABLE_SCLK_FSYS, 0, 0, 0),
2282 /* ENABLE_IP_FSYS0 */
2283 GATE(CLK_PCIE, "pcie", "sclk_pcie_100", ENABLE_IP_FSYS0, 17, 0, 0),
2284 GATE(CLK_PDMA1, "pdma1", "aclk_pdma1", ENABLE_IP_FSYS0, 15, 0, 0),
2285 GATE(CLK_PDMA0, "pdma0", "aclk_pdma0", ENABLE_IP_FSYS0, 0, 0, 0),
2288 static const struct samsung_cmu_info fsys_cmu_info __initconst = {
2289 .mux_clks = fsys_mux_clks,
2290 .nr_mux_clks = ARRAY_SIZE(fsys_mux_clks),
2291 .gate_clks = fsys_gate_clks,
2292 .nr_gate_clks = ARRAY_SIZE(fsys_gate_clks),
2293 .fixed_clks = fsys_fixed_clks,
2294 .nr_fixed_clks = ARRAY_SIZE(fsys_fixed_clks),
2295 .nr_clk_ids = FSYS_NR_CLK,
2296 .clk_regs = fsys_clk_regs,
2297 .nr_clk_regs = ARRAY_SIZE(fsys_clk_regs),
2300 static void __init exynos5433_cmu_fsys_init(struct device_node *np)
2302 samsung_cmu_register_one(np, &fsys_cmu_info);
2305 CLK_OF_DECLARE(exynos5433_cmu_fsys, "samsung,exynos5433-cmu-fsys",
2306 exynos5433_cmu_fsys_init);
2309 * Register offset definitions for CMU_G2D
2311 #define MUX_SEL_G2D0 0x0200
2312 #define MUX_SEL_ENABLE_G2D0 0x0300
2313 #define MUX_SEL_STAT_G2D0 0x0400
2314 #define DIV_G2D 0x0600
2315 #define DIV_STAT_G2D 0x0700
2316 #define DIV_ENABLE_ACLK_G2D 0x0800
2317 #define DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D 0x0804
2318 #define DIV_ENABLE_PCLK_G2D 0x0900
2319 #define DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D 0x0904
2320 #define DIV_ENABLE_IP_G2D0 0x0b00
2321 #define DIV_ENABLE_IP_G2D1 0x0b04
2322 #define DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D 0x0b08
2324 static const unsigned long g2d_clk_regs[] __initconst = {
2326 MUX_SEL_ENABLE_G2D0,
2328 DIV_ENABLE_ACLK_G2D,
2329 DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D,
2330 DIV_ENABLE_PCLK_G2D,
2331 DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D,
2334 DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D,
2337 /* list of all parent clock list */
2338 PNAME(mout_aclk_g2d_266_user_p) = { "oscclk", "aclk_g2d_266", };
2339 PNAME(mout_aclk_g2d_400_user_p) = { "oscclk", "aclk_g2d_400", };
2341 static const struct samsung_mux_clock g2d_mux_clks[] __initconst = {
2343 MUX(CLK_MUX_ACLK_G2D_266_USER, "mout_aclk_g2d_266_user",
2344 mout_aclk_g2d_266_user_p, MUX_SEL_G2D0, 4, 1),
2345 MUX(CLK_MUX_ACLK_G2D_400_USER, "mout_aclk_g2d_400_user",
2346 mout_aclk_g2d_400_user_p, MUX_SEL_G2D0, 0, 1),
2349 static const struct samsung_div_clock g2d_div_clks[] __initconst = {
2351 DIV(CLK_DIV_PCLK_G2D, "div_pclk_g2d", "mout_aclk_g2d_266_user",
2355 static const struct samsung_gate_clock g2d_gate_clks[] __initconst = {
2356 /* DIV_ENABLE_ACLK_G2D */
2357 GATE(CLK_ACLK_SMMU_MDMA1, "aclk_smmu_mdma1", "mout_aclk_g2d_266_user",
2358 DIV_ENABLE_ACLK_G2D, 12, 0, 0),
2359 GATE(CLK_ACLK_BTS_MDMA1, "aclk_bts_mdam1", "mout_aclk_g2d_266_user",
2360 DIV_ENABLE_ACLK_G2D, 11, 0, 0),
2361 GATE(CLK_ACLK_BTS_G2D, "aclk_bts_g2d", "mout_aclk_g2d_400_user",
2362 DIV_ENABLE_ACLK_G2D, 10, 0, 0),
2363 GATE(CLK_ACLK_ALB_G2D, "aclk_alb_g2d", "mout_aclk_g2d_400_user",
2364 DIV_ENABLE_ACLK_G2D, 9, 0, 0),
2365 GATE(CLK_ACLK_AXIUS_G2DX, "aclk_axius_g2dx", "mout_aclk_g2d_400_user",
2366 DIV_ENABLE_ACLK_G2D, 8, 0, 0),
2367 GATE(CLK_ACLK_ASYNCAXI_SYSX, "aclk_asyncaxi_sysx",
2368 "mout_aclk_g2d_400_user", DIV_ENABLE_ACLK_G2D,
2370 GATE(CLK_ACLK_AHB2APB_G2D1P, "aclk_ahb2apb_g2d1p", "div_pclk_g2d",
2371 DIV_ENABLE_ACLK_G2D, 6, CLK_IGNORE_UNUSED, 0),
2372 GATE(CLK_ACLK_AHB2APB_G2D0P, "aclk_ahb2apb_g2d0p", "div_pclk_g2d",
2373 DIV_ENABLE_ACLK_G2D, 5, CLK_IGNORE_UNUSED, 0),
2374 GATE(CLK_ACLK_XIU_G2DX, "aclk_xiu_g2dx", "mout_aclk_g2d_400_user",
2375 DIV_ENABLE_ACLK_G2D, 4, CLK_IGNORE_UNUSED, 0),
2376 GATE(CLK_ACLK_G2DNP_133, "aclk_g2dnp_133", "div_pclk_g2d",
2377 DIV_ENABLE_ACLK_G2D, 3, CLK_IGNORE_UNUSED, 0),
2378 GATE(CLK_ACLK_G2DND_400, "aclk_g2dnd_400", "mout_aclk_g2d_400_user",
2379 DIV_ENABLE_ACLK_G2D, 2, CLK_IGNORE_UNUSED, 0),
2380 GATE(CLK_ACLK_MDMA1, "aclk_mdma1", "mout_aclk_g2d_266_user",
2381 DIV_ENABLE_ACLK_G2D, 1, 0, 0),
2382 GATE(CLK_ACLK_G2D, "aclk_g2d", "mout_aclk_g2d_400_user",
2383 DIV_ENABLE_ACLK_G2D, 0, 0, 0),
2385 /* DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D */
2386 GATE(CLK_ACLK_SMMU_G2D, "aclk_smmu_g2d", "mout_aclk_g2d_400_user",
2387 DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D, 0, 0, 0),
2389 /* DIV_ENABLE_PCLK_G2D */
2390 GATE(CLK_PCLK_SMMU_MDMA1, "pclk_smmu_mdma1", "div_pclk_g2d",
2391 DIV_ENABLE_PCLK_G2D, 7, 0, 0),
2392 GATE(CLK_PCLK_BTS_MDMA1, "pclk_bts_mdam1", "div_pclk_g2d",
2393 DIV_ENABLE_PCLK_G2D, 6, 0, 0),
2394 GATE(CLK_PCLK_BTS_G2D, "pclk_bts_g2d", "div_pclk_g2d",
2395 DIV_ENABLE_PCLK_G2D, 5, 0, 0),
2396 GATE(CLK_PCLK_ALB_G2D, "pclk_alb_g2d", "div_pclk_g2d",
2397 DIV_ENABLE_PCLK_G2D, 4, 0, 0),
2398 GATE(CLK_PCLK_ASYNCAXI_SYSX, "pclk_asyncaxi_sysx", "div_pclk_g2d",
2399 DIV_ENABLE_PCLK_G2D, 3, 0, 0),
2400 GATE(CLK_PCLK_PMU_G2D, "pclk_pmu_g2d", "div_pclk_g2d",
2401 DIV_ENABLE_PCLK_G2D, 2, CLK_IGNORE_UNUSED, 0),
2402 GATE(CLK_PCLK_SYSREG_G2D, "pclk_sysreg_g2d", "div_pclk_g2d",
2403 DIV_ENABLE_PCLK_G2D, 1, CLK_IGNORE_UNUSED, 0),
2404 GATE(CLK_PCLK_G2D, "pclk_g2d", "div_pclk_g2d", DIV_ENABLE_PCLK_G2D,
2407 /* DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D */
2408 GATE(CLK_PCLK_SMMU_G2D, "pclk_smmu_g2d", "div_pclk_g2d",
2409 DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D, 0, 0, 0),
2412 static const struct samsung_cmu_info g2d_cmu_info __initconst = {
2413 .mux_clks = g2d_mux_clks,
2414 .nr_mux_clks = ARRAY_SIZE(g2d_mux_clks),
2415 .div_clks = g2d_div_clks,
2416 .nr_div_clks = ARRAY_SIZE(g2d_div_clks),
2417 .gate_clks = g2d_gate_clks,
2418 .nr_gate_clks = ARRAY_SIZE(g2d_gate_clks),
2419 .nr_clk_ids = G2D_NR_CLK,
2420 .clk_regs = g2d_clk_regs,
2421 .nr_clk_regs = ARRAY_SIZE(g2d_clk_regs),
2424 static void __init exynos5433_cmu_g2d_init(struct device_node *np)
2426 samsung_cmu_register_one(np, &g2d_cmu_info);
2429 CLK_OF_DECLARE(exynos5433_cmu_g2d, "samsung,exynos5433-cmu-g2d",
2430 exynos5433_cmu_g2d_init);
2433 * Register offset definitions for CMU_DISP
2435 #define DISP_PLL_LOCK 0x0000
2436 #define DISP_PLL_CON0 0x0100
2437 #define DISP_PLL_CON1 0x0104
2438 #define DISP_PLL_FREQ_DET 0x0108
2439 #define MUX_SEL_DISP0 0x0200
2440 #define MUX_SEL_DISP1 0x0204
2441 #define MUX_SEL_DISP2 0x0208
2442 #define MUX_SEL_DISP3 0x020c
2443 #define MUX_SEL_DISP4 0x0210
2444 #define MUX_ENABLE_DISP0 0x0300
2445 #define MUX_ENABLE_DISP1 0x0304
2446 #define MUX_ENABLE_DISP2 0x0308
2447 #define MUX_ENABLE_DISP3 0x030c
2448 #define MUX_ENABLE_DISP4 0x0310
2449 #define MUX_STAT_DISP0 0x0400
2450 #define MUX_STAT_DISP1 0x0404
2451 #define MUX_STAT_DISP2 0x0408
2452 #define MUX_STAT_DISP3 0x040c
2453 #define MUX_STAT_DISP4 0x0410
2454 #define MUX_IGNORE_DISP2 0x0508
2455 #define DIV_DISP 0x0600
2456 #define DIV_DISP_PLL_FREQ_DET 0x0604
2457 #define DIV_STAT_DISP 0x0700
2458 #define DIV_STAT_DISP_PLL_FREQ_DET 0x0704
2459 #define ENABLE_ACLK_DISP0 0x0800
2460 #define ENABLE_ACLK_DISP1 0x0804
2461 #define ENABLE_PCLK_DISP 0x0900
2462 #define ENABLE_SCLK_DISP 0x0a00
2463 #define ENABLE_IP_DISP0 0x0b00
2464 #define ENABLE_IP_DISP1 0x0b04
2465 #define CLKOUT_CMU_DISP 0x0c00
2466 #define CLKOUT_CMU_DISP_DIV_STAT 0x0c04
2468 static const unsigned long disp_clk_regs[] __initconst = {
2485 DIV_DISP_PLL_FREQ_DET,
2493 CLKOUT_CMU_DISP_DIV_STAT,
2496 /* list of all parent clock list */
2497 PNAME(mout_disp_pll_p) = { "oscclk", "fout_disp_pll", };
2498 PNAME(mout_sclk_dsim1_user_p) = { "oscclk", "sclk_dsim1_disp", };
2499 PNAME(mout_sclk_dsim0_user_p) = { "oscclk", "sclk_dsim0_disp", };
2500 PNAME(mout_sclk_dsd_user_p) = { "oscclk", "sclk_dsd_disp", };
2501 PNAME(mout_sclk_decon_tv_eclk_user_p) = { "oscclk",
2502 "sclk_decon_tv_eclk_disp", };
2503 PNAME(mout_sclk_decon_vclk_user_p) = { "oscclk",
2504 "sclk_decon_vclk_disp", };
2505 PNAME(mout_sclk_decon_eclk_user_p) = { "oscclk",
2506 "sclk_decon_eclk_disp", };
2507 PNAME(mout_sclk_decon_tv_vlkc_user_p) = { "oscclk",
2508 "sclk_decon_tv_vclk_disp", };
2509 PNAME(mout_aclk_disp_333_user_p) = { "oscclk", "aclk_disp_333", };
2511 PNAME(mout_phyclk_mipidphy1_bitclkdiv8_user_p) = { "oscclk",
2512 "phyclk_mipidphy1_bitclkdiv8_phy", };
2513 PNAME(mout_phyclk_mipidphy1_rxclkesc0_user_p) = { "oscclk",
2514 "phyclk_mipidphy1_rxclkesc0_phy", };
2515 PNAME(mout_phyclk_mipidphy0_bitclkdiv8_user_p) = { "oscclk",
2516 "phyclk_mipidphy0_bitclkdiv8_phy", };
2517 PNAME(mout_phyclk_mipidphy0_rxclkesc0_user_p) = { "oscclk",
2518 "phyclk_mipidphy0_rxclkesc0_phy", };
2519 PNAME(mout_phyclk_hdmiphy_tmds_clko_user_p) = { "oscclk",
2520 "phyclk_hdmiphy_tmds_clko_phy", };
2521 PNAME(mout_phyclk_hdmiphy_pixel_clko_user_p) = { "oscclk",
2522 "phyclk_hdmiphy_pixel_clko_phy", };
2524 PNAME(mout_sclk_dsim0_p) = { "mout_disp_pll",
2525 "mout_sclk_dsim0_user", };
2526 PNAME(mout_sclk_decon_tv_eclk_p) = { "mout_disp_pll",
2527 "mout_sclk_decon_tv_eclk_user", };
2528 PNAME(mout_sclk_decon_vclk_p) = { "mout_disp_pll",
2529 "mout_sclk_decon_vclk_user", };
2530 PNAME(mout_sclk_decon_eclk_p) = { "mout_disp_pll",
2531 "mout_sclk_decon_eclk_user", };
2533 PNAME(mout_sclk_dsim1_b_disp_p) = { "mout_sclk_dsim1_a_disp",
2534 "mout_sclk_dsim1_user", };
2535 PNAME(mout_sclk_decon_tv_vclk_c_disp_p) = {
2536 "mout_phyclk_hdmiphy_pixel_clko_user",
2537 "mout_sclk_decon_tv_vclk_b_disp", };
2538 PNAME(mout_sclk_decon_tv_vclk_b_disp_p) = { "mout_sclk_decon_tv_vclk_a_disp",
2539 "mout_sclk_decon_tv_vclk_user", };
2541 static const struct samsung_pll_clock disp_pll_clks[] __initconst = {
2542 PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll", "oscclk",
2543 DISP_PLL_LOCK, DISP_PLL_CON0, exynos5443_pll_rates),
2546 static const struct samsung_fixed_factor_clock disp_fixed_factor_clks[] __initconst = {
2548 * sclk_rgb_{vclk|tv_vclk} is half clock of sclk_decon_{vclk|tv_vclk}.
2549 * The divider has fixed value (2) between sclk_rgb_{vclk|tv_vclk}
2550 * and sclk_decon_{vclk|tv_vclk}.
2552 FFACTOR(CLK_SCLK_RGB_VCLK, "sclk_rgb_vclk", "sclk_decon_vclk",
2554 FFACTOR(CLK_SCLK_RGB_TV_VCLK, "sclk_rgb_tv_vclk", "sclk_decon_tv_vclk",
2558 static const struct samsung_fixed_rate_clock disp_fixed_clks[] __initconst = {
2559 /* PHY clocks from MIPI_DPHY1 */
2560 FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, 0, 188000000),
2561 FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, 0, 100000000),
2562 /* PHY clocks from MIPI_DPHY0 */
2563 FRATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY, "phyclk_mipidphy0_bitclkdiv8_phy",
2564 NULL, 0, 188000000),
2565 FRATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY, "phyclk_mipidphy0_rxclkesc0_phy",
2566 NULL, 0, 100000000),
2567 /* PHY clocks from HDMI_PHY */
2568 FRATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY, "phyclk_hdmiphy_tmds_clko_phy",
2569 NULL, 0, 300000000),
2570 FRATE(CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY, "phyclk_hdmiphy_pixel_clko_phy",
2571 NULL, 0, 166000000),
2574 static const struct samsung_mux_clock disp_mux_clks[] __initconst = {
2576 MUX(CLK_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p, MUX_SEL_DISP0,
2580 MUX(CLK_MOUT_SCLK_DSIM1_USER, "mout_sclk_dsim1_user",
2581 mout_sclk_dsim1_user_p, MUX_SEL_DISP1, 28, 1),
2582 MUX(CLK_MOUT_SCLK_DSIM0_USER, "mout_sclk_dsim0_user",
2583 mout_sclk_dsim0_user_p, MUX_SEL_DISP1, 24, 1),
2584 MUX(CLK_MOUT_SCLK_DSD_USER, "mout_sclk_dsd_user", mout_sclk_dsd_user_p,
2585 MUX_SEL_DISP1, 20, 1),
2586 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_USER, "mout_sclk_decon_tv_eclk_user",
2587 mout_sclk_decon_tv_eclk_user_p, MUX_SEL_DISP1, 16, 1),
2588 MUX(CLK_MOUT_SCLK_DECON_VCLK_USER, "mout_sclk_decon_vclk_user",
2589 mout_sclk_decon_vclk_user_p, MUX_SEL_DISP1, 12, 1),
2590 MUX(CLK_MOUT_SCLK_DECON_ECLK_USER, "mout_sclk_decon_eclk_user",
2591 mout_sclk_decon_eclk_user_p, MUX_SEL_DISP1, 8, 1),
2592 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_USER, "mout_sclk_decon_tv_vclk_user",
2593 mout_sclk_decon_tv_vlkc_user_p, MUX_SEL_DISP1, 4, 1),
2594 MUX(CLK_MOUT_ACLK_DISP_333_USER, "mout_aclk_disp_333_user",
2595 mout_aclk_disp_333_user_p, MUX_SEL_DISP1, 0, 1),
2598 MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER,
2599 "mout_phyclk_mipidphy1_bitclkdiv8_user",
2600 mout_phyclk_mipidphy1_bitclkdiv8_user_p, MUX_SEL_DISP2,
2602 MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER,
2603 "mout_phyclk_mipidphy1_rxclkesc0_user",
2604 mout_phyclk_mipidphy1_rxclkesc0_user_p, MUX_SEL_DISP2,
2606 MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER,
2607 "mout_phyclk_mipidphy0_bitclkdiv8_user",
2608 mout_phyclk_mipidphy0_bitclkdiv8_user_p, MUX_SEL_DISP2,
2610 MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER,
2611 "mout_phyclk_mipidphy0_rxclkesc0_user",
2612 mout_phyclk_mipidphy0_rxclkesc0_user_p, MUX_SEL_DISP2,
2614 MUX(CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER,
2615 "mout_phyclk_hdmiphy_tmds_clko_user",
2616 mout_phyclk_hdmiphy_tmds_clko_user_p, MUX_SEL_DISP2,
2618 MUX(CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER,
2619 "mout_phyclk_hdmiphy_pixel_clko_user",
2620 mout_phyclk_hdmiphy_pixel_clko_user_p, MUX_SEL_DISP2,
2624 MUX(CLK_MOUT_SCLK_DSIM0, "mout_sclk_dsim0", mout_sclk_dsim0_p,
2625 MUX_SEL_DISP3, 12, 1),
2626 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK, "mout_sclk_decon_tv_eclk",
2627 mout_sclk_decon_tv_eclk_p, MUX_SEL_DISP3, 8, 1),
2628 MUX(CLK_MOUT_SCLK_DECON_VCLK, "mout_sclk_decon_vclk",
2629 mout_sclk_decon_vclk_p, MUX_SEL_DISP3, 4, 1),
2630 MUX(CLK_MOUT_SCLK_DECON_ECLK, "mout_sclk_decon_eclk",
2631 mout_sclk_decon_eclk_p, MUX_SEL_DISP3, 0, 1),
2634 MUX(CLK_MOUT_SCLK_DSIM1_B_DISP, "mout_sclk_dsim1_b_disp",
2635 mout_sclk_dsim1_b_disp_p, MUX_SEL_DISP4, 16, 1),
2636 MUX(CLK_MOUT_SCLK_DSIM1_A_DISP, "mout_sclk_dsim1_a_disp",
2637 mout_sclk_dsim0_p, MUX_SEL_DISP4, 12, 1),
2638 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP,
2639 "mout_sclk_decon_tv_vclk_c_disp",
2640 mout_sclk_decon_tv_vclk_c_disp_p, MUX_SEL_DISP4, 8, 1),
2641 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP,
2642 "mout_sclk_decon_tv_vclk_b_disp",
2643 mout_sclk_decon_tv_vclk_b_disp_p, MUX_SEL_DISP4, 4, 1),
2644 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP,
2645 "mout_sclk_decon_tv_vclk_a_disp",
2646 mout_sclk_decon_vclk_p, MUX_SEL_DISP4, 0, 1),
2649 static const struct samsung_div_clock disp_div_clks[] __initconst = {
2651 DIV(CLK_DIV_SCLK_DSIM1_DISP, "div_sclk_dsim1_disp",
2652 "mout_sclk_dsim1_b_disp", DIV_DISP, 24, 3),
2653 DIV(CLK_DIV_SCLK_DECON_TV_VCLK_DISP, "div_sclk_decon_tv_vclk_disp",
2654 "mout_sclk_decon_tv_vclk_c_disp", DIV_DISP, 20, 3),
2655 DIV(CLK_DIV_SCLK_DSIM0_DISP, "div_sclk_dsim0_disp", "mout_sclk_dsim0",
2657 DIV(CLK_DIV_SCLK_DECON_TV_ECLK_DISP, "div_sclk_decon_tv_eclk_disp",
2658 "mout_sclk_decon_tv_eclk", DIV_DISP, 12, 3),
2659 DIV(CLK_DIV_SCLK_DECON_VCLK_DISP, "div_sclk_decon_vclk_disp",
2660 "mout_sclk_decon_vclk", DIV_DISP, 8, 3),
2661 DIV(CLK_DIV_SCLK_DECON_ECLK_DISP, "div_sclk_decon_eclk_disp",
2662 "mout_sclk_decon_eclk", DIV_DISP, 4, 3),
2663 DIV(CLK_DIV_PCLK_DISP, "div_pclk_disp", "mout_aclk_disp_333_user",
2667 static const struct samsung_gate_clock disp_gate_clks[] __initconst = {
2668 /* ENABLE_ACLK_DISP0 */
2669 GATE(CLK_ACLK_DECON_TV, "aclk_decon_tv", "mout_aclk_disp_333_user",
2670 ENABLE_ACLK_DISP0, 2, 0, 0),
2671 GATE(CLK_ACLK_DECON, "aclk_decon", "mout_aclk_disp_333_user",
2672 ENABLE_ACLK_DISP0, 0, 0, 0),
2674 /* ENABLE_ACLK_DISP1 */
2675 GATE(CLK_ACLK_SMMU_TV1X, "aclk_smmu_tv1x", "mout_aclk_disp_333_user",
2676 ENABLE_ACLK_DISP1, 25, 0, 0),
2677 GATE(CLK_ACLK_SMMU_TV0X, "aclk_smmu_tv0x", "mout_aclk_disp_333_user",
2678 ENABLE_ACLK_DISP1, 24, 0, 0),
2679 GATE(CLK_ACLK_SMMU_DECON1X, "aclk_smmu_decon1x",
2680 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 23, 0, 0),
2681 GATE(CLK_ACLK_SMMU_DECON0X, "aclk_smmu_decon0x",
2682 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 22, 0, 0),
2683 GATE(CLK_ACLK_BTS_DECON_TV_M3, "aclk_bts_decon_tv_m3",
2684 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 21, 0, 0),
2685 GATE(CLK_ACLK_BTS_DECON_TV_M2, "aclk_bts_decon_tv_m2",
2686 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 20, 0, 0),
2687 GATE(CLK_ACLK_BTS_DECON_TV_M1, "aclk_bts_decon_tv_m1",
2688 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 19, 0, 0),
2689 GATE(CLK_ACLK_BTS_DECON_TV_M0, "aclk-bts_decon_tv_m0",
2690 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 18, 0, 0),
2691 GATE(CLK_ACLK_BTS_DECON_NM4, "aclk_bts_decon_nm4",
2692 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 17, 0, 0),
2693 GATE(CLK_ACLK_BTS_DECON_NM3, "aclk_bts_decon_nm3",
2694 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 16, 0, 0),
2695 GATE(CLK_ACLK_BTS_DECON_NM2, "aclk_bts_decon_nm2",
2696 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 15, 0, 0),
2697 GATE(CLK_ACLK_BTS_DECON_NM1, "aclk_bts_decon_nm1",
2698 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 14, 0, 0),
2699 GATE(CLK_ACLK_BTS_DECON_NM0, "aclk_bts_decon_nm0",
2700 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 13, 0, 0),
2701 GATE(CLK_ACLK_AHB2APB_DISPSFR2P, "aclk_ahb2apb_dispsfr2p",
2702 "div_pclk_disp", ENABLE_ACLK_DISP1,
2703 12, CLK_IGNORE_UNUSED, 0),
2704 GATE(CLK_ACLK_AHB2APB_DISPSFR1P, "aclk_ahb2apb_dispsfr1p",
2705 "div_pclk_disp", ENABLE_ACLK_DISP1,
2706 11, CLK_IGNORE_UNUSED, 0),
2707 GATE(CLK_ACLK_AHB2APB_DISPSFR0P, "aclk_ahb2apb_dispsfr0p",
2708 "div_pclk_disp", ENABLE_ACLK_DISP1,
2709 10, CLK_IGNORE_UNUSED, 0),
2710 GATE(CLK_ACLK_AHB_DISPH, "aclk_ahb_disph", "div_pclk_disp",
2711 ENABLE_ACLK_DISP1, 8, CLK_IGNORE_UNUSED, 0),
2712 GATE(CLK_ACLK_XIU_TV1X, "aclk_xiu_tv1x", "mout_aclk_disp_333_user",
2713 ENABLE_ACLK_DISP1, 7, 0, 0),
2714 GATE(CLK_ACLK_XIU_TV0X, "aclk_xiu_tv0x", "mout_aclk_disp_333_user",
2715 ENABLE_ACLK_DISP1, 6, 0, 0),
2716 GATE(CLK_ACLK_XIU_DECON1X, "aclk_xiu_decon1x",
2717 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 5, 0, 0),
2718 GATE(CLK_ACLK_XIU_DECON0X, "aclk_xiu_decon0x",
2719 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 4, 0, 0),
2720 GATE(CLK_ACLK_XIU_DISP1X, "aclk_xiu_disp1x", "mout_aclk_disp_333_user",
2721 ENABLE_ACLK_DISP1, 3, CLK_IGNORE_UNUSED, 0),
2722 GATE(CLK_ACLK_XIU_DISPNP_100, "aclk_xiu_dispnp_100", "div_pclk_disp",
2723 ENABLE_ACLK_DISP1, 2, CLK_IGNORE_UNUSED, 0),
2724 GATE(CLK_ACLK_DISP1ND_333, "aclk_disp1nd_333",
2725 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 1,
2726 CLK_IGNORE_UNUSED, 0),
2727 GATE(CLK_ACLK_DISP0ND_333, "aclk_disp0nd_333",
2728 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1,
2729 0, CLK_IGNORE_UNUSED, 0),
2731 /* ENABLE_PCLK_DISP */
2732 GATE(CLK_PCLK_SMMU_TV1X, "pclk_smmu_tv1x", "div_pclk_disp",
2733 ENABLE_PCLK_DISP, 23, 0, 0),
2734 GATE(CLK_PCLK_SMMU_TV0X, "pclk_smmu_tv0x", "div_pclk_disp",
2735 ENABLE_PCLK_DISP, 22, 0, 0),
2736 GATE(CLK_PCLK_SMMU_DECON1X, "pclk_smmu_decon1x", "div_pclk_disp",
2737 ENABLE_PCLK_DISP, 21, 0, 0),
2738 GATE(CLK_PCLK_SMMU_DECON0X, "pclk_smmu_decon0x", "div_pclk_disp",
2739 ENABLE_PCLK_DISP, 20, 0, 0),
2740 GATE(CLK_PCLK_BTS_DECON_TV_M3, "pclk_bts_decon_tv_m3", "div_pclk_disp",
2741 ENABLE_PCLK_DISP, 19, 0, 0),
2742 GATE(CLK_PCLK_BTS_DECON_TV_M2, "pclk_bts_decon_tv_m2", "div_pclk_disp",
2743 ENABLE_PCLK_DISP, 18, 0, 0),
2744 GATE(CLK_PCLK_BTS_DECON_TV_M1, "pclk_bts_decon_tv_m1", "div_pclk_disp",
2745 ENABLE_PCLK_DISP, 17, 0, 0),
2746 GATE(CLK_PCLK_BTS_DECON_TV_M0, "pclk_bts_decon_tv_m0", "div_pclk_disp",
2747 ENABLE_PCLK_DISP, 16, 0, 0),
2748 GATE(CLK_PCLK_BTS_DECONM4, "pclk_bts_deconm4", "div_pclk_disp",
2749 ENABLE_PCLK_DISP, 15, 0, 0),
2750 GATE(CLK_PCLK_BTS_DECONM3, "pclk_bts_deconm3", "div_pclk_disp",
2751 ENABLE_PCLK_DISP, 14, 0, 0),
2752 GATE(CLK_PCLK_BTS_DECONM2, "pclk_bts_deconm2", "div_pclk_disp",
2753 ENABLE_PCLK_DISP, 13, 0, 0),
2754 GATE(CLK_PCLK_BTS_DECONM1, "pclk_bts_deconm1", "div_pclk_disp",
2755 ENABLE_PCLK_DISP, 12, 0, 0),
2756 GATE(CLK_PCLK_BTS_DECONM0, "pclk_bts_deconm0", "div_pclk_disp",
2757 ENABLE_PCLK_DISP, 11, 0, 0),
2758 GATE(CLK_PCLK_MIC1, "pclk_mic1", "div_pclk_disp",
2759 ENABLE_PCLK_DISP, 10, 0, 0),
2760 GATE(CLK_PCLK_PMU_DISP, "pclk_pmu_disp", "div_pclk_disp",
2761 ENABLE_PCLK_DISP, 9, CLK_IGNORE_UNUSED, 0),
2762 GATE(CLK_PCLK_SYSREG_DISP, "pclk_sysreg_disp", "div_pclk_disp",
2763 ENABLE_PCLK_DISP, 8, CLK_IGNORE_UNUSED, 0),
2764 GATE(CLK_PCLK_HDMIPHY, "pclk_hdmiphy", "div_pclk_disp",
2765 ENABLE_PCLK_DISP, 7, 0, 0),
2766 GATE(CLK_PCLK_HDMI, "pclk_hdmi", "div_pclk_disp",
2767 ENABLE_PCLK_DISP, 6, 0, 0),
2768 GATE(CLK_PCLK_MIC0, "pclk_mic0", "div_pclk_disp",
2769 ENABLE_PCLK_DISP, 5, 0, 0),
2770 GATE(CLK_PCLK_DSIM1, "pclk_dsim1", "div_pclk_disp",
2771 ENABLE_PCLK_DISP, 3, 0, 0),
2772 GATE(CLK_PCLK_DSIM0, "pclk_dsim0", "div_pclk_disp",
2773 ENABLE_PCLK_DISP, 2, 0, 0),
2774 GATE(CLK_PCLK_DECON_TV, "pclk_decon_tv", "div_pclk_disp",
2775 ENABLE_PCLK_DISP, 1, 0, 0),
2776 GATE(CLK_PCLK_DECON, "pclk_decon", "div_pclk_disp",
2777 ENABLE_PCLK_DISP, 0, 0, 0),
2779 /* ENABLE_SCLK_DISP */
2780 GATE(CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8, "phyclk_mipidphy1_bitclkdiv8",
2781 "mout_phyclk_mipidphy1_bitclkdiv8_user",
2782 ENABLE_SCLK_DISP, 26, 0, 0),
2783 GATE(CLK_PHYCLK_MIPIDPHY1_RXCLKESC0, "phyclk_mipidphy1_rxclkesc0",
2784 "mout_phyclk_mipidphy1_rxclkesc0_user",
2785 ENABLE_SCLK_DISP, 25, 0, 0),
2786 GATE(CLK_SCLK_RGB_TV_VCLK_TO_DSIM1, "sclk_rgb_tv_vclk_to_dsim1",
2787 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 24, 0, 0),
2788 GATE(CLK_SCLK_RGB_TV_VCLK_TO_MIC1, "sclk_rgb_tv_vclk_to_mic1",
2789 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 23, 0, 0),
2790 GATE(CLK_SCLK_DSIM1, "sclk_dsim1", "div_sclk_dsim1_disp",
2791 ENABLE_SCLK_DISP, 22, 0, 0),
2792 GATE(CLK_SCLK_DECON_TV_VCLK, "sclk_decon_tv_vclk",
2793 "div_sclk_decon_tv_vclk_disp",
2794 ENABLE_SCLK_DISP, 21, 0, 0),
2795 GATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8, "phyclk_mipidphy0_bitclkdiv8",
2796 "mout_phyclk_mipidphy0_bitclkdiv8_user",
2797 ENABLE_SCLK_DISP, 15, 0, 0),
2798 GATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0, "phyclk_mipidphy0_rxclkesc0",
2799 "mout_phyclk_mipidphy0_rxclkesc0_user",
2800 ENABLE_SCLK_DISP, 14, 0, 0),
2801 GATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO, "phyclk_hdmiphy_tmds_clko",
2802 "mout_phyclk_hdmiphy_tmds_clko_user",
2803 ENABLE_SCLK_DISP, 13, 0, 0),
2804 GATE(CLK_PHYCLK_HDMI_PIXEL, "phyclk_hdmi_pixel",
2805 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 12, 0, 0),
2806 GATE(CLK_SCLK_RGB_VCLK_TO_SMIES, "sclk_rgb_vclk_to_smies",
2807 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 11, 0, 0),
2808 GATE(CLK_SCLK_RGB_VCLK_TO_DSIM0, "sclk_rgb_vclk_to_dsim0",
2809 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 9, 0, 0),
2810 GATE(CLK_SCLK_RGB_VCLK_TO_MIC0, "sclk_rgb_vclk_to_mic0",
2811 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 8, 0, 0),
2812 GATE(CLK_SCLK_DSD, "sclk_dsd", "mout_sclk_dsd_user",
2813 ENABLE_SCLK_DISP, 7, 0, 0),
2814 GATE(CLK_SCLK_HDMI_SPDIF, "sclk_hdmi_spdif", "sclk_hdmi_spdif_disp",
2815 ENABLE_SCLK_DISP, 6, 0, 0),
2816 GATE(CLK_SCLK_DSIM0, "sclk_dsim0", "div_sclk_dsim0_disp",
2817 ENABLE_SCLK_DISP, 5, 0, 0),
2818 GATE(CLK_SCLK_DECON_TV_ECLK, "sclk_decon_tv_eclk",
2819 "div_sclk_decon_tv_eclk_disp",
2820 ENABLE_SCLK_DISP, 4, 0, 0),
2821 GATE(CLK_SCLK_DECON_VCLK, "sclk_decon_vclk",
2822 "div_sclk_decon_vclk_disp", ENABLE_SCLK_DISP, 3, 0, 0),
2823 GATE(CLK_SCLK_DECON_ECLK, "sclk_decon_eclk",
2824 "div_sclk_decon_eclk_disp", ENABLE_SCLK_DISP, 2, 0, 0),
2827 static const struct samsung_cmu_info disp_cmu_info __initconst = {
2828 .pll_clks = disp_pll_clks,
2829 .nr_pll_clks = ARRAY_SIZE(disp_pll_clks),
2830 .mux_clks = disp_mux_clks,
2831 .nr_mux_clks = ARRAY_SIZE(disp_mux_clks),
2832 .div_clks = disp_div_clks,
2833 .nr_div_clks = ARRAY_SIZE(disp_div_clks),
2834 .gate_clks = disp_gate_clks,
2835 .nr_gate_clks = ARRAY_SIZE(disp_gate_clks),
2836 .fixed_clks = disp_fixed_clks,
2837 .nr_fixed_clks = ARRAY_SIZE(disp_fixed_clks),
2838 .fixed_factor_clks = disp_fixed_factor_clks,
2839 .nr_fixed_factor_clks = ARRAY_SIZE(disp_fixed_factor_clks),
2840 .nr_clk_ids = DISP_NR_CLK,
2841 .clk_regs = disp_clk_regs,
2842 .nr_clk_regs = ARRAY_SIZE(disp_clk_regs),
2845 static void __init exynos5433_cmu_disp_init(struct device_node *np)
2847 samsung_cmu_register_one(np, &disp_cmu_info);
2850 CLK_OF_DECLARE(exynos5433_cmu_disp, "samsung,exynos5433-cmu-disp",
2851 exynos5433_cmu_disp_init);
2854 * Register offset definitions for CMU_AUD
2856 #define MUX_SEL_AUD0 0x0200
2857 #define MUX_SEL_AUD1 0x0204
2858 #define MUX_ENABLE_AUD0 0x0300
2859 #define MUX_ENABLE_AUD1 0x0304
2860 #define MUX_STAT_AUD0 0x0400
2861 #define DIV_AUD0 0x0600
2862 #define DIV_AUD1 0x0604
2863 #define DIV_STAT_AUD0 0x0700
2864 #define DIV_STAT_AUD1 0x0704
2865 #define ENABLE_ACLK_AUD 0x0800
2866 #define ENABLE_PCLK_AUD 0x0900
2867 #define ENABLE_SCLK_AUD0 0x0a00
2868 #define ENABLE_SCLK_AUD1 0x0a04
2869 #define ENABLE_IP_AUD0 0x0b00
2870 #define ENABLE_IP_AUD1 0x0b04
2872 static const unsigned long aud_clk_regs[] __initconst = {
2887 /* list of all parent clock list */
2888 PNAME(mout_aud_pll_user_aud_p) = { "oscclk", "fout_aud_pll", };
2889 PNAME(mout_sclk_aud_pcm_p) = { "mout_aud_pll_user", "ioclk_audiocdclk0",};
2891 static const struct samsung_fixed_rate_clock aud_fixed_clks[] __initconst = {
2892 FRATE(0, "ioclk_jtag_tclk", NULL, 0, 33000000),
2893 FRATE(0, "ioclk_slimbus_clk", NULL, 0, 25000000),
2894 FRATE(0, "ioclk_i2s_bclk", NULL, 0, 50000000),
2897 static const struct samsung_mux_clock aud_mux_clks[] __initconst = {
2899 MUX(CLK_MOUT_AUD_PLL_USER, "mout_aud_pll_user",
2900 mout_aud_pll_user_aud_p, MUX_SEL_AUD0, 0, 1),
2903 MUX(CLK_MOUT_SCLK_AUD_PCM, "mout_sclk_aud_pcm", mout_sclk_aud_pcm_p,
2904 MUX_SEL_AUD1, 8, 1),
2905 MUX(CLK_MOUT_SCLK_AUD_I2S, "mout_sclk_aud_i2s", mout_sclk_aud_pcm_p,
2906 MUX_SEL_AUD1, 0, 1),
2909 static const struct samsung_div_clock aud_div_clks[] __initconst = {
2911 DIV(CLK_DIV_ATCLK_AUD, "div_atclk_aud", "div_aud_ca5", DIV_AUD0,
2913 DIV(CLK_DIV_PCLK_DBG_AUD, "div_pclk_dbg_aud", "div_aud_ca5", DIV_AUD0,
2915 DIV(CLK_DIV_ACLK_AUD, "div_aclk_aud", "div_aud_ca5", DIV_AUD0,
2917 DIV(CLK_DIV_AUD_CA5, "div_aud_ca5", "mout_aud_pll_user", DIV_AUD0,
2921 DIV(CLK_DIV_SCLK_AUD_SLIMBUS, "div_sclk_aud_slimbus",
2922 "mout_aud_pll_user", DIV_AUD1, 16, 5),
2923 DIV(CLK_DIV_SCLK_AUD_UART, "div_sclk_aud_uart", "mout_aud_pll_user",
2925 DIV(CLK_DIV_SCLK_AUD_PCM, "div_sclk_aud_pcm", "mout_sclk_aud_pcm",
2927 DIV(CLK_DIV_SCLK_AUD_I2S, "div_sclk_aud_i2s", "mout_sclk_aud_i2s",
2931 static const struct samsung_gate_clock aud_gate_clks[] __initconst = {
2932 /* ENABLE_ACLK_AUD */
2933 GATE(CLK_ACLK_INTR_CTRL, "aclk_intr_ctrl", "div_aclk_aud",
2934 ENABLE_ACLK_AUD, 12, 0, 0),
2935 GATE(CLK_ACLK_SMMU_LPASSX, "aclk_smmu_lpassx", "div_aclk_aud",
2936 ENABLE_ACLK_AUD, 7, 0, 0),
2937 GATE(CLK_ACLK_XIU_LPASSX, "aclk_xiu_lpassx", "div_aclk_aud",
2938 ENABLE_ACLK_AUD, 0, 4, 0),
2939 GATE(CLK_ACLK_AUDNP_133, "aclk_audnp_133", "div_aclk_aud",
2940 ENABLE_ACLK_AUD, 0, 3, 0),
2941 GATE(CLK_ACLK_AUDND_133, "aclk_audnd_133", "div_aclk_aud",
2942 ENABLE_ACLK_AUD, 0, 2, 0),
2943 GATE(CLK_ACLK_SRAMC, "aclk_sramc", "div_aclk_aud", ENABLE_ACLK_AUD,
2945 GATE(CLK_ACLK_DMAC, "aclk_dmac", "div_aclk_aud", ENABLE_ACLK_AUD,
2946 0, CLK_IGNORE_UNUSED, 0),
2948 /* ENABLE_PCLK_AUD */
2949 GATE(CLK_PCLK_WDT1, "pclk_wdt1", "div_aclk_aud", ENABLE_PCLK_AUD,
2951 GATE(CLK_PCLK_WDT0, "pclk_wdt0", "div_aclk_aud", ENABLE_PCLK_AUD,
2953 GATE(CLK_PCLK_SFR1, "pclk_sfr1", "div_aclk_aud", ENABLE_PCLK_AUD,
2955 GATE(CLK_PCLK_SMMU_LPASSX, "pclk_smmu_lpassx", "div_aclk_aud",
2956 ENABLE_PCLK_AUD, 10, 0, 0),
2957 GATE(CLK_PCLK_GPIO_AUD, "pclk_gpio_aud", "div_aclk_aud",
2958 ENABLE_PCLK_AUD, 9, CLK_IGNORE_UNUSED, 0),
2959 GATE(CLK_PCLK_PMU_AUD, "pclk_pmu_aud", "div_aclk_aud",
2960 ENABLE_PCLK_AUD, 8, CLK_IGNORE_UNUSED, 0),
2961 GATE(CLK_PCLK_SYSREG_AUD, "pclk_sysreg_aud", "div_aclk_aud",
2962 ENABLE_PCLK_AUD, 7, CLK_IGNORE_UNUSED, 0),
2963 GATE(CLK_PCLK_AUD_SLIMBUS, "pclk_aud_slimbus", "div_aclk_aud",
2964 ENABLE_PCLK_AUD, 6, 0, 0),
2965 GATE(CLK_PCLK_AUD_UART, "pclk_aud_uart", "div_aclk_aud",
2966 ENABLE_PCLK_AUD, 5, 0, 0),
2967 GATE(CLK_PCLK_AUD_PCM, "pclk_aud_pcm", "div_aclk_aud",
2968 ENABLE_PCLK_AUD, 4, 0, 0),
2969 GATE(CLK_PCLK_AUD_I2S, "pclk_aud_i2s", "div_aclk_aud",
2970 ENABLE_PCLK_AUD, 3, 0, 0),
2971 GATE(CLK_PCLK_TIMER, "pclk_timer", "div_aclk_aud", ENABLE_PCLK_AUD,
2973 GATE(CLK_PCLK_SFR0_CTRL, "pclk_sfr0_ctrl", "div_aclk_aud",
2974 ENABLE_PCLK_AUD, 0, 0, 0),
2976 /* ENABLE_SCLK_AUD0 */
2977 GATE(CLK_ATCLK_AUD, "atclk_aud", "div_atclk_aud", ENABLE_SCLK_AUD0,
2978 2, CLK_IGNORE_UNUSED, 0),
2979 GATE(CLK_PCLK_DBG_AUD, "pclk_dbg_aud", "div_pclk_dbg_aud",
2980 ENABLE_SCLK_AUD0, 1, 0, 0),
2981 GATE(CLK_SCLK_AUD_CA5, "sclk_aud_ca5", "div_aud_ca5", ENABLE_SCLK_AUD0,
2984 /* ENABLE_SCLK_AUD1 */
2985 GATE(CLK_SCLK_JTAG_TCK, "sclk_jtag_tck", "ioclk_jtag_tclk",
2986 ENABLE_SCLK_AUD1, 6, 0, 0),
2987 GATE(CLK_SCLK_SLIMBUS_CLKIN, "sclk_slimbus_clkin", "ioclk_slimbus_clk",
2988 ENABLE_SCLK_AUD1, 5, 0, 0),
2989 GATE(CLK_SCLK_AUD_SLIMBUS, "sclk_aud_slimbus", "div_sclk_aud_slimbus",
2990 ENABLE_SCLK_AUD1, 4, 0, 0),
2991 GATE(CLK_SCLK_AUD_UART, "sclk_aud_uart", "div_sclk_aud_uart",
2992 ENABLE_SCLK_AUD1, 3, CLK_IGNORE_UNUSED, 0),
2993 GATE(CLK_SCLK_AUD_PCM, "sclk_aud_pcm", "div_sclk_aud_pcm",
2994 ENABLE_SCLK_AUD1, 2, 0, 0),
2995 GATE(CLK_SCLK_I2S_BCLK, "sclk_i2s_bclk", "ioclk_i2s_bclk",
2996 ENABLE_SCLK_AUD1, 1, CLK_IGNORE_UNUSED, 0),
2997 GATE(CLK_SCLK_AUD_I2S, "sclk_aud_i2s", "div_sclk_aud_i2s",
2998 ENABLE_SCLK_AUD1, 0, CLK_IGNORE_UNUSED, 0),
3001 static const struct samsung_cmu_info aud_cmu_info __initconst = {
3002 .mux_clks = aud_mux_clks,
3003 .nr_mux_clks = ARRAY_SIZE(aud_mux_clks),
3004 .div_clks = aud_div_clks,
3005 .nr_div_clks = ARRAY_SIZE(aud_div_clks),
3006 .gate_clks = aud_gate_clks,
3007 .nr_gate_clks = ARRAY_SIZE(aud_gate_clks),
3008 .fixed_clks = aud_fixed_clks,
3009 .nr_fixed_clks = ARRAY_SIZE(aud_fixed_clks),
3010 .nr_clk_ids = AUD_NR_CLK,
3011 .clk_regs = aud_clk_regs,
3012 .nr_clk_regs = ARRAY_SIZE(aud_clk_regs),
3015 static void __init exynos5433_cmu_aud_init(struct device_node *np)
3017 samsung_cmu_register_one(np, &aud_cmu_info);
3019 CLK_OF_DECLARE(exynos5433_cmu_aud, "samsung,exynos5433-cmu-aud",
3020 exynos5433_cmu_aud_init);
3024 * Register offset definitions for CMU_BUS{0|1|2}
3026 #define DIV_BUS 0x0600
3027 #define DIV_STAT_BUS 0x0700
3028 #define ENABLE_ACLK_BUS 0x0800
3029 #define ENABLE_PCLK_BUS 0x0900
3030 #define ENABLE_IP_BUS0 0x0b00
3031 #define ENABLE_IP_BUS1 0x0b04
3033 #define MUX_SEL_BUS2 0x0200 /* Only for CMU_BUS2 */
3034 #define MUX_ENABLE_BUS2 0x0300 /* Only for CMU_BUS2 */
3035 #define MUX_STAT_BUS2 0x0400 /* Only for CMU_BUS2 */
3037 /* list of all parent clock list */
3038 PNAME(mout_aclk_bus2_400_p) = { "oscclk", "aclk_bus2_400", };
3040 #define CMU_BUS_COMMON_CLK_REGS \
3047 static const unsigned long bus01_clk_regs[] __initconst = {
3048 CMU_BUS_COMMON_CLK_REGS,
3051 static const unsigned long bus2_clk_regs[] __initconst = {
3054 CMU_BUS_COMMON_CLK_REGS,
3057 static const struct samsung_div_clock bus0_div_clks[] __initconst = {
3059 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus0_133", "aclk_bus0_400",
3063 /* CMU_BUS0 clocks */
3064 static const struct samsung_gate_clock bus0_gate_clks[] __initconst = {
3065 /* ENABLE_ACLK_BUS0 */
3066 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus0p", "div_pclk_bus0_133",
3067 ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0),
3068 GATE(CLK_ACLK_BUSNP_133, "aclk_bus0np_133", "div_pclk_bus0_133",
3069 ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
3070 GATE(CLK_ACLK_BUSND_400, "aclk_bus0nd_400", "aclk_bus0_400",
3071 ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3073 /* ENABLE_PCLK_BUS0 */
3074 GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus0srvnd_133", "div_pclk_bus0_133",
3075 ENABLE_PCLK_BUS, 2, 0, 0),
3076 GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus0", "div_pclk_bus0_133",
3077 ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
3078 GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus0", "div_pclk_bus0_133",
3079 ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3082 /* CMU_BUS1 clocks */
3083 static const struct samsung_div_clock bus1_div_clks[] __initconst = {
3085 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus1_133", "aclk_bus1_400",
3089 static const struct samsung_gate_clock bus1_gate_clks[] __initconst = {
3090 /* ENABLE_ACLK_BUS1 */
3091 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus1p", "div_pclk_bus1_133",
3092 ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0),
3093 GATE(CLK_ACLK_BUSNP_133, "aclk_bus1np_133", "div_pclk_bus1_133",
3094 ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
3095 GATE(CLK_ACLK_BUSND_400, "aclk_bus1nd_400", "aclk_bus1_400",
3096 ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3098 /* ENABLE_PCLK_BUS1 */
3099 GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus1srvnd_133", "div_pclk_bus1_133",
3100 ENABLE_PCLK_BUS, 2, 0, 0),
3101 GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus1", "div_pclk_bus1_133",
3102 ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
3103 GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus1", "div_pclk_bus1_133",
3104 ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3107 /* CMU_BUS2 clocks */
3108 static const struct samsung_mux_clock bus2_mux_clks[] __initconst = {
3110 MUX(CLK_MOUT_ACLK_BUS2_400_USER, "mout_aclk_bus2_400_user",
3111 mout_aclk_bus2_400_p, MUX_SEL_BUS2, 0, 1),
3114 static const struct samsung_div_clock bus2_div_clks[] __initconst = {
3116 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus2_133",
3117 "mout_aclk_bus2_400_user", DIV_BUS, 0, 3),
3120 static const struct samsung_gate_clock bus2_gate_clks[] __initconst = {
3121 /* ENABLE_ACLK_BUS2 */
3122 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus2p", "div_pclk_bus2_133",
3123 ENABLE_ACLK_BUS, 3, CLK_IGNORE_UNUSED, 0),
3124 GATE(CLK_ACLK_BUSNP_133, "aclk_bus2np_133", "div_pclk_bus2_133",
3125 ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
3126 GATE(CLK_ACLK_BUS2BEND_400, "aclk_bus2bend_400",
3127 "mout_aclk_bus2_400_user", ENABLE_ACLK_BUS,
3128 1, CLK_IGNORE_UNUSED, 0),
3129 GATE(CLK_ACLK_BUS2RTND_400, "aclk_bus2rtnd_400",
3130 "mout_aclk_bus2_400_user", ENABLE_ACLK_BUS,
3131 0, CLK_IGNORE_UNUSED, 0),
3133 /* ENABLE_PCLK_BUS2 */
3134 GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus2srvnd_133", "div_pclk_bus2_133",
3135 ENABLE_PCLK_BUS, 2, 0, 0),
3136 GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus2", "div_pclk_bus2_133",
3137 ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
3138 GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus2", "div_pclk_bus2_133",
3139 ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3142 #define CMU_BUS_INFO_CLKS(id) \
3143 .div_clks = bus##id##_div_clks, \
3144 .nr_div_clks = ARRAY_SIZE(bus##id##_div_clks), \
3145 .gate_clks = bus##id##_gate_clks, \
3146 .nr_gate_clks = ARRAY_SIZE(bus##id##_gate_clks), \
3147 .nr_clk_ids = BUSx_NR_CLK
3149 static const struct samsung_cmu_info bus0_cmu_info __initconst = {
3150 CMU_BUS_INFO_CLKS(0),
3151 .clk_regs = bus01_clk_regs,
3152 .nr_clk_regs = ARRAY_SIZE(bus01_clk_regs),
3155 static const struct samsung_cmu_info bus1_cmu_info __initconst = {
3156 CMU_BUS_INFO_CLKS(1),
3157 .clk_regs = bus01_clk_regs,
3158 .nr_clk_regs = ARRAY_SIZE(bus01_clk_regs),
3161 static const struct samsung_cmu_info bus2_cmu_info __initconst = {
3162 CMU_BUS_INFO_CLKS(2),
3163 .mux_clks = bus2_mux_clks,
3164 .nr_mux_clks = ARRAY_SIZE(bus2_mux_clks),
3165 .clk_regs = bus2_clk_regs,
3166 .nr_clk_regs = ARRAY_SIZE(bus2_clk_regs),
3169 #define exynos5433_cmu_bus_init(id) \
3170 static void __init exynos5433_cmu_bus##id##_init(struct device_node *np)\
3172 samsung_cmu_register_one(np, &bus##id##_cmu_info); \
3174 CLK_OF_DECLARE(exynos5433_cmu_bus##id, \
3175 "samsung,exynos5433-cmu-bus"#id, \
3176 exynos5433_cmu_bus##id##_init)
3178 exynos5433_cmu_bus_init(0);
3179 exynos5433_cmu_bus_init(1);
3180 exynos5433_cmu_bus_init(2);
3183 * Register offset definitions for CMU_G3D
3185 #define G3D_PLL_LOCK 0x0000
3186 #define G3D_PLL_CON0 0x0100
3187 #define G3D_PLL_CON1 0x0104
3188 #define G3D_PLL_FREQ_DET 0x010c
3189 #define MUX_SEL_G3D 0x0200
3190 #define MUX_ENABLE_G3D 0x0300
3191 #define MUX_STAT_G3D 0x0400
3192 #define DIV_G3D 0x0600
3193 #define DIV_G3D_PLL_FREQ_DET 0x0604
3194 #define DIV_STAT_G3D 0x0700
3195 #define DIV_STAT_G3D_PLL_FREQ_DET 0x0704
3196 #define ENABLE_ACLK_G3D 0x0800
3197 #define ENABLE_PCLK_G3D 0x0900
3198 #define ENABLE_SCLK_G3D 0x0a00
3199 #define ENABLE_IP_G3D0 0x0b00
3200 #define ENABLE_IP_G3D1 0x0b04
3201 #define CLKOUT_CMU_G3D 0x0c00
3202 #define CLKOUT_CMU_G3D_DIV_STAT 0x0c04
3203 #define CLK_STOPCTRL 0x1000
3205 static const unsigned long g3d_clk_regs[] __initconst = {
3213 DIV_G3D_PLL_FREQ_DET,
3220 CLKOUT_CMU_G3D_DIV_STAT,
3224 /* list of all parent clock list */
3225 PNAME(mout_aclk_g3d_400_p) = { "mout_g3d_pll", "aclk_g3d_400", };
3226 PNAME(mout_g3d_pll_p) = { "oscclk", "fout_g3d_pll", };
3228 static const struct samsung_pll_clock g3d_pll_clks[] __initconst = {
3229 PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk",
3230 G3D_PLL_LOCK, G3D_PLL_CON0, exynos5443_pll_rates),
3233 static const struct samsung_mux_clock g3d_mux_clks[] __initconst = {
3235 MUX_F(CLK_MOUT_ACLK_G3D_400, "mout_aclk_g3d_400", mout_aclk_g3d_400_p,
3236 MUX_SEL_G3D, 8, 1, CLK_SET_RATE_PARENT, 0),
3237 MUX_F(CLK_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p,
3238 MUX_SEL_G3D, 0, 1, CLK_SET_RATE_PARENT, 0),
3241 static const struct samsung_div_clock g3d_div_clks[] __initconst = {
3243 DIV(CLK_DIV_SCLK_HPM_G3D, "div_sclk_hpm_g3d", "mout_g3d_pll", DIV_G3D,
3245 DIV(CLK_DIV_PCLK_G3D, "div_pclk_g3d", "div_aclk_g3d", DIV_G3D,
3247 DIV_F(CLK_DIV_ACLK_G3D, "div_aclk_g3d", "mout_aclk_g3d_400", DIV_G3D,
3248 0, 3, CLK_SET_RATE_PARENT, 0),
3251 static const struct samsung_gate_clock g3d_gate_clks[] __initconst = {
3252 /* ENABLE_ACLK_G3D */
3253 GATE(CLK_ACLK_BTS_G3D1, "aclk_bts_g3d1", "div_aclk_g3d",
3254 ENABLE_ACLK_G3D, 7, 0, 0),
3255 GATE(CLK_ACLK_BTS_G3D0, "aclk_bts_g3d0", "div_aclk_g3d",
3256 ENABLE_ACLK_G3D, 6, 0, 0),
3257 GATE(CLK_ACLK_ASYNCAPBS_G3D, "aclk_asyncapbs_g3d", "div_pclk_g3d",
3258 ENABLE_ACLK_G3D, 5, CLK_IGNORE_UNUSED, 0),
3259 GATE(CLK_ACLK_ASYNCAPBM_G3D, "aclk_asyncapbm_g3d", "div_aclk_g3d",
3260 ENABLE_ACLK_G3D, 4, CLK_IGNORE_UNUSED, 0),
3261 GATE(CLK_ACLK_AHB2APB_G3DP, "aclk_ahb2apb_g3dp", "div_pclk_g3d",
3262 ENABLE_ACLK_G3D, 3, CLK_IGNORE_UNUSED, 0),
3263 GATE(CLK_ACLK_G3DNP_150, "aclk_g3dnp_150", "div_pclk_g3d",
3264 ENABLE_ACLK_G3D, 2, CLK_IGNORE_UNUSED, 0),
3265 GATE(CLK_ACLK_G3DND_600, "aclk_g3dnd_600", "div_aclk_g3d",
3266 ENABLE_ACLK_G3D, 1, CLK_IGNORE_UNUSED, 0),
3267 GATE(CLK_ACLK_G3D, "aclk_g3d", "div_aclk_g3d",
3268 ENABLE_ACLK_G3D, 0, CLK_SET_RATE_PARENT, 0),
3270 /* ENABLE_PCLK_G3D */
3271 GATE(CLK_PCLK_BTS_G3D1, "pclk_bts_g3d1", "div_pclk_g3d",
3272 ENABLE_PCLK_G3D, 3, 0, 0),
3273 GATE(CLK_PCLK_BTS_G3D0, "pclk_bts_g3d0", "div_pclk_g3d",
3274 ENABLE_PCLK_G3D, 2, 0, 0),
3275 GATE(CLK_PCLK_PMU_G3D, "pclk_pmu_g3d", "div_pclk_g3d",
3276 ENABLE_PCLK_G3D, 1, CLK_IGNORE_UNUSED, 0),
3277 GATE(CLK_PCLK_SYSREG_G3D, "pclk_sysreg_g3d", "div_pclk_g3d",
3278 ENABLE_PCLK_G3D, 0, CLK_IGNORE_UNUSED, 0),
3280 /* ENABLE_SCLK_G3D */
3281 GATE(CLK_SCLK_HPM_G3D, "sclk_hpm_g3d", "div_sclk_hpm_g3d",
3282 ENABLE_SCLK_G3D, 0, 0, 0),
3285 static const struct samsung_cmu_info g3d_cmu_info __initconst = {
3286 .pll_clks = g3d_pll_clks,
3287 .nr_pll_clks = ARRAY_SIZE(g3d_pll_clks),
3288 .mux_clks = g3d_mux_clks,
3289 .nr_mux_clks = ARRAY_SIZE(g3d_mux_clks),
3290 .div_clks = g3d_div_clks,
3291 .nr_div_clks = ARRAY_SIZE(g3d_div_clks),
3292 .gate_clks = g3d_gate_clks,
3293 .nr_gate_clks = ARRAY_SIZE(g3d_gate_clks),
3294 .nr_clk_ids = G3D_NR_CLK,
3295 .clk_regs = g3d_clk_regs,
3296 .nr_clk_regs = ARRAY_SIZE(g3d_clk_regs),
3299 static void __init exynos5433_cmu_g3d_init(struct device_node *np)
3301 samsung_cmu_register_one(np, &g3d_cmu_info);
3303 CLK_OF_DECLARE(exynos5433_cmu_g3d, "samsung,exynos5433-cmu-g3d",
3304 exynos5433_cmu_g3d_init);
3307 * Register offset definitions for CMU_GSCL
3309 #define MUX_SEL_GSCL 0x0200
3310 #define MUX_ENABLE_GSCL 0x0300
3311 #define MUX_STAT_GSCL 0x0400
3312 #define ENABLE_ACLK_GSCL 0x0800
3313 #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 0x0804
3314 #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 0x0808
3315 #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 0x080c
3316 #define ENABLE_PCLK_GSCL 0x0900
3317 #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 0x0904
3318 #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 0x0908
3319 #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 0x090c
3320 #define ENABLE_IP_GSCL0 0x0b00
3321 #define ENABLE_IP_GSCL1 0x0b04
3322 #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL0 0x0b08
3323 #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL1 0x0b0c
3324 #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL2 0x0b10
3326 static const unsigned long gscl_clk_regs[] __initconst = {
3330 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0,
3331 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1,
3332 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2,
3334 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0,
3335 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1,
3336 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2,
3339 ENABLE_IP_GSCL_SECURE_SMMU_GSCL0,
3340 ENABLE_IP_GSCL_SECURE_SMMU_GSCL1,
3341 ENABLE_IP_GSCL_SECURE_SMMU_GSCL2,
3344 /* list of all parent clock list */
3345 PNAME(aclk_gscl_111_user_p) = { "oscclk", "aclk_gscl_111", };
3346 PNAME(aclk_gscl_333_user_p) = { "oscclk", "aclk_gscl_333", };
3348 static const struct samsung_mux_clock gscl_mux_clks[] __initconst = {
3350 MUX(CLK_MOUT_ACLK_GSCL_111_USER, "mout_aclk_gscl_111_user",
3351 aclk_gscl_111_user_p, MUX_SEL_GSCL, 4, 1),
3352 MUX(CLK_MOUT_ACLK_GSCL_333_USER, "mout_aclk_gscl_333_user",
3353 aclk_gscl_333_user_p, MUX_SEL_GSCL, 0, 1),
3356 static const struct samsung_gate_clock gscl_gate_clks[] __initconst = {
3357 /* ENABLE_ACLK_GSCL */
3358 GATE(CLK_ACLK_BTS_GSCL2, "aclk_bts_gscl2", "mout_aclk_gscl_333_user",
3359 ENABLE_ACLK_GSCL, 11, 0, 0),
3360 GATE(CLK_ACLK_BTS_GSCL1, "aclk_bts_gscl1", "mout_aclk_gscl_333_user",
3361 ENABLE_ACLK_GSCL, 10, 0, 0),
3362 GATE(CLK_ACLK_BTS_GSCL0, "aclk_bts_gscl0", "mout_aclk_gscl_333_user",
3363 ENABLE_ACLK_GSCL, 9, 0, 0),
3364 GATE(CLK_ACLK_AHB2APB_GSCLP, "aclk_ahb2apb_gsclp",
3365 "mout_aclk_gscl_111_user", ENABLE_ACLK_GSCL,
3366 8, CLK_IGNORE_UNUSED, 0),
3367 GATE(CLK_ACLK_XIU_GSCLX, "aclk_xiu_gsclx", "mout_aclk_gscl_333_user",
3368 ENABLE_ACLK_GSCL, 7, 0, 0),
3369 GATE(CLK_ACLK_GSCLNP_111, "aclk_gsclnp_111", "mout_aclk_gscl_111_user",
3370 ENABLE_ACLK_GSCL, 6, CLK_IGNORE_UNUSED, 0),
3371 GATE(CLK_ACLK_GSCLRTND_333, "aclk_gsclrtnd_333",
3372 "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 5,
3373 CLK_IGNORE_UNUSED, 0),
3374 GATE(CLK_ACLK_GSCLBEND_333, "aclk_gsclbend_333",
3375 "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 4,
3376 CLK_IGNORE_UNUSED, 0),
3377 GATE(CLK_ACLK_GSD, "aclk_gsd", "mout_aclk_gscl_333_user",
3378 ENABLE_ACLK_GSCL, 3, 0, 0),
3379 GATE(CLK_ACLK_GSCL2, "aclk_gscl2", "mout_aclk_gscl_333_user",
3380 ENABLE_ACLK_GSCL, 2, 0, 0),
3381 GATE(CLK_ACLK_GSCL1, "aclk_gscl1", "mout_aclk_gscl_333_user",
3382 ENABLE_ACLK_GSCL, 1, 0, 0),
3383 GATE(CLK_ACLK_GSCL0, "aclk_gscl0", "mout_aclk_gscl_333_user",
3384 ENABLE_ACLK_GSCL, 0, 0, 0),
3386 /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 */
3387 GATE(CLK_ACLK_SMMU_GSCL0, "aclk_smmu_gscl0", "mout_aclk_gscl_333_user",
3388 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
3390 /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 */
3391 GATE(CLK_ACLK_SMMU_GSCL1, "aclk_smmu_gscl1", "mout_aclk_gscl_333_user",
3392 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1, 0, 0, 0),
3394 /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 */
3395 GATE(CLK_ACLK_SMMU_GSCL2, "aclk_smmu_gscl2", "mout_aclk_gscl_333_user",
3396 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0),
3398 /* ENABLE_PCLK_GSCL */
3399 GATE(CLK_PCLK_BTS_GSCL2, "pclk_bts_gscl2", "mout_aclk_gscl_111_user",
3400 ENABLE_PCLK_GSCL, 7, 0, 0),
3401 GATE(CLK_PCLK_BTS_GSCL1, "pclk_bts_gscl1", "mout_aclk_gscl_111_user",
3402 ENABLE_PCLK_GSCL, 6, 0, 0),
3403 GATE(CLK_PCLK_BTS_GSCL0, "pclk_bts_gscl0", "mout_aclk_gscl_111_user",
3404 ENABLE_PCLK_GSCL, 5, 0, 0),
3405 GATE(CLK_PCLK_PMU_GSCL, "pclk_pmu_gscl", "mout_aclk_gscl_111_user",
3406 ENABLE_PCLK_GSCL, 4, CLK_IGNORE_UNUSED, 0),
3407 GATE(CLK_PCLK_SYSREG_GSCL, "pclk_sysreg_gscl",
3408 "mout_aclk_gscl_111_user", ENABLE_PCLK_GSCL,
3409 3, CLK_IGNORE_UNUSED, 0),
3410 GATE(CLK_PCLK_GSCL2, "pclk_gscl2", "mout_aclk_gscl_111_user",
3411 ENABLE_PCLK_GSCL, 2, 0, 0),
3412 GATE(CLK_PCLK_GSCL1, "pclk_gscl1", "mout_aclk_gscl_111_user",
3413 ENABLE_PCLK_GSCL, 1, 0, 0),
3414 GATE(CLK_PCLK_GSCL0, "pclk_gscl0", "mout_aclk_gscl_111_user",
3415 ENABLE_PCLK_GSCL, 0, 0, 0),
3417 /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 */
3418 GATE(CLK_PCLK_SMMU_GSCL0, "pclk_smmu_gscl0", "mout_aclk_gscl_111_user",
3419 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
3421 /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 */
3422 GATE(CLK_PCLK_SMMU_GSCL1, "pclk_smmu_gscl1", "mout_aclk_gscl_111_user",
3423 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1, 0, 0, 0),
3425 /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 */
3426 GATE(CLK_PCLK_SMMU_GSCL2, "pclk_smmu_gscl2", "mout_aclk_gscl_111_user",
3427 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0),
3430 static const struct samsung_cmu_info gscl_cmu_info __initconst = {
3431 .mux_clks = gscl_mux_clks,
3432 .nr_mux_clks = ARRAY_SIZE(gscl_mux_clks),
3433 .gate_clks = gscl_gate_clks,
3434 .nr_gate_clks = ARRAY_SIZE(gscl_gate_clks),
3435 .nr_clk_ids = GSCL_NR_CLK,
3436 .clk_regs = gscl_clk_regs,
3437 .nr_clk_regs = ARRAY_SIZE(gscl_clk_regs),
3440 static void __init exynos5433_cmu_gscl_init(struct device_node *np)
3442 samsung_cmu_register_one(np, &gscl_cmu_info);
3444 CLK_OF_DECLARE(exynos5433_cmu_gscl, "samsung,exynos5433-cmu-gscl",
3445 exynos5433_cmu_gscl_init);
3448 * Register offset definitions for CMU_APOLLO
3450 #define APOLLO_PLL_LOCK 0x0000
3451 #define APOLLO_PLL_CON0 0x0100
3452 #define APOLLO_PLL_CON1 0x0104
3453 #define APOLLO_PLL_FREQ_DET 0x010c
3454 #define MUX_SEL_APOLLO0 0x0200
3455 #define MUX_SEL_APOLLO1 0x0204
3456 #define MUX_SEL_APOLLO2 0x0208
3457 #define MUX_ENABLE_APOLLO0 0x0300
3458 #define MUX_ENABLE_APOLLO1 0x0304
3459 #define MUX_ENABLE_APOLLO2 0x0308
3460 #define MUX_STAT_APOLLO0 0x0400
3461 #define MUX_STAT_APOLLO1 0x0404
3462 #define MUX_STAT_APOLLO2 0x0408
3463 #define DIV_APOLLO0 0x0600
3464 #define DIV_APOLLO1 0x0604
3465 #define DIV_APOLLO_PLL_FREQ_DET 0x0608
3466 #define DIV_STAT_APOLLO0 0x0700
3467 #define DIV_STAT_APOLLO1 0x0704
3468 #define DIV_STAT_APOLLO_PLL_FREQ_DET 0x0708
3469 #define ENABLE_ACLK_APOLLO 0x0800
3470 #define ENABLE_PCLK_APOLLO 0x0900
3471 #define ENABLE_SCLK_APOLLO 0x0a00
3472 #define ENABLE_IP_APOLLO0 0x0b00
3473 #define ENABLE_IP_APOLLO1 0x0b04
3474 #define CLKOUT_CMU_APOLLO 0x0c00
3475 #define CLKOUT_CMU_APOLLO_DIV_STAT 0x0c04
3476 #define ARMCLK_STOPCTRL 0x1000
3477 #define APOLLO_PWR_CTRL 0x1020
3478 #define APOLLO_PWR_CTRL2 0x1024
3479 #define APOLLO_INTR_SPREAD_ENABLE 0x1080
3480 #define APOLLO_INTR_SPREAD_USE_STANDBYWFI 0x1084
3481 #define APOLLO_INTR_SPREAD_BLOCKING_DURATION 0x1088
3483 static const unsigned long apollo_clk_regs[] __initconst = {
3487 APOLLO_PLL_FREQ_DET,
3496 DIV_APOLLO_PLL_FREQ_DET,
3503 CLKOUT_CMU_APOLLO_DIV_STAT,
3507 APOLLO_INTR_SPREAD_ENABLE,
3508 APOLLO_INTR_SPREAD_USE_STANDBYWFI,
3509 APOLLO_INTR_SPREAD_BLOCKING_DURATION,
3512 /* list of all parent clock list */
3513 PNAME(mout_apollo_pll_p) = { "oscclk", "fout_apollo_pll", };
3514 PNAME(mout_bus_pll_apollo_user_p) = { "oscclk", "sclk_bus_pll_apollo", };
3515 PNAME(mout_apollo_p) = { "mout_apollo_pll",
3516 "mout_bus_pll_apollo_user", };
3518 static const struct samsung_pll_clock apollo_pll_clks[] __initconst = {
3519 PLL(pll_35xx, CLK_FOUT_APOLLO_PLL, "fout_apollo_pll", "oscclk",
3520 APOLLO_PLL_LOCK, APOLLO_PLL_CON0, exynos5443_pll_rates),
3523 static const struct samsung_mux_clock apollo_mux_clks[] __initconst = {
3524 /* MUX_SEL_APOLLO0 */
3525 MUX_F(CLK_MOUT_APOLLO_PLL, "mout_apollo_pll", mout_apollo_pll_p,
3526 MUX_SEL_APOLLO0, 0, 1, CLK_SET_RATE_PARENT |
3527 CLK_RECALC_NEW_RATES, 0),
3529 /* MUX_SEL_APOLLO1 */
3530 MUX(CLK_MOUT_BUS_PLL_APOLLO_USER, "mout_bus_pll_apollo_user",
3531 mout_bus_pll_apollo_user_p, MUX_SEL_APOLLO1, 0, 1),
3533 /* MUX_SEL_APOLLO2 */
3534 MUX_F(CLK_MOUT_APOLLO, "mout_apollo", mout_apollo_p, MUX_SEL_APOLLO2,
3535 0, 1, CLK_SET_RATE_PARENT, 0),
3538 static const struct samsung_div_clock apollo_div_clks[] __initconst = {
3540 DIV_F(CLK_DIV_CNTCLK_APOLLO, "div_cntclk_apollo", "div_apollo2",
3541 DIV_APOLLO0, 24, 3, CLK_GET_RATE_NOCACHE,
3542 CLK_DIVIDER_READ_ONLY),
3543 DIV_F(CLK_DIV_PCLK_DBG_APOLLO, "div_pclk_dbg_apollo", "div_apollo2",
3544 DIV_APOLLO0, 20, 3, CLK_GET_RATE_NOCACHE,
3545 CLK_DIVIDER_READ_ONLY),
3546 DIV_F(CLK_DIV_ATCLK_APOLLO, "div_atclk_apollo", "div_apollo2",
3547 DIV_APOLLO0, 16, 3, CLK_GET_RATE_NOCACHE,
3548 CLK_DIVIDER_READ_ONLY),
3549 DIV_F(CLK_DIV_PCLK_APOLLO, "div_pclk_apollo", "div_apollo2",
3550 DIV_APOLLO0, 12, 3, CLK_GET_RATE_NOCACHE,
3551 CLK_DIVIDER_READ_ONLY),
3552 DIV_F(CLK_DIV_ACLK_APOLLO, "div_aclk_apollo", "div_apollo2",
3553 DIV_APOLLO0, 8, 3, CLK_GET_RATE_NOCACHE,
3554 CLK_DIVIDER_READ_ONLY),
3555 DIV_F(CLK_DIV_APOLLO2, "div_apollo2", "div_apollo1",
3556 DIV_APOLLO0, 4, 3, CLK_SET_RATE_PARENT, 0),
3557 DIV_F(CLK_DIV_APOLLO1, "div_apollo1", "mout_apollo",
3558 DIV_APOLLO0, 0, 3, CLK_SET_RATE_PARENT, 0),
3561 DIV_F(CLK_DIV_SCLK_HPM_APOLLO, "div_sclk_hpm_apollo", "mout_apollo",
3562 DIV_APOLLO1, 4, 3, CLK_GET_RATE_NOCACHE,
3563 CLK_DIVIDER_READ_ONLY),
3564 DIV_F(CLK_DIV_APOLLO_PLL, "div_apollo_pll", "mout_apollo",
3565 DIV_APOLLO1, 0, 3, CLK_GET_RATE_NOCACHE,
3566 CLK_DIVIDER_READ_ONLY),
3569 static const struct samsung_gate_clock apollo_gate_clks[] __initconst = {
3570 /* ENABLE_ACLK_APOLLO */
3571 GATE(CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS, "aclk_asatbslv_apollo_3_cssys",
3572 "div_atclk_apollo", ENABLE_ACLK_APOLLO,
3573 6, CLK_IGNORE_UNUSED, 0),
3574 GATE(CLK_ACLK_ASATBSLV_APOLLO_2_CSSYS, "aclk_asatbslv_apollo_2_cssys",
3575 "div_atclk_apollo", ENABLE_ACLK_APOLLO,
3576 5, CLK_IGNORE_UNUSED, 0),
3577 GATE(CLK_ACLK_ASATBSLV_APOLLO_1_CSSYS, "aclk_asatbslv_apollo_1_cssys",
3578 "div_atclk_apollo", ENABLE_ACLK_APOLLO,
3579 4, CLK_IGNORE_UNUSED, 0),
3580 GATE(CLK_ACLK_ASATBSLV_APOLLO_0_CSSYS, "aclk_asatbslv_apollo_0_cssys",
3581 "div_atclk_apollo", ENABLE_ACLK_APOLLO,
3582 3, CLK_IGNORE_UNUSED, 0),
3583 GATE(CLK_ACLK_ASYNCACES_APOLLO_CCI, "aclk_asyncaces_apollo_cci",
3584 "div_aclk_apollo", ENABLE_ACLK_APOLLO,
3585 2, CLK_IGNORE_UNUSED, 0),
3586 GATE(CLK_ACLK_AHB2APB_APOLLOP, "aclk_ahb2apb_apollop",
3587 "div_pclk_apollo", ENABLE_ACLK_APOLLO,
3588 1, CLK_IGNORE_UNUSED, 0),
3589 GATE(CLK_ACLK_APOLLONP_200, "aclk_apollonp_200",
3590 "div_pclk_apollo", ENABLE_ACLK_APOLLO,
3591 0, CLK_IGNORE_UNUSED, 0),
3593 /* ENABLE_PCLK_APOLLO */
3594 GATE(CLK_PCLK_ASAPBMST_CSSYS_APOLLO, "pclk_asapbmst_cssys_apollo",
3595 "div_pclk_dbg_apollo", ENABLE_PCLK_APOLLO,
3596 2, CLK_IGNORE_UNUSED, 0),
3597 GATE(CLK_PCLK_PMU_APOLLO, "pclk_pmu_apollo", "div_pclk_apollo",
3598 ENABLE_PCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0),
3599 GATE(CLK_PCLK_SYSREG_APOLLO, "pclk_sysreg_apollo",
3600 "div_pclk_apollo", ENABLE_PCLK_APOLLO,
3601 0, CLK_IGNORE_UNUSED, 0),
3603 /* ENABLE_SCLK_APOLLO */
3604 GATE(CLK_CNTCLK_APOLLO, "cntclk_apollo", "div_cntclk_apollo",
3605 ENABLE_SCLK_APOLLO, 3, CLK_IGNORE_UNUSED, 0),
3606 GATE(CLK_SCLK_HPM_APOLLO, "sclk_hpm_apollo", "div_sclk_hpm_apollo",
3607 ENABLE_SCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0),
3610 #define E5433_APOLLO_DIV0(cntclk, pclk_dbg, atclk, pclk, aclk) \
3611 (((cntclk) << 24) | ((pclk_dbg) << 20) | ((atclk) << 16) | \
3612 ((pclk) << 12) | ((aclk) << 8))
3614 #define E5433_APOLLO_DIV1(hpm, copy) \
3615 (((hpm) << 4) | ((copy) << 0))
3617 static const struct exynos_cpuclk_cfg_data exynos5433_apolloclk_d[] __initconst = {
3618 { 1300000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3619 { 1200000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3620 { 1100000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3621 { 1000000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3622 { 900000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3623 { 800000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3624 { 700000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3625 { 600000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), },
3626 { 500000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), },
3627 { 400000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), },
3631 static void __init exynos5433_cmu_apollo_init(struct device_node *np)
3633 void __iomem *reg_base;
3634 struct samsung_clk_provider *ctx;
3636 reg_base = of_iomap(np, 0);
3638 panic("%s: failed to map registers\n", __func__);
3642 ctx = samsung_clk_init(np, reg_base, APOLLO_NR_CLK);
3644 panic("%s: unable to allocate ctx\n", __func__);
3648 samsung_clk_register_pll(ctx, apollo_pll_clks,
3649 ARRAY_SIZE(apollo_pll_clks), reg_base);
3650 samsung_clk_register_mux(ctx, apollo_mux_clks,
3651 ARRAY_SIZE(apollo_mux_clks));
3652 samsung_clk_register_div(ctx, apollo_div_clks,
3653 ARRAY_SIZE(apollo_div_clks));
3654 samsung_clk_register_gate(ctx, apollo_gate_clks,
3655 ARRAY_SIZE(apollo_gate_clks));
3657 exynos_register_cpu_clock(ctx, CLK_SCLK_APOLLO, "apolloclk",
3658 mout_apollo_p[0], mout_apollo_p[1], 0x200,
3659 exynos5433_apolloclk_d, ARRAY_SIZE(exynos5433_apolloclk_d),
3660 CLK_CPU_HAS_E5433_REGS_LAYOUT);
3662 samsung_clk_sleep_init(reg_base, apollo_clk_regs,
3663 ARRAY_SIZE(apollo_clk_regs));
3665 samsung_clk_of_add_provider(np, ctx);
3667 CLK_OF_DECLARE(exynos5433_cmu_apollo, "samsung,exynos5433-cmu-apollo",
3668 exynos5433_cmu_apollo_init);
3671 * Register offset definitions for CMU_ATLAS
3673 #define ATLAS_PLL_LOCK 0x0000
3674 #define ATLAS_PLL_CON0 0x0100
3675 #define ATLAS_PLL_CON1 0x0104
3676 #define ATLAS_PLL_FREQ_DET 0x010c
3677 #define MUX_SEL_ATLAS0 0x0200
3678 #define MUX_SEL_ATLAS1 0x0204
3679 #define MUX_SEL_ATLAS2 0x0208
3680 #define MUX_ENABLE_ATLAS0 0x0300
3681 #define MUX_ENABLE_ATLAS1 0x0304
3682 #define MUX_ENABLE_ATLAS2 0x0308
3683 #define MUX_STAT_ATLAS0 0x0400
3684 #define MUX_STAT_ATLAS1 0x0404
3685 #define MUX_STAT_ATLAS2 0x0408
3686 #define DIV_ATLAS0 0x0600
3687 #define DIV_ATLAS1 0x0604
3688 #define DIV_ATLAS_PLL_FREQ_DET 0x0608
3689 #define DIV_STAT_ATLAS0 0x0700
3690 #define DIV_STAT_ATLAS1 0x0704
3691 #define DIV_STAT_ATLAS_PLL_FREQ_DET 0x0708
3692 #define ENABLE_ACLK_ATLAS 0x0800
3693 #define ENABLE_PCLK_ATLAS 0x0900
3694 #define ENABLE_SCLK_ATLAS 0x0a00
3695 #define ENABLE_IP_ATLAS0 0x0b00
3696 #define ENABLE_IP_ATLAS1 0x0b04
3697 #define CLKOUT_CMU_ATLAS 0x0c00
3698 #define CLKOUT_CMU_ATLAS_DIV_STAT 0x0c04
3699 #define ARMCLK_STOPCTRL 0x1000
3700 #define ATLAS_PWR_CTRL 0x1020
3701 #define ATLAS_PWR_CTRL2 0x1024
3702 #define ATLAS_INTR_SPREAD_ENABLE 0x1080
3703 #define ATLAS_INTR_SPREAD_USE_STANDBYWFI 0x1084
3704 #define ATLAS_INTR_SPREAD_BLOCKING_DURATION 0x1088
3706 static const unsigned long atlas_clk_regs[] __initconst = {
3719 DIV_ATLAS_PLL_FREQ_DET,
3726 CLKOUT_CMU_ATLAS_DIV_STAT,
3730 ATLAS_INTR_SPREAD_ENABLE,
3731 ATLAS_INTR_SPREAD_USE_STANDBYWFI,
3732 ATLAS_INTR_SPREAD_BLOCKING_DURATION,
3735 /* list of all parent clock list */
3736 PNAME(mout_atlas_pll_p) = { "oscclk", "fout_atlas_pll", };
3737 PNAME(mout_bus_pll_atlas_user_p) = { "oscclk", "sclk_bus_pll_atlas", };
3738 PNAME(mout_atlas_p) = { "mout_atlas_pll",
3739 "mout_bus_pll_atlas_user", };
3741 static const struct samsung_pll_clock atlas_pll_clks[] __initconst = {
3742 PLL(pll_35xx, CLK_FOUT_ATLAS_PLL, "fout_atlas_pll", "oscclk",
3743 ATLAS_PLL_LOCK, ATLAS_PLL_CON0, exynos5443_pll_rates),
3746 static const struct samsung_mux_clock atlas_mux_clks[] __initconst = {
3747 /* MUX_SEL_ATLAS0 */
3748 MUX_F(CLK_MOUT_ATLAS_PLL, "mout_atlas_pll", mout_atlas_pll_p,
3749 MUX_SEL_ATLAS0, 0, 1, CLK_SET_RATE_PARENT |
3750 CLK_RECALC_NEW_RATES, 0),
3752 /* MUX_SEL_ATLAS1 */
3753 MUX(CLK_MOUT_BUS_PLL_ATLAS_USER, "mout_bus_pll_atlas_user",
3754 mout_bus_pll_atlas_user_p, MUX_SEL_ATLAS1, 0, 1),
3756 /* MUX_SEL_ATLAS2 */
3757 MUX_F(CLK_MOUT_ATLAS, "mout_atlas", mout_atlas_p, MUX_SEL_ATLAS2,
3758 0, 1, CLK_SET_RATE_PARENT, 0),
3761 static const struct samsung_div_clock atlas_div_clks[] __initconst = {
3763 DIV_F(CLK_DIV_CNTCLK_ATLAS, "div_cntclk_atlas", "div_atlas2",
3764 DIV_ATLAS0, 24, 3, CLK_GET_RATE_NOCACHE,
3765 CLK_DIVIDER_READ_ONLY),
3766 DIV_F(CLK_DIV_PCLK_DBG_ATLAS, "div_pclk_dbg_atlas", "div_atclk_atlas",
3767 DIV_ATLAS0, 20, 3, CLK_GET_RATE_NOCACHE,
3768 CLK_DIVIDER_READ_ONLY),
3769 DIV_F(CLK_DIV_ATCLK_ATLASO, "div_atclk_atlas", "div_atlas2",
3770 DIV_ATLAS0, 16, 3, CLK_GET_RATE_NOCACHE,
3771 CLK_DIVIDER_READ_ONLY),
3772 DIV_F(CLK_DIV_PCLK_ATLAS, "div_pclk_atlas", "div_atlas2",
3773 DIV_ATLAS0, 12, 3, CLK_GET_RATE_NOCACHE,
3774 CLK_DIVIDER_READ_ONLY),
3775 DIV_F(CLK_DIV_ACLK_ATLAS, "div_aclk_atlas", "div_atlas2",
3776 DIV_ATLAS0, 8, 3, CLK_GET_RATE_NOCACHE,
3777 CLK_DIVIDER_READ_ONLY),
3778 DIV_F(CLK_DIV_ATLAS2, "div_atlas2", "div_atlas1",
3779 DIV_ATLAS0, 4, 3, CLK_SET_RATE_PARENT, 0),
3780 DIV_F(CLK_DIV_ATLAS1, "div_atlas1", "mout_atlas",
3781 DIV_ATLAS0, 0, 3, CLK_SET_RATE_PARENT, 0),
3784 DIV_F(CLK_DIV_SCLK_HPM_ATLAS, "div_sclk_hpm_atlas", "mout_atlas",
3785 DIV_ATLAS1, 4, 3, CLK_GET_RATE_NOCACHE,
3786 CLK_DIVIDER_READ_ONLY),
3787 DIV_F(CLK_DIV_ATLAS_PLL, "div_atlas_pll", "mout_atlas",
3788 DIV_ATLAS1, 0, 3, CLK_GET_RATE_NOCACHE,
3789 CLK_DIVIDER_READ_ONLY),
3792 static const struct samsung_gate_clock atlas_gate_clks[] __initconst = {
3793 /* ENABLE_ACLK_ATLAS */
3794 GATE(CLK_ACLK_ATB_AUD_CSSYS, "aclk_atb_aud_cssys",
3795 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3796 9, CLK_IGNORE_UNUSED, 0),
3797 GATE(CLK_ACLK_ATB_APOLLO3_CSSYS, "aclk_atb_apollo3_cssys",
3798 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3799 8, CLK_IGNORE_UNUSED, 0),
3800 GATE(CLK_ACLK_ATB_APOLLO2_CSSYS, "aclk_atb_apollo2_cssys",
3801 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3802 7, CLK_IGNORE_UNUSED, 0),
3803 GATE(CLK_ACLK_ATB_APOLLO1_CSSYS, "aclk_atb_apollo1_cssys",
3804 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3805 6, CLK_IGNORE_UNUSED, 0),
3806 GATE(CLK_ACLK_ATB_APOLLO0_CSSYS, "aclk_atb_apollo0_cssys",
3807 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3808 5, CLK_IGNORE_UNUSED, 0),
3809 GATE(CLK_ACLK_ASYNCAHBS_CSSYS_SSS, "aclk_asyncahbs_cssys_sss",
3810 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3811 4, CLK_IGNORE_UNUSED, 0),
3812 GATE(CLK_ACLK_ASYNCAXIS_CSSYS_CCIX, "aclk_asyncaxis_cssys_ccix",
3813 "div_pclk_dbg_atlas", ENABLE_ACLK_ATLAS,
3814 3, CLK_IGNORE_UNUSED, 0),
3815 GATE(CLK_ACLK_ASYNCACES_ATLAS_CCI, "aclk_asyncaces_atlas_cci",
3816 "div_aclk_atlas", ENABLE_ACLK_ATLAS,
3817 2, CLK_IGNORE_UNUSED, 0),
3818 GATE(CLK_ACLK_AHB2APB_ATLASP, "aclk_ahb2apb_atlasp", "div_pclk_atlas",
3819 ENABLE_ACLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
3820 GATE(CLK_ACLK_ATLASNP_200, "aclk_atlasnp_200", "div_pclk_atlas",
3821 ENABLE_ACLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0),
3823 /* ENABLE_PCLK_ATLAS */
3824 GATE(CLK_PCLK_ASYNCAPB_AUD_CSSYS, "pclk_asyncapb_aud_cssys",
3825 "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
3826 5, CLK_IGNORE_UNUSED, 0),
3827 GATE(CLK_PCLK_ASYNCAPB_ISP_CSSYS, "pclk_asyncapb_isp_cssys",
3828 "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
3829 4, CLK_IGNORE_UNUSED, 0),
3830 GATE(CLK_PCLK_ASYNCAPB_APOLLO_CSSYS, "pclk_asyncapb_apollo_cssys",
3831 "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
3832 3, CLK_IGNORE_UNUSED, 0),
3833 GATE(CLK_PCLK_PMU_ATLAS, "pclk_pmu_atlas", "div_pclk_atlas",
3834 ENABLE_PCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0),
3835 GATE(CLK_PCLK_SYSREG_ATLAS, "pclk_sysreg_atlas", "div_pclk_atlas",
3836 ENABLE_PCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
3837 GATE(CLK_PCLK_SECJTAG, "pclk_secjtag", "div_pclk_dbg_atlas",
3838 ENABLE_PCLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0),
3840 /* ENABLE_SCLK_ATLAS */
3841 GATE(CLK_CNTCLK_ATLAS, "cntclk_atlas", "div_cntclk_atlas",
3842 ENABLE_SCLK_ATLAS, 10, CLK_IGNORE_UNUSED, 0),
3843 GATE(CLK_SCLK_HPM_ATLAS, "sclk_hpm_atlas", "div_sclk_hpm_atlas",
3844 ENABLE_SCLK_ATLAS, 7, CLK_IGNORE_UNUSED, 0),
3845 GATE(CLK_TRACECLK, "traceclk", "div_atclk_atlas",
3846 ENABLE_SCLK_ATLAS, 6, CLK_IGNORE_UNUSED, 0),
3847 GATE(CLK_CTMCLK, "ctmclk", "div_atclk_atlas",
3848 ENABLE_SCLK_ATLAS, 5, CLK_IGNORE_UNUSED, 0),
3849 GATE(CLK_HCLK_CSSYS, "hclk_cssys", "div_atclk_atlas",
3850 ENABLE_SCLK_ATLAS, 4, CLK_IGNORE_UNUSED, 0),
3851 GATE(CLK_PCLK_DBG_CSSYS, "pclk_dbg_cssys", "div_pclk_dbg_atlas",
3852 ENABLE_SCLK_ATLAS, 3, CLK_IGNORE_UNUSED, 0),
3853 GATE(CLK_PCLK_DBG, "pclk_dbg", "div_pclk_dbg_atlas",
3854 ENABLE_SCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0),
3855 GATE(CLK_ATCLK, "atclk", "div_atclk_atlas",
3856 ENABLE_SCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
3859 #define E5433_ATLAS_DIV0(cntclk, pclk_dbg, atclk, pclk, aclk) \
3860 (((cntclk) << 24) | ((pclk_dbg) << 20) | ((atclk) << 16) | \
3861 ((pclk) << 12) | ((aclk) << 8))
3863 #define E5433_ATLAS_DIV1(hpm, copy) \
3864 (((hpm) << 4) | ((copy) << 0))
3866 static const struct exynos_cpuclk_cfg_data exynos5433_atlasclk_d[] __initconst = {
3867 { 1900000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), },
3868 { 1800000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), },
3869 { 1700000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), },
3870 { 1600000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), },
3871 { 1500000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
3872 { 1400000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
3873 { 1300000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
3874 { 1200000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
3875 { 1100000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
3876 { 1000000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
3877 { 900000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
3878 { 800000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
3879 { 700000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
3880 { 600000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
3881 { 500000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
3885 static void __init exynos5433_cmu_atlas_init(struct device_node *np)
3887 void __iomem *reg_base;
3888 struct samsung_clk_provider *ctx;
3890 reg_base = of_iomap(np, 0);
3892 panic("%s: failed to map registers\n", __func__);
3896 ctx = samsung_clk_init(np, reg_base, ATLAS_NR_CLK);
3898 panic("%s: unable to allocate ctx\n", __func__);
3902 samsung_clk_register_pll(ctx, atlas_pll_clks,
3903 ARRAY_SIZE(atlas_pll_clks), reg_base);
3904 samsung_clk_register_mux(ctx, atlas_mux_clks,
3905 ARRAY_SIZE(atlas_mux_clks));
3906 samsung_clk_register_div(ctx, atlas_div_clks,
3907 ARRAY_SIZE(atlas_div_clks));
3908 samsung_clk_register_gate(ctx, atlas_gate_clks,
3909 ARRAY_SIZE(atlas_gate_clks));
3911 exynos_register_cpu_clock(ctx, CLK_SCLK_ATLAS, "atlasclk",
3912 mout_atlas_p[0], mout_atlas_p[1], 0x200,
3913 exynos5433_atlasclk_d, ARRAY_SIZE(exynos5433_atlasclk_d),
3914 CLK_CPU_HAS_E5433_REGS_LAYOUT);
3916 samsung_clk_sleep_init(reg_base, atlas_clk_regs,
3917 ARRAY_SIZE(atlas_clk_regs));
3919 samsung_clk_of_add_provider(np, ctx);
3921 CLK_OF_DECLARE(exynos5433_cmu_atlas, "samsung,exynos5433-cmu-atlas",
3922 exynos5433_cmu_atlas_init);
3925 * Register offset definitions for CMU_MSCL
3927 #define MUX_SEL_MSCL0 0x0200
3928 #define MUX_SEL_MSCL1 0x0204
3929 #define MUX_ENABLE_MSCL0 0x0300
3930 #define MUX_ENABLE_MSCL1 0x0304
3931 #define MUX_STAT_MSCL0 0x0400
3932 #define MUX_STAT_MSCL1 0x0404
3933 #define DIV_MSCL 0x0600
3934 #define DIV_STAT_MSCL 0x0700
3935 #define ENABLE_ACLK_MSCL 0x0800
3936 #define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0 0x0804
3937 #define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1 0x0808
3938 #define ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG 0x080c
3939 #define ENABLE_PCLK_MSCL 0x0900
3940 #define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 0x0904
3941 #define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 0x0908
3942 #define ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG 0x090c
3943 #define ENABLE_SCLK_MSCL 0x0a00
3944 #define ENABLE_IP_MSCL0 0x0b00
3945 #define ENABLE_IP_MSCL1 0x0b04
3946 #define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0 0x0b08
3947 #define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1 0x0b0c
3948 #define ENABLE_IP_MSCL_SECURE_SMMU_JPEG 0x0b10
3950 static const unsigned long mscl_clk_regs[] __initconst = {
3957 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0,
3958 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1,
3959 ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG,
3961 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0,
3962 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1,
3963 ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG,
3967 ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0,
3968 ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1,
3969 ENABLE_IP_MSCL_SECURE_SMMU_JPEG,
3972 /* list of all parent clock list */
3973 PNAME(mout_sclk_jpeg_user_p) = { "oscclk", "sclk_jpeg_mscl", };
3974 PNAME(mout_aclk_mscl_400_user_p) = { "oscclk", "aclk_mscl_400", };
3975 PNAME(mout_sclk_jpeg_p) = { "mout_sclk_jpeg_user",
3976 "mout_aclk_mscl_400_user", };
3978 static const struct samsung_mux_clock mscl_mux_clks[] __initconst = {
3980 MUX(CLK_MOUT_SCLK_JPEG_USER, "mout_sclk_jpeg_user",
3981 mout_sclk_jpeg_user_p, MUX_SEL_MSCL0, 4, 1),
3982 MUX(CLK_MOUT_ACLK_MSCL_400_USER, "mout_aclk_mscl_400_user",
3983 mout_aclk_mscl_400_user_p, MUX_SEL_MSCL0, 0, 1),
3986 MUX(CLK_MOUT_SCLK_JPEG, "mout_sclk_jpeg", mout_sclk_jpeg_p,
3987 MUX_SEL_MSCL1, 0, 1),
3990 static const struct samsung_div_clock mscl_div_clks[] __initconst = {
3992 DIV(CLK_DIV_PCLK_MSCL, "div_pclk_mscl", "mout_aclk_mscl_400_user",
3996 static const struct samsung_gate_clock mscl_gate_clks[] __initconst = {
3997 /* ENABLE_ACLK_MSCL */
3998 GATE(CLK_ACLK_BTS_JPEG, "aclk_bts_jpeg", "mout_aclk_mscl_400_user",
3999 ENABLE_ACLK_MSCL, 9, 0, 0),
4000 GATE(CLK_ACLK_BTS_M2MSCALER1, "aclk_bts_m2mscaler1",
4001 "mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 8, 0, 0),
4002 GATE(CLK_ACLK_BTS_M2MSCALER0, "aclk_bts_m2mscaler0",
4003 "mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 7, 0, 0),
4004 GATE(CLK_ACLK_AHB2APB_MSCL0P, "aclk_abh2apb_mscl0p", "div_pclk_mscl",
4005 ENABLE_ACLK_MSCL, 6, CLK_IGNORE_UNUSED, 0),
4006 GATE(CLK_ACLK_XIU_MSCLX, "aclk_xiu_msclx", "mout_aclk_mscl_400_user",
4007 ENABLE_ACLK_MSCL, 5, CLK_IGNORE_UNUSED, 0),
4008 GATE(CLK_ACLK_MSCLNP_100, "aclk_msclnp_100", "div_pclk_mscl",
4009 ENABLE_ACLK_MSCL, 4, CLK_IGNORE_UNUSED, 0),
4010 GATE(CLK_ACLK_MSCLND_400, "aclk_msclnd_400", "mout_aclk_mscl_400_user",
4011 ENABLE_ACLK_MSCL, 3, CLK_IGNORE_UNUSED, 0),
4012 GATE(CLK_ACLK_JPEG, "aclk_jpeg", "mout_aclk_mscl_400_user",
4013 ENABLE_ACLK_MSCL, 2, 0, 0),
4014 GATE(CLK_ACLK_M2MSCALER1, "aclk_m2mscaler1", "mout_aclk_mscl_400_user",
4015 ENABLE_ACLK_MSCL, 1, 0, 0),
4016 GATE(CLK_ACLK_M2MSCALER0, "aclk_m2mscaler0", "mout_aclk_mscl_400_user",
4017 ENABLE_ACLK_MSCL, 0, 0, 0),
4019 /* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0 */
4020 GATE(CLK_ACLK_SMMU_M2MSCALER0, "aclk_smmu_m2mscaler0",
4021 "mout_aclk_mscl_400_user",
4022 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0,
4023 0, CLK_IGNORE_UNUSED, 0),
4025 /* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1 */
4026 GATE(CLK_ACLK_SMMU_M2MSCALER1, "aclk_smmu_m2mscaler1",
4027 "mout_aclk_mscl_400_user",
4028 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1,
4029 0, CLK_IGNORE_UNUSED, 0),
4031 /* ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG */
4032 GATE(CLK_ACLK_SMMU_JPEG, "aclk_smmu_jpeg", "mout_aclk_mscl_400_user",
4033 ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG,
4034 0, CLK_IGNORE_UNUSED, 0),
4036 /* ENABLE_PCLK_MSCL */
4037 GATE(CLK_PCLK_BTS_JPEG, "pclk_bts_jpeg", "div_pclk_mscl",
4038 ENABLE_PCLK_MSCL, 7, 0, 0),
4039 GATE(CLK_PCLK_BTS_M2MSCALER1, "pclk_bts_m2mscaler1", "div_pclk_mscl",
4040 ENABLE_PCLK_MSCL, 6, 0, 0),
4041 GATE(CLK_PCLK_BTS_M2MSCALER0, "pclk_bts_m2mscaler0", "div_pclk_mscl",
4042 ENABLE_PCLK_MSCL, 5, 0, 0),
4043 GATE(CLK_PCLK_PMU_MSCL, "pclk_pmu_mscl", "div_pclk_mscl",
4044 ENABLE_PCLK_MSCL, 4, CLK_IGNORE_UNUSED, 0),
4045 GATE(CLK_PCLK_SYSREG_MSCL, "pclk_sysreg_mscl", "div_pclk_mscl",
4046 ENABLE_PCLK_MSCL, 3, CLK_IGNORE_UNUSED, 0),
4047 GATE(CLK_PCLK_JPEG, "pclk_jpeg", "div_pclk_mscl",
4048 ENABLE_PCLK_MSCL, 2, 0, 0),
4049 GATE(CLK_PCLK_M2MSCALER1, "pclk_m2mscaler1", "div_pclk_mscl",
4050 ENABLE_PCLK_MSCL, 1, 0, 0),
4051 GATE(CLK_PCLK_M2MSCALER0, "pclk_m2mscaler0", "div_pclk_mscl",
4052 ENABLE_PCLK_MSCL, 0, 0, 0),
4054 /* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 */
4055 GATE(CLK_PCLK_SMMU_M2MSCALER0, "pclk_smmu_m2mscaler0", "div_pclk_mscl",
4056 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0,
4057 0, CLK_IGNORE_UNUSED, 0),
4059 /* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 */
4060 GATE(CLK_PCLK_SMMU_M2MSCALER1, "pclk_smmu_m2mscaler1", "div_pclk_mscl",
4061 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1,
4062 0, CLK_IGNORE_UNUSED, 0),
4064 /* ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG */
4065 GATE(CLK_PCLK_SMMU_JPEG, "pclk_smmu_jpeg", "div_pclk_mscl",
4066 ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG,
4067 0, CLK_IGNORE_UNUSED, 0),
4069 /* ENABLE_SCLK_MSCL */
4070 GATE(CLK_SCLK_JPEG, "sclk_jpeg", "mout_sclk_jpeg", ENABLE_SCLK_MSCL, 0,
4071 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
4074 static const struct samsung_cmu_info mscl_cmu_info __initconst = {
4075 .mux_clks = mscl_mux_clks,
4076 .nr_mux_clks = ARRAY_SIZE(mscl_mux_clks),
4077 .div_clks = mscl_div_clks,
4078 .nr_div_clks = ARRAY_SIZE(mscl_div_clks),
4079 .gate_clks = mscl_gate_clks,
4080 .nr_gate_clks = ARRAY_SIZE(mscl_gate_clks),
4081 .nr_clk_ids = MSCL_NR_CLK,
4082 .clk_regs = mscl_clk_regs,
4083 .nr_clk_regs = ARRAY_SIZE(mscl_clk_regs),
4086 static void __init exynos5433_cmu_mscl_init(struct device_node *np)
4088 samsung_cmu_register_one(np, &mscl_cmu_info);
4090 CLK_OF_DECLARE(exynos5433_cmu_mscl, "samsung,exynos5433-cmu-mscl",
4091 exynos5433_cmu_mscl_init);
4094 * Register offset definitions for CMU_MFC
4096 #define MUX_SEL_MFC 0x0200
4097 #define MUX_ENABLE_MFC 0x0300
4098 #define MUX_STAT_MFC 0x0400
4099 #define DIV_MFC 0x0600
4100 #define DIV_STAT_MFC 0x0700
4101 #define ENABLE_ACLK_MFC 0x0800
4102 #define ENABLE_ACLK_MFC_SECURE_SMMU_MFC 0x0804
4103 #define ENABLE_PCLK_MFC 0x0900
4104 #define ENABLE_PCLK_MFC_SECURE_SMMU_MFC 0x0904
4105 #define ENABLE_IP_MFC0 0x0b00
4106 #define ENABLE_IP_MFC1 0x0b04
4107 #define ENABLE_IP_MFC_SECURE_SMMU_MFC 0x0b08
4109 static const unsigned long mfc_clk_regs[] __initconst = {
4114 ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
4116 ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
4119 ENABLE_IP_MFC_SECURE_SMMU_MFC,
4122 PNAME(mout_aclk_mfc_400_user_p) = { "oscclk", "aclk_mfc_400", };
4124 static const struct samsung_mux_clock mfc_mux_clks[] __initconst = {
4126 MUX(CLK_MOUT_ACLK_MFC_400_USER, "mout_aclk_mfc_400_user",
4127 mout_aclk_mfc_400_user_p, MUX_SEL_MFC, 0, 0),
4130 static const struct samsung_div_clock mfc_div_clks[] __initconst = {
4132 DIV(CLK_DIV_PCLK_MFC, "div_pclk_mfc", "mout_aclk_mfc_400_user",
4136 static const struct samsung_gate_clock mfc_gate_clks[] __initconst = {
4137 /* ENABLE_ACLK_MFC */
4138 GATE(CLK_ACLK_BTS_MFC_1, "aclk_bts_mfc_1", "mout_aclk_mfc_400_user",
4139 ENABLE_ACLK_MFC, 6, 0, 0),
4140 GATE(CLK_ACLK_BTS_MFC_0, "aclk_bts_mfc_0", "mout_aclk_mfc_400_user",
4141 ENABLE_ACLK_MFC, 5, 0, 0),
4142 GATE(CLK_ACLK_AHB2APB_MFCP, "aclk_ahb2apb_mfcp", "div_pclk_mfc",
4143 ENABLE_ACLK_MFC, 4, CLK_IGNORE_UNUSED, 0),
4144 GATE(CLK_ACLK_XIU_MFCX, "aclk_xiu_mfcx", "mout_aclk_mfc_400_user",
4145 ENABLE_ACLK_MFC, 3, CLK_IGNORE_UNUSED, 0),
4146 GATE(CLK_ACLK_MFCNP_100, "aclk_mfcnp_100", "div_pclk_mfc",
4147 ENABLE_ACLK_MFC, 2, CLK_IGNORE_UNUSED, 0),
4148 GATE(CLK_ACLK_MFCND_400, "aclk_mfcnd_400", "mout_aclk_mfc_400_user",
4149 ENABLE_ACLK_MFC, 1, CLK_IGNORE_UNUSED, 0),
4150 GATE(CLK_ACLK_MFC, "aclk_mfc", "mout_aclk_mfc_400_user",
4151 ENABLE_ACLK_MFC, 0, 0, 0),
4153 /* ENABLE_ACLK_MFC_SECURE_SMMU_MFC */
4154 GATE(CLK_ACLK_SMMU_MFC_1, "aclk_smmu_mfc_1", "mout_aclk_mfc_400_user",
4155 ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
4156 1, CLK_IGNORE_UNUSED, 0),
4157 GATE(CLK_ACLK_SMMU_MFC_0, "aclk_smmu_mfc_0", "mout_aclk_mfc_400_user",
4158 ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
4159 0, CLK_IGNORE_UNUSED, 0),
4161 /* ENABLE_PCLK_MFC */
4162 GATE(CLK_PCLK_BTS_MFC_1, "pclk_bts_mfc_1", "div_pclk_mfc",
4163 ENABLE_PCLK_MFC, 4, 0, 0),
4164 GATE(CLK_PCLK_BTS_MFC_0, "pclk_bts_mfc_0", "div_pclk_mfc",
4165 ENABLE_PCLK_MFC, 3, 0, 0),
4166 GATE(CLK_PCLK_PMU_MFC, "pclk_pmu_mfc", "div_pclk_mfc",
4167 ENABLE_PCLK_MFC, 2, CLK_IGNORE_UNUSED, 0),
4168 GATE(CLK_PCLK_SYSREG_MFC, "pclk_sysreg_mfc", "div_pclk_mfc",
4169 ENABLE_PCLK_MFC, 1, CLK_IGNORE_UNUSED, 0),
4170 GATE(CLK_PCLK_MFC, "pclk_mfc", "div_pclk_mfc",
4171 ENABLE_PCLK_MFC, 4, CLK_IGNORE_UNUSED, 0),
4173 /* ENABLE_PCLK_MFC_SECURE_SMMU_MFC */
4174 GATE(CLK_PCLK_SMMU_MFC_1, "pclk_smmu_mfc_1", "div_pclk_mfc",
4175 ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
4176 1, CLK_IGNORE_UNUSED, 0),
4177 GATE(CLK_PCLK_SMMU_MFC_0, "pclk_smmu_mfc_0", "div_pclk_mfc",
4178 ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
4179 0, CLK_IGNORE_UNUSED, 0),
4182 static const struct samsung_cmu_info mfc_cmu_info __initconst = {
4183 .mux_clks = mfc_mux_clks,
4184 .nr_mux_clks = ARRAY_SIZE(mfc_mux_clks),
4185 .div_clks = mfc_div_clks,
4186 .nr_div_clks = ARRAY_SIZE(mfc_div_clks),
4187 .gate_clks = mfc_gate_clks,
4188 .nr_gate_clks = ARRAY_SIZE(mfc_gate_clks),
4189 .nr_clk_ids = MFC_NR_CLK,
4190 .clk_regs = mfc_clk_regs,
4191 .nr_clk_regs = ARRAY_SIZE(mfc_clk_regs),
4194 static void __init exynos5433_cmu_mfc_init(struct device_node *np)
4196 samsung_cmu_register_one(np, &mfc_cmu_info);
4198 CLK_OF_DECLARE(exynos5433_cmu_mfc, "samsung,exynos5433-cmu-mfc",
4199 exynos5433_cmu_mfc_init);
4202 * Register offset definitions for CMU_HEVC
4204 #define MUX_SEL_HEVC 0x0200
4205 #define MUX_ENABLE_HEVC 0x0300
4206 #define MUX_STAT_HEVC 0x0400
4207 #define DIV_HEVC 0x0600
4208 #define DIV_STAT_HEVC 0x0700
4209 #define ENABLE_ACLK_HEVC 0x0800
4210 #define ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC 0x0804
4211 #define ENABLE_PCLK_HEVC 0x0900
4212 #define ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC 0x0904
4213 #define ENABLE_IP_HEVC0 0x0b00
4214 #define ENABLE_IP_HEVC1 0x0b04
4215 #define ENABLE_IP_HEVC_SECURE_SMMU_HEVC 0x0b08
4217 static const unsigned long hevc_clk_regs[] __initconst = {
4222 ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
4224 ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
4227 ENABLE_IP_HEVC_SECURE_SMMU_HEVC,
4230 PNAME(mout_aclk_hevc_400_user_p) = { "oscclk", "aclk_hevc_400", };
4232 static const struct samsung_mux_clock hevc_mux_clks[] __initconst = {
4234 MUX(CLK_MOUT_ACLK_HEVC_400_USER, "mout_aclk_hevc_400_user",
4235 mout_aclk_hevc_400_user_p, MUX_SEL_HEVC, 0, 0),
4238 static const struct samsung_div_clock hevc_div_clks[] __initconst = {
4240 DIV(CLK_DIV_PCLK_HEVC, "div_pclk_hevc", "mout_aclk_hevc_400_user",
4244 static const struct samsung_gate_clock hevc_gate_clks[] __initconst = {
4245 /* ENABLE_ACLK_HEVC */
4246 GATE(CLK_ACLK_BTS_HEVC_1, "aclk_bts_hevc_1", "mout_aclk_hevc_400_user",
4247 ENABLE_ACLK_HEVC, 6, 0, 0),
4248 GATE(CLK_ACLK_BTS_HEVC_0, "aclk_bts_hevc_0", "mout_aclk_hevc_400_user",
4249 ENABLE_ACLK_HEVC, 5, 0, 0),
4250 GATE(CLK_ACLK_AHB2APB_HEVCP, "aclk_ahb2apb_hevcp", "div_pclk_hevc",
4251 ENABLE_ACLK_HEVC, 4, CLK_IGNORE_UNUSED, 0),
4252 GATE(CLK_ACLK_XIU_HEVCX, "aclk_xiu_hevcx", "mout_aclk_hevc_400_user",
4253 ENABLE_ACLK_HEVC, 3, CLK_IGNORE_UNUSED, 0),
4254 GATE(CLK_ACLK_HEVCNP_100, "aclk_hevcnp_100", "div_pclk_hevc",
4255 ENABLE_ACLK_HEVC, 2, CLK_IGNORE_UNUSED, 0),
4256 GATE(CLK_ACLK_HEVCND_400, "aclk_hevcnd_400", "mout_aclk_hevc_400_user",
4257 ENABLE_ACLK_HEVC, 1, CLK_IGNORE_UNUSED, 0),
4258 GATE(CLK_ACLK_HEVC, "aclk_hevc", "mout_aclk_hevc_400_user",
4259 ENABLE_ACLK_HEVC, 0, 0, 0),
4261 /* ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC */
4262 GATE(CLK_ACLK_SMMU_HEVC_1, "aclk_smmu_hevc_1",
4263 "mout_aclk_hevc_400_user",
4264 ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
4265 1, CLK_IGNORE_UNUSED, 0),
4266 GATE(CLK_ACLK_SMMU_HEVC_0, "aclk_smmu_hevc_0",
4267 "mout_aclk_hevc_400_user",
4268 ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
4269 0, CLK_IGNORE_UNUSED, 0),
4271 /* ENABLE_PCLK_HEVC */
4272 GATE(CLK_PCLK_BTS_HEVC_1, "pclk_bts_hevc_1", "div_pclk_hevc",
4273 ENABLE_PCLK_HEVC, 4, 0, 0),
4274 GATE(CLK_PCLK_BTS_HEVC_0, "pclk_bts_hevc_0", "div_pclk_hevc",
4275 ENABLE_PCLK_HEVC, 3, 0, 0),
4276 GATE(CLK_PCLK_PMU_HEVC, "pclk_pmu_hevc", "div_pclk_hevc",
4277 ENABLE_PCLK_HEVC, 2, CLK_IGNORE_UNUSED, 0),
4278 GATE(CLK_PCLK_SYSREG_HEVC, "pclk_sysreg_hevc", "div_pclk_hevc",
4279 ENABLE_PCLK_HEVC, 1, CLK_IGNORE_UNUSED, 0),
4280 GATE(CLK_PCLK_HEVC, "pclk_hevc", "div_pclk_hevc",
4281 ENABLE_PCLK_HEVC, 4, CLK_IGNORE_UNUSED, 0),
4283 /* ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC */
4284 GATE(CLK_PCLK_SMMU_HEVC_1, "pclk_smmu_hevc_1", "div_pclk_hevc",
4285 ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
4286 1, CLK_IGNORE_UNUSED, 0),
4287 GATE(CLK_PCLK_SMMU_HEVC_0, "pclk_smmu_hevc_0", "div_pclk_hevc",
4288 ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
4289 0, CLK_IGNORE_UNUSED, 0),
4292 static const struct samsung_cmu_info hevc_cmu_info __initconst = {
4293 .mux_clks = hevc_mux_clks,
4294 .nr_mux_clks = ARRAY_SIZE(hevc_mux_clks),
4295 .div_clks = hevc_div_clks,
4296 .nr_div_clks = ARRAY_SIZE(hevc_div_clks),
4297 .gate_clks = hevc_gate_clks,
4298 .nr_gate_clks = ARRAY_SIZE(hevc_gate_clks),
4299 .nr_clk_ids = HEVC_NR_CLK,
4300 .clk_regs = hevc_clk_regs,
4301 .nr_clk_regs = ARRAY_SIZE(hevc_clk_regs),
4304 static void __init exynos5433_cmu_hevc_init(struct device_node *np)
4306 samsung_cmu_register_one(np, &hevc_cmu_info);
4308 CLK_OF_DECLARE(exynos5433_cmu_hevc, "samsung,exynos5433-cmu-hevc",
4309 exynos5433_cmu_hevc_init);
4312 * Register offset definitions for CMU_ISP
4314 #define MUX_SEL_ISP 0x0200
4315 #define MUX_ENABLE_ISP 0x0300
4316 #define MUX_STAT_ISP 0x0400
4317 #define DIV_ISP 0x0600
4318 #define DIV_STAT_ISP 0x0700
4319 #define ENABLE_ACLK_ISP0 0x0800
4320 #define ENABLE_ACLK_ISP1 0x0804
4321 #define ENABLE_ACLK_ISP2 0x0808
4322 #define ENABLE_PCLK_ISP 0x0900
4323 #define ENABLE_SCLK_ISP 0x0a00
4324 #define ENABLE_IP_ISP0 0x0b00
4325 #define ENABLE_IP_ISP1 0x0b04
4326 #define ENABLE_IP_ISP2 0x0b08
4327 #define ENABLE_IP_ISP3 0x0b0c
4329 static const unsigned long isp_clk_regs[] __initconst = {
4344 PNAME(mout_aclk_isp_dis_400_user_p) = { "oscclk", "aclk_isp_dis_400", };
4345 PNAME(mout_aclk_isp_400_user_p) = { "oscclk", "aclk_isp_400", };
4347 static const struct samsung_mux_clock isp_mux_clks[] __initconst = {
4349 MUX(CLK_MOUT_ACLK_ISP_DIS_400_USER, "mout_aclk_isp_dis_400_user",
4350 mout_aclk_isp_dis_400_user_p, MUX_SEL_ISP, 4, 0),
4351 MUX(CLK_MOUT_ACLK_ISP_400_USER, "mout_aclk_isp_400_user",
4352 mout_aclk_isp_400_user_p, MUX_SEL_ISP, 0, 0),
4355 static const struct samsung_div_clock isp_div_clks[] __initconst = {
4357 DIV(CLK_DIV_PCLK_ISP_DIS, "div_pclk_isp_dis",
4358 "mout_aclk_isp_dis_400_user", DIV_ISP, 12, 3),
4359 DIV(CLK_DIV_PCLK_ISP, "div_pclk_isp", "mout_aclk_isp_400_user",
4361 DIV(CLK_DIV_ACLK_ISP_D_200, "div_aclk_isp_d_200",
4362 "mout_aclk_isp_400_user", DIV_ISP, 4, 3),
4363 DIV(CLK_DIV_ACLK_ISP_C_200, "div_aclk_isp_c_200",
4364 "mout_aclk_isp_400_user", DIV_ISP, 0, 3),
4367 static const struct samsung_gate_clock isp_gate_clks[] __initconst = {
4368 /* ENABLE_ACLK_ISP0 */
4369 GATE(CLK_ACLK_ISP_D_GLUE, "aclk_isp_d_glue", "mout_aclk_isp_400_user",
4370 ENABLE_ACLK_ISP0, 6, CLK_IGNORE_UNUSED, 0),
4371 GATE(CLK_ACLK_SCALERP, "aclk_scalerp", "mout_aclk_isp_400_user",
4372 ENABLE_ACLK_ISP0, 5, 0, 0),
4373 GATE(CLK_ACLK_3DNR, "aclk_3dnr", "mout_aclk_isp_400_user",
4374 ENABLE_ACLK_ISP0, 4, 0, 0),
4375 GATE(CLK_ACLK_DIS, "aclk_dis", "mout_aclk_isp_dis_400_user",
4376 ENABLE_ACLK_ISP0, 3, 0, 0),
4377 GATE(CLK_ACLK_SCALERC, "aclk_scalerc", "mout_aclk_isp_400_user",
4378 ENABLE_ACLK_ISP0, 2, 0, 0),
4379 GATE(CLK_ACLK_DRC, "aclk_drc", "mout_aclk_isp_400_user",
4380 ENABLE_ACLK_ISP0, 1, 0, 0),
4381 GATE(CLK_ACLK_ISP, "aclk_isp", "mout_aclk_isp_400_user",
4382 ENABLE_ACLK_ISP0, 0, 0, 0),
4384 /* ENABLE_ACLK_ISP1 */
4385 GATE(CLK_ACLK_AXIUS_SCALERP, "aclk_axius_scalerp",
4386 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4387 17, CLK_IGNORE_UNUSED, 0),
4388 GATE(CLK_ACLK_AXIUS_SCALERC, "aclk_axius_scalerc",
4389 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4390 16, CLK_IGNORE_UNUSED, 0),
4391 GATE(CLK_ACLK_AXIUS_DRC, "aclk_axius_drc",
4392 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4393 15, CLK_IGNORE_UNUSED, 0),
4394 GATE(CLK_ACLK_ASYNCAHBM_ISP2P, "aclk_asyncahbm_isp2p",
4395 "div_pclk_isp", ENABLE_ACLK_ISP1,
4396 14, CLK_IGNORE_UNUSED, 0),
4397 GATE(CLK_ACLK_ASYNCAHBM_ISP1P, "aclk_asyncahbm_isp1p",
4398 "div_pclk_isp", ENABLE_ACLK_ISP1,
4399 13, CLK_IGNORE_UNUSED, 0),
4400 GATE(CLK_ACLK_ASYNCAXIS_DIS1, "aclk_asyncaxis_dis1",
4401 "mout_aclk_isp_dis_400_user", ENABLE_ACLK_ISP1,
4402 12, CLK_IGNORE_UNUSED, 0),
4403 GATE(CLK_ACLK_ASYNCAXIS_DIS0, "aclk_asyncaxis_dis0",
4404 "mout_aclk_isp_dis_400_user", ENABLE_ACLK_ISP1,
4405 11, CLK_IGNORE_UNUSED, 0),
4406 GATE(CLK_ACLK_ASYNCAXIM_DIS1, "aclk_asyncaxim_dis1",
4407 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4408 10, CLK_IGNORE_UNUSED, 0),
4409 GATE(CLK_ACLK_ASYNCAXIM_DIS0, "aclk_asyncaxim_dis0",
4410 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4411 9, CLK_IGNORE_UNUSED, 0),
4412 GATE(CLK_ACLK_ASYNCAXIM_ISP2P, "aclk_asyncaxim_isp2p",
4413 "div_aclk_isp_d_200", ENABLE_ACLK_ISP1,
4414 8, CLK_IGNORE_UNUSED, 0),
4415 GATE(CLK_ACLK_ASYNCAXIM_ISP1P, "aclk_asyncaxim_isp1p",
4416 "div_aclk_isp_c_200", ENABLE_ACLK_ISP1,
4417 7, CLK_IGNORE_UNUSED, 0),
4418 GATE(CLK_ACLK_AHB2APB_ISP2P, "aclk_ahb2apb_isp2p", "div_pclk_isp",
4419 ENABLE_ACLK_ISP1, 6, CLK_IGNORE_UNUSED, 0),
4420 GATE(CLK_ACLK_AHB2APB_ISP1P, "aclk_ahb2apb_isp1p", "div_pclk_isp",
4421 ENABLE_ACLK_ISP1, 5, CLK_IGNORE_UNUSED, 0),
4422 GATE(CLK_ACLK_AXI2APB_ISP2P, "aclk_axi2apb_isp2p",
4423 "div_aclk_isp_d_200", ENABLE_ACLK_ISP1,
4424 4, CLK_IGNORE_UNUSED, 0),
4425 GATE(CLK_ACLK_AXI2APB_ISP1P, "aclk_axi2apb_isp1p",
4426 "div_aclk_isp_c_200", ENABLE_ACLK_ISP1,
4427 3, CLK_IGNORE_UNUSED, 0),
4428 GATE(CLK_ACLK_XIU_ISPEX1, "aclk_xiu_ispex1", "mout_aclk_isp_400_user",
4429 ENABLE_ACLK_ISP1, 2, CLK_IGNORE_UNUSED, 0),
4430 GATE(CLK_ACLK_XIU_ISPEX0, "aclk_xiu_ispex0", "mout_aclk_isp_400_user",
4431 ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0),
4432 GATE(CLK_ACLK_ISPND_400, "aclk_ispnd_400", "mout_aclk_isp_400_user",
4433 ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0),
4435 /* ENABLE_ACLK_ISP2 */
4436 GATE(CLK_ACLK_SMMU_SCALERP, "aclk_smmu_scalerp",
4437 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
4438 13, CLK_IGNORE_UNUSED, 0),
4439 GATE(CLK_ACLK_SMMU_3DNR, "aclk_smmu_3dnr", "mout_aclk_isp_400_user",
4440 ENABLE_ACLK_ISP2, 12, CLK_IGNORE_UNUSED, 0),
4441 GATE(CLK_ACLK_SMMU_DIS1, "aclk_smmu_dis1", "mout_aclk_isp_400_user",
4442 ENABLE_ACLK_ISP2, 11, CLK_IGNORE_UNUSED, 0),
4443 GATE(CLK_ACLK_SMMU_DIS0, "aclk_smmu_dis0", "mout_aclk_isp_400_user",
4444 ENABLE_ACLK_ISP2, 10, CLK_IGNORE_UNUSED, 0),
4445 GATE(CLK_ACLK_SMMU_SCALERC, "aclk_smmu_scalerc",
4446 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
4447 9, CLK_IGNORE_UNUSED, 0),
4448 GATE(CLK_ACLK_SMMU_DRC, "aclk_smmu_drc", "mout_aclk_isp_400_user",
4449 ENABLE_ACLK_ISP2, 8, CLK_IGNORE_UNUSED, 0),
4450 GATE(CLK_ACLK_SMMU_ISP, "aclk_smmu_isp", "mout_aclk_isp_400_user",
4451 ENABLE_ACLK_ISP2, 7, CLK_IGNORE_UNUSED, 0),
4452 GATE(CLK_ACLK_BTS_SCALERP, "aclk_bts_scalerp",
4453 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
4454 6, CLK_IGNORE_UNUSED, 0),
4455 GATE(CLK_ACLK_BTS_3DR, "aclk_bts_3dnr", "mout_aclk_isp_400_user",
4456 ENABLE_ACLK_ISP2, 5, CLK_IGNORE_UNUSED, 0),
4457 GATE(CLK_ACLK_BTS_DIS1, "aclk_bts_dis1", "mout_aclk_isp_400_user",
4458 ENABLE_ACLK_ISP2, 4, CLK_IGNORE_UNUSED, 0),
4459 GATE(CLK_ACLK_BTS_DIS0, "aclk_bts_dis0", "mout_aclk_isp_400_user",
4460 ENABLE_ACLK_ISP2, 3, CLK_IGNORE_UNUSED, 0),
4461 GATE(CLK_ACLK_BTS_SCALERC, "aclk_bts_scalerc",
4462 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
4463 2, CLK_IGNORE_UNUSED, 0),
4464 GATE(CLK_ACLK_BTS_DRC, "aclk_bts_drc", "mout_aclk_isp_400_user",
4465 ENABLE_ACLK_ISP2, 1, CLK_IGNORE_UNUSED, 0),
4466 GATE(CLK_ACLK_BTS_ISP, "aclk_bts_isp", "mout_aclk_isp_400_user",
4467 ENABLE_ACLK_ISP2, 0, CLK_IGNORE_UNUSED, 0),
4469 /* ENABLE_PCLK_ISP */
4470 GATE(CLK_PCLK_SMMU_SCALERP, "pclk_smmu_scalerp", "div_aclk_isp_d_200",
4471 ENABLE_PCLK_ISP, 25, CLK_IGNORE_UNUSED, 0),
4472 GATE(CLK_PCLK_SMMU_3DNR, "pclk_smmu_3dnr", "div_aclk_isp_d_200",
4473 ENABLE_PCLK_ISP, 24, CLK_IGNORE_UNUSED, 0),
4474 GATE(CLK_PCLK_SMMU_DIS1, "pclk_smmu_dis1", "div_aclk_isp_d_200",
4475 ENABLE_PCLK_ISP, 23, CLK_IGNORE_UNUSED, 0),
4476 GATE(CLK_PCLK_SMMU_DIS0, "pclk_smmu_dis0", "div_aclk_isp_d_200",
4477 ENABLE_PCLK_ISP, 22, CLK_IGNORE_UNUSED, 0),
4478 GATE(CLK_PCLK_SMMU_SCALERC, "pclk_smmu_scalerc", "div_aclk_isp_c_200",
4479 ENABLE_PCLK_ISP, 21, CLK_IGNORE_UNUSED, 0),
4480 GATE(CLK_PCLK_SMMU_DRC, "pclk_smmu_drc", "div_aclk_isp_c_200",
4481 ENABLE_PCLK_ISP, 20, CLK_IGNORE_UNUSED, 0),
4482 GATE(CLK_PCLK_SMMU_ISP, "pclk_smmu_isp", "div_aclk_isp_c_200",
4483 ENABLE_PCLK_ISP, 19, CLK_IGNORE_UNUSED, 0),
4484 GATE(CLK_PCLK_BTS_SCALERP, "pclk_bts_scalerp", "div_pclk_isp",
4485 ENABLE_PCLK_ISP, 18, CLK_IGNORE_UNUSED, 0),
4486 GATE(CLK_PCLK_BTS_3DNR, "pclk_bts_3dnr", "div_pclk_isp",
4487 ENABLE_PCLK_ISP, 17, CLK_IGNORE_UNUSED, 0),
4488 GATE(CLK_PCLK_BTS_DIS1, "pclk_bts_dis1", "div_pclk_isp",
4489 ENABLE_PCLK_ISP, 16, CLK_IGNORE_UNUSED, 0),
4490 GATE(CLK_PCLK_BTS_DIS0, "pclk_bts_dis0", "div_pclk_isp",
4491 ENABLE_PCLK_ISP, 15, CLK_IGNORE_UNUSED, 0),
4492 GATE(CLK_PCLK_BTS_SCALERC, "pclk_bts_scalerc", "div_pclk_isp",
4493 ENABLE_PCLK_ISP, 14, CLK_IGNORE_UNUSED, 0),
4494 GATE(CLK_PCLK_BTS_DRC, "pclk_bts_drc", "div_pclk_isp",
4495 ENABLE_PCLK_ISP, 13, CLK_IGNORE_UNUSED, 0),
4496 GATE(CLK_PCLK_BTS_ISP, "pclk_bts_isp", "div_pclk_isp",
4497 ENABLE_PCLK_ISP, 12, CLK_IGNORE_UNUSED, 0),
4498 GATE(CLK_PCLK_ASYNCAXI_DIS1, "pclk_asyncaxi_dis1", "div_pclk_isp",
4499 ENABLE_PCLK_ISP, 11, CLK_IGNORE_UNUSED, 0),
4500 GATE(CLK_PCLK_ASYNCAXI_DIS0, "pclk_asyncaxi_dis0", "div_pclk_isp",
4501 ENABLE_PCLK_ISP, 10, CLK_IGNORE_UNUSED, 0),
4502 GATE(CLK_PCLK_PMU_ISP, "pclk_pmu_isp", "div_pclk_isp",
4503 ENABLE_PCLK_ISP, 9, CLK_IGNORE_UNUSED, 0),
4504 GATE(CLK_PCLK_SYSREG_ISP, "pclk_sysreg_isp", "div_pclk_isp",
4505 ENABLE_PCLK_ISP, 8, CLK_IGNORE_UNUSED, 0),
4506 GATE(CLK_PCLK_CMU_ISP_LOCAL, "pclk_cmu_isp_local",
4507 "div_aclk_isp_c_200", ENABLE_PCLK_ISP,
4508 7, CLK_IGNORE_UNUSED, 0),
4509 GATE(CLK_PCLK_SCALERP, "pclk_scalerp", "div_aclk_isp_d_200",
4510 ENABLE_PCLK_ISP, 6, CLK_IGNORE_UNUSED, 0),
4511 GATE(CLK_PCLK_3DNR, "pclk_3dnr", "div_aclk_isp_d_200",
4512 ENABLE_PCLK_ISP, 5, CLK_IGNORE_UNUSED, 0),
4513 GATE(CLK_PCLK_DIS_CORE, "pclk_dis_core", "div_pclk_isp_dis",
4514 ENABLE_PCLK_ISP, 4, CLK_IGNORE_UNUSED, 0),
4515 GATE(CLK_PCLK_DIS, "pclk_dis", "div_aclk_isp_d_200",
4516 ENABLE_PCLK_ISP, 3, CLK_IGNORE_UNUSED, 0),
4517 GATE(CLK_PCLK_SCALERC, "pclk_scalerc", "div_aclk_isp_c_200",
4518 ENABLE_PCLK_ISP, 2, CLK_IGNORE_UNUSED, 0),
4519 GATE(CLK_PCLK_DRC, "pclk_drc", "div_aclk_isp_c_200",
4520 ENABLE_PCLK_ISP, 1, CLK_IGNORE_UNUSED, 0),
4521 GATE(CLK_PCLK_ISP, "pclk_isp", "div_aclk_isp_c_200",
4522 ENABLE_PCLK_ISP, 0, CLK_IGNORE_UNUSED, 0),
4524 /* ENABLE_SCLK_ISP */
4525 GATE(CLK_SCLK_PIXELASYNCS_DIS, "sclk_pixelasyncs_dis",
4526 "mout_aclk_isp_dis_400_user", ENABLE_SCLK_ISP,
4527 5, CLK_IGNORE_UNUSED, 0),
4528 GATE(CLK_SCLK_PIXELASYNCM_DIS, "sclk_pixelasyncm_dis",
4529 "mout_aclk_isp_dis_400_user", ENABLE_SCLK_ISP,
4530 4, CLK_IGNORE_UNUSED, 0),
4531 GATE(CLK_SCLK_PIXELASYNCS_SCALERP, "sclk_pixelasyncs_scalerp",
4532 "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
4533 3, CLK_IGNORE_UNUSED, 0),
4534 GATE(CLK_SCLK_PIXELASYNCM_ISPD, "sclk_pixelasyncm_ispd",
4535 "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
4536 2, CLK_IGNORE_UNUSED, 0),
4537 GATE(CLK_SCLK_PIXELASYNCS_ISPC, "sclk_pixelasyncs_ispc",
4538 "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
4539 1, CLK_IGNORE_UNUSED, 0),
4540 GATE(CLK_SCLK_PIXELASYNCM_ISPC, "sclk_pixelasyncm_ispc",
4541 "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
4542 0, CLK_IGNORE_UNUSED, 0),
4545 static const struct samsung_cmu_info isp_cmu_info __initconst = {
4546 .mux_clks = isp_mux_clks,
4547 .nr_mux_clks = ARRAY_SIZE(isp_mux_clks),
4548 .div_clks = isp_div_clks,
4549 .nr_div_clks = ARRAY_SIZE(isp_div_clks),
4550 .gate_clks = isp_gate_clks,
4551 .nr_gate_clks = ARRAY_SIZE(isp_gate_clks),
4552 .nr_clk_ids = ISP_NR_CLK,
4553 .clk_regs = isp_clk_regs,
4554 .nr_clk_regs = ARRAY_SIZE(isp_clk_regs),
4557 static void __init exynos5433_cmu_isp_init(struct device_node *np)
4559 samsung_cmu_register_one(np, &isp_cmu_info);
4561 CLK_OF_DECLARE(exynos5433_cmu_isp, "samsung,exynos5433-cmu-isp",
4562 exynos5433_cmu_isp_init);
4565 * Register offset definitions for CMU_CAM0
4567 #define MUX_SEL_CAM00 0x0200
4568 #define MUX_SEL_CAM01 0x0204
4569 #define MUX_SEL_CAM02 0x0208
4570 #define MUX_SEL_CAM03 0x020c
4571 #define MUX_SEL_CAM04 0x0210
4572 #define MUX_ENABLE_CAM00 0x0300
4573 #define MUX_ENABLE_CAM01 0x0304
4574 #define MUX_ENABLE_CAM02 0x0308
4575 #define MUX_ENABLE_CAM03 0x030c
4576 #define MUX_ENABLE_CAM04 0x0310
4577 #define MUX_STAT_CAM00 0x0400
4578 #define MUX_STAT_CAM01 0x0404
4579 #define MUX_STAT_CAM02 0x0408
4580 #define MUX_STAT_CAM03 0x040c
4581 #define MUX_STAT_CAM04 0x0410
4582 #define MUX_IGNORE_CAM01 0x0504
4583 #define DIV_CAM00 0x0600
4584 #define DIV_CAM01 0x0604
4585 #define DIV_CAM02 0x0608
4586 #define DIV_CAM03 0x060c
4587 #define DIV_STAT_CAM00 0x0700
4588 #define DIV_STAT_CAM01 0x0704
4589 #define DIV_STAT_CAM02 0x0708
4590 #define DIV_STAT_CAM03 0x070c
4591 #define ENABLE_ACLK_CAM00 0X0800
4592 #define ENABLE_ACLK_CAM01 0X0804
4593 #define ENABLE_ACLK_CAM02 0X0808
4594 #define ENABLE_PCLK_CAM0 0X0900
4595 #define ENABLE_SCLK_CAM0 0X0a00
4596 #define ENABLE_IP_CAM00 0X0b00
4597 #define ENABLE_IP_CAM01 0X0b04
4598 #define ENABLE_IP_CAM02 0X0b08
4599 #define ENABLE_IP_CAM03 0X0b0C
4601 static const unsigned long cam0_clk_regs[] __initconst = {
4627 PNAME(mout_aclk_cam0_333_user_p) = { "oscclk", "aclk_cam0_333", };
4628 PNAME(mout_aclk_cam0_400_user_p) = { "oscclk", "aclk_cam0_400", };
4629 PNAME(mout_aclk_cam0_552_user_p) = { "oscclk", "aclk_cam0_552", };
4631 PNAME(mout_phyclk_rxbyteclkhs0_s4_user_p) = { "oscclk",
4632 "phyclk_rxbyteclkhs0_s4_phy", };
4633 PNAME(mout_phyclk_rxbyteclkhs0_s2a_user_p) = { "oscclk",
4634 "phyclk_rxbyteclkhs0_s2a_phy", };
4636 PNAME(mout_aclk_lite_d_b_p) = { "mout_aclk_lite_d_a",
4637 "mout_aclk_cam0_333_user", };
4638 PNAME(mout_aclk_lite_d_a_p) = { "mout_aclk_cam0_552_user",
4639 "mout_aclk_cam0_400_user", };
4640 PNAME(mout_aclk_lite_b_b_p) = { "mout_aclk_lite_b_a",
4641 "mout_aclk_cam0_333_user", };
4642 PNAME(mout_aclk_lite_b_a_p) = { "mout_aclk_cam0_552_user",
4643 "mout_aclk_cam0_400_user", };
4644 PNAME(mout_aclk_lite_a_b_p) = { "mout_aclk_lite_a_a",
4645 "mout_aclk_cam0_333_user", };
4646 PNAME(mout_aclk_lite_a_a_p) = { "mout_aclk_cam0_552_user",
4647 "mout_aclk_cam0_400_user", };
4648 PNAME(mout_aclk_cam0_400_p) = { "mout_aclk_cam0_400_user",
4649 "mout_aclk_cam0_333_user", };
4651 PNAME(mout_aclk_csis1_b_p) = { "mout_aclk_csis1_a",
4652 "mout_aclk_cam0_333_user" };
4653 PNAME(mout_aclk_csis1_a_p) = { "mout_aclk_cam0_552_user",
4654 "mout_aclk_cam0_400_user", };
4655 PNAME(mout_aclk_csis0_b_p) = { "mout_aclk_csis0_a",
4656 "mout_aclk_cam0_333_user", };
4657 PNAME(mout_aclk_csis0_a_p) = { "mout_aclk_cam0_552_user",
4658 "mout_aclk-cam0_400_user", };
4659 PNAME(mout_aclk_3aa1_b_p) = { "mout_aclk_3aa1_a",
4660 "mout_aclk_cam0_333_user", };
4661 PNAME(mout_aclk_3aa1_a_p) = { "mout_aclk_cam0_552_user",
4662 "mout_aclk_cam0_400_user", };
4663 PNAME(mout_aclk_3aa0_b_p) = { "mout_aclk_3aa0_a",
4664 "mout_aclk_cam0_333_user", };
4665 PNAME(mout_aclk_3aa0_a_p) = { "mout_aclk_cam0_552_user",
4666 "mout_aclk_cam0_400_user", };
4668 PNAME(mout_sclk_lite_freecnt_c_p) = { "mout_sclk_lite_freecnt_b",
4669 "div_pclk_lite_d", };
4670 PNAME(mout_sclk_lite_freecnt_b_p) = { "mout_sclk_lite_freecnt_a",
4671 "div_pclk_pixelasync_lite_c", };
4672 PNAME(mout_sclk_lite_freecnt_a_p) = { "div_pclk_lite_a",
4673 "div_pclk_lite_b", };
4674 PNAME(mout_sclk_pixelasync_lite_c_b_p) = { "mout_sclk_pixelasync_lite_c_a",
4675 "mout_aclk_cam0_333_user", };
4676 PNAME(mout_sclk_pixelasync_lite_c_a_p) = { "mout_aclk_cam0_552_user",
4677 "mout_aclk_cam0_400_user", };
4678 PNAME(mout_sclk_pixelasync_lite_c_init_b_p) = {
4679 "mout_sclk_pixelasync_lite_c_init_a",
4680 "mout_aclk_cam0_400_user", };
4681 PNAME(mout_sclk_pixelasync_lite_c_init_a_p) = {
4682 "mout_aclk_cam0_552_user",
4683 "mout_aclk_cam0_400_user", };
4685 static const struct samsung_fixed_rate_clock cam0_fixed_clks[] __initconst = {
4686 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY, "phyclk_rxbyteclkhs0_s4_phy",
4687 NULL, 0, 100000000),
4688 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY, "phyclk_rxbyteclkhs0_s2a_phy",
4689 NULL, 0, 100000000),
4692 static const struct samsung_mux_clock cam0_mux_clks[] __initconst = {
4694 MUX(CLK_MOUT_ACLK_CAM0_333_USER, "mout_aclk_cam0_333_user",
4695 mout_aclk_cam0_333_user_p, MUX_SEL_CAM00, 8, 1),
4696 MUX(CLK_MOUT_ACLK_CAM0_400_USER, "mout_aclk_cam0_400_user",
4697 mout_aclk_cam0_400_user_p, MUX_SEL_CAM00, 4, 1),
4698 MUX(CLK_MOUT_ACLK_CAM0_552_USER, "mout_aclk_cam0_552_user",
4699 mout_aclk_cam0_552_user_p, MUX_SEL_CAM00, 0, 1),
4702 MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S4_USER,
4703 "mout_phyclk_rxbyteclkhs0_s4_user",
4704 mout_phyclk_rxbyteclkhs0_s4_user_p,
4705 MUX_SEL_CAM01, 4, 1),
4706 MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2A_USER,
4707 "mout_phyclk_rxbyteclkhs0_s2a_user",
4708 mout_phyclk_rxbyteclkhs0_s2a_user_p,
4709 MUX_SEL_CAM01, 0, 1),
4712 MUX(CLK_MOUT_ACLK_LITE_D_B, "mout_aclk_lite_d_b", mout_aclk_lite_d_b_p,
4713 MUX_SEL_CAM02, 24, 1),
4714 MUX(CLK_MOUT_ACLK_LITE_D_A, "mout_aclk_lite_d_a", mout_aclk_lite_d_a_p,
4715 MUX_SEL_CAM02, 20, 1),
4716 MUX(CLK_MOUT_ACLK_LITE_B_B, "mout_aclk_lite_b_b", mout_aclk_lite_b_b_p,
4717 MUX_SEL_CAM02, 16, 1),
4718 MUX(CLK_MOUT_ACLK_LITE_B_A, "mout_aclk_lite_b_a", mout_aclk_lite_b_a_p,
4719 MUX_SEL_CAM02, 12, 1),
4720 MUX(CLK_MOUT_ACLK_LITE_A_B, "mout_aclk_lite_a_b", mout_aclk_lite_a_b_p,
4721 MUX_SEL_CAM02, 8, 1),
4722 MUX(CLK_MOUT_ACLK_LITE_A_A, "mout_aclk_lite_a_a", mout_aclk_lite_a_a_p,
4723 MUX_SEL_CAM02, 4, 1),
4724 MUX(CLK_MOUT_ACLK_CAM0_400, "mout_aclk_cam0_400", mout_aclk_cam0_400_p,
4725 MUX_SEL_CAM02, 0, 1),
4728 MUX(CLK_MOUT_ACLK_CSIS1_B, "mout_aclk_csis1_b", mout_aclk_csis1_b_p,
4729 MUX_SEL_CAM03, 28, 1),
4730 MUX(CLK_MOUT_ACLK_CSIS1_A, "mout_aclk_csis1_a", mout_aclk_csis1_a_p,
4731 MUX_SEL_CAM03, 24, 1),
4732 MUX(CLK_MOUT_ACLK_CSIS0_B, "mout_aclk_csis0_b", mout_aclk_csis0_b_p,
4733 MUX_SEL_CAM03, 20, 1),
4734 MUX(CLK_MOUT_ACLK_CSIS0_A, "mout_aclk_csis0_a", mout_aclk_csis0_a_p,
4735 MUX_SEL_CAM03, 16, 1),
4736 MUX(CLK_MOUT_ACLK_3AA1_B, "mout_aclk_3aa1_b", mout_aclk_3aa1_b_p,
4737 MUX_SEL_CAM03, 12, 1),
4738 MUX(CLK_MOUT_ACLK_3AA1_A, "mout_aclk_3aa1_a", mout_aclk_3aa1_a_p,
4739 MUX_SEL_CAM03, 8, 1),
4740 MUX(CLK_MOUT_ACLK_3AA0_B, "mout_aclk_3aa0_b", mout_aclk_3aa0_b_p,
4741 MUX_SEL_CAM03, 4, 1),
4742 MUX(CLK_MOUT_ACLK_3AA0_A, "mout_aclk_3aa0_a", mout_aclk_3aa0_a_p,
4743 MUX_SEL_CAM03, 0, 1),
4746 MUX(CLK_MOUT_SCLK_LITE_FREECNT_C, "mout_sclk_lite_freecnt_c",
4747 mout_sclk_lite_freecnt_c_p, MUX_SEL_CAM04, 24, 1),
4748 MUX(CLK_MOUT_SCLK_LITE_FREECNT_B, "mout_sclk_lite_freecnt_b",
4749 mout_sclk_lite_freecnt_b_p, MUX_SEL_CAM04, 20, 1),
4750 MUX(CLK_MOUT_SCLK_LITE_FREECNT_A, "mout_sclk_lite_freecnt_a",
4751 mout_sclk_lite_freecnt_a_p, MUX_SEL_CAM04, 16, 1),
4752 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_B, "mout_sclk_pixelasync_lite_c_b",
4753 mout_sclk_pixelasync_lite_c_b_p, MUX_SEL_CAM04, 12, 1),
4754 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_A, "mout_sclk_pixelasync_lite_c_a",
4755 mout_sclk_pixelasync_lite_c_a_p, MUX_SEL_CAM04, 8, 1),
4756 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_B,
4757 "mout_sclk_pixelasync_lite_c_init_b",
4758 mout_sclk_pixelasync_lite_c_init_b_p,
4759 MUX_SEL_CAM04, 4, 1),
4760 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_A,
4761 "mout_sclk_pixelasync_lite_c_init_a",
4762 mout_sclk_pixelasync_lite_c_init_a_p,
4763 MUX_SEL_CAM04, 0, 1),
4766 static const struct samsung_div_clock cam0_div_clks[] __initconst = {
4768 DIV(CLK_DIV_PCLK_CAM0_50, "div_pclk_cam0_50", "div_aclk_cam0_200",
4770 DIV(CLK_DIV_ACLK_CAM0_200, "div_aclk_cam0_200", "mout_aclk_cam0_400",
4772 DIV(CLK_DIV_ACLK_CAM0_BUS_400, "div_aclk_cam0_bus_400",
4773 "mout_aclk_cam0_400", DIV_CAM00, 0, 3),
4776 DIV(CLK_DIV_PCLK_LITE_D, "div_pclk_lite_d", "div_aclk_lite_d",
4778 DIV(CLK_DIV_ACLK_LITE_D, "div_aclk_lite_d", "mout_aclk_lite_d_b",
4780 DIV(CLK_DIV_PCLK_LITE_B, "div_pclk_lite_b", "div_aclk_lite_b",
4782 DIV(CLK_DIV_ACLK_LITE_B, "div_aclk_lite_b", "mout_aclk_lite_b_b",
4784 DIV(CLK_DIV_PCLK_LITE_A, "div_pclk_lite_a", "div_aclk_lite_a",
4786 DIV(CLK_DIV_ACLK_LITE_A, "div_aclk_lite_a", "mout_aclk_lite_a_b",
4790 DIV(CLK_DIV_ACLK_CSIS1, "div_aclk_csis1", "mout_aclk_csis1_b",
4792 DIV(CLK_DIV_ACLK_CSIS0, "div_aclk_csis0", "mout_aclk_csis0_b",
4794 DIV(CLK_DIV_PCLK_3AA1, "div_pclk_3aa1", "div_aclk_3aa1",
4796 DIV(CLK_DIV_ACLK_3AA1, "div_aclk_3aa1", "mout_aclk_3aa1_b",
4798 DIV(CLK_DIV_PCLK_3AA0, "div_pclk_3aa0", "div_aclk_3aa0",
4800 DIV(CLK_DIV_ACLK_3AA0, "div_aclk_3aa0", "mout_aclk_3aa0_b",
4804 DIV(CLK_DIV_SCLK_PIXELASYNC_LITE_C, "div_sclk_pixelasync_lite_c",
4805 "mout_sclk_pixelasync_lite_c_b", DIV_CAM03, 8, 3),
4806 DIV(CLK_DIV_PCLK_PIXELASYNC_LITE_C, "div_pclk_pixelasync_lite_c",
4807 "div_sclk_pixelasync_lite_c_init", DIV_CAM03, 4, 2),
4808 DIV(CLK_DIV_SCLK_PIXELASYNC_LITE_C_INIT,
4809 "div_sclk_pixelasync_lite_c_init",
4810 "mout_sclk_pixelasync_lite_c_init_b", DIV_CAM03, 0, 3),
4813 static const struct samsung_gate_clock cam0_gate_clks[] __initconst = {
4814 /* ENABLE_ACLK_CAM00 */
4815 GATE(CLK_ACLK_CSIS1, "aclk_csis1", "div_aclk_csis1", ENABLE_ACLK_CAM00,
4817 GATE(CLK_ACLK_CSIS0, "aclk_csis0", "div_aclk_csis0", ENABLE_ACLK_CAM00,
4819 GATE(CLK_ACLK_3AA1, "aclk_3aa1", "div_aclk_3aa1", ENABLE_ACLK_CAM00,
4821 GATE(CLK_ACLK_3AA0, "aclk_3aa0", "div_aclk_3aa0", ENABLE_ACLK_CAM00,
4823 GATE(CLK_ACLK_LITE_D, "aclk_lite_d", "div_aclk_lite_d",
4824 ENABLE_ACLK_CAM00, 2, 0, 0),
4825 GATE(CLK_ACLK_LITE_B, "aclk_lite_b", "div_aclk_lite_b",
4826 ENABLE_ACLK_CAM00, 1, 0, 0),
4827 GATE(CLK_ACLK_LITE_A, "aclk_lite_a", "div_aclk_lite_a",
4828 ENABLE_ACLK_CAM00, 0, 0, 0),
4830 /* ENABLE_ACLK_CAM01 */
4831 GATE(CLK_ACLK_AHBSYNCDN, "aclk_ahbsyncdn", "div_aclk_cam0_200",
4832 ENABLE_ACLK_CAM01, 31, CLK_IGNORE_UNUSED, 0),
4833 GATE(CLK_ACLK_AXIUS_LITE_D, "aclk_axius_lite_d", "div_aclk_cam0_bus_400",
4834 ENABLE_ACLK_CAM01, 30, CLK_IGNORE_UNUSED, 0),
4835 GATE(CLK_ACLK_AXIUS_LITE_B, "aclk_axius_lite_b", "div_aclk_cam0_bus_400",
4836 ENABLE_ACLK_CAM01, 29, CLK_IGNORE_UNUSED, 0),
4837 GATE(CLK_ACLK_AXIUS_LITE_A, "aclk_axius_lite_a", "div_aclk_cam0_bus_400",
4838 ENABLE_ACLK_CAM01, 28, CLK_IGNORE_UNUSED, 0),
4839 GATE(CLK_ACLK_ASYNCAPBM_3AA1, "aclk_asyncapbm_3aa1", "div_pclk_3aa1",
4840 ENABLE_ACLK_CAM01, 27, CLK_IGNORE_UNUSED, 0),
4841 GATE(CLK_ACLK_ASYNCAPBS_3AA1, "aclk_asyncapbs_3aa1", "div_aclk_3aa1",
4842 ENABLE_ACLK_CAM01, 26, CLK_IGNORE_UNUSED, 0),
4843 GATE(CLK_ACLK_ASYNCAPBM_3AA0, "aclk_asyncapbm_3aa0", "div_pclk_3aa0",
4844 ENABLE_ACLK_CAM01, 25, CLK_IGNORE_UNUSED, 0),
4845 GATE(CLK_ACLK_ASYNCAPBS_3AA0, "aclk_asyncapbs_3aa0", "div_aclk_3aa0",
4846 ENABLE_ACLK_CAM01, 24, CLK_IGNORE_UNUSED, 0),
4847 GATE(CLK_ACLK_ASYNCAPBM_LITE_D, "aclk_asyncapbm_lite_d",
4848 "div_pclk_lite_d", ENABLE_ACLK_CAM01,
4849 23, CLK_IGNORE_UNUSED, 0),
4850 GATE(CLK_ACLK_ASYNCAPBS_LITE_D, "aclk_asyncapbs_lite_d",
4851 "div_aclk_cam0_200", ENABLE_ACLK_CAM01,
4852 22, CLK_IGNORE_UNUSED, 0),
4853 GATE(CLK_ACLK_ASYNCAPBM_LITE_B, "aclk_asyncapbm_lite_b",
4854 "div_pclk_lite_b", ENABLE_ACLK_CAM01,
4855 21, CLK_IGNORE_UNUSED, 0),
4856 GATE(CLK_ACLK_ASYNCAPBS_LITE_B, "aclk_asyncapbs_lite_b",
4857 "div_aclk_cam0_200", ENABLE_ACLK_CAM01,
4858 20, CLK_IGNORE_UNUSED, 0),
4859 GATE(CLK_ACLK_ASYNCAPBM_LITE_A, "aclk_asyncapbm_lite_a",
4860 "div_pclk_lite_a", ENABLE_ACLK_CAM01,
4861 19, CLK_IGNORE_UNUSED, 0),
4862 GATE(CLK_ACLK_ASYNCAPBS_LITE_A, "aclk_asyncapbs_lite_a",
4863 "div_aclk_cam0_200", ENABLE_ACLK_CAM01,
4864 18, CLK_IGNORE_UNUSED, 0),
4865 GATE(CLK_ACLK_ASYNCAXIM_ISP0P, "aclk_asyncaxim_isp0p",
4866 "div_aclk_cam0_200", ENABLE_ACLK_CAM01,
4867 17, CLK_IGNORE_UNUSED, 0),
4868 GATE(CLK_ACLK_ASYNCAXIM_3AA1, "aclk_asyncaxim_3aa1",
4869 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4870 16, CLK_IGNORE_UNUSED, 0),
4871 GATE(CLK_ACLK_ASYNCAXIS_3AA1, "aclk_asyncaxis_3aa1",
4872 "div_aclk_3aa1", ENABLE_ACLK_CAM01,
4873 15, CLK_IGNORE_UNUSED, 0),
4874 GATE(CLK_ACLK_ASYNCAXIM_3AA0, "aclk_asyncaxim_3aa0",
4875 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4876 14, CLK_IGNORE_UNUSED, 0),
4877 GATE(CLK_ACLK_ASYNCAXIS_3AA0, "aclk_asyncaxis_3aa0",
4878 "div_aclk_3aa0", ENABLE_ACLK_CAM01,
4879 13, CLK_IGNORE_UNUSED, 0),
4880 GATE(CLK_ACLK_ASYNCAXIM_LITE_D, "aclk_asyncaxim_lite_d",
4881 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4882 12, CLK_IGNORE_UNUSED, 0),
4883 GATE(CLK_ACLK_ASYNCAXIS_LITE_D, "aclk_asyncaxis_lite_d",
4884 "div_aclk_lite_d", ENABLE_ACLK_CAM01,
4885 11, CLK_IGNORE_UNUSED, 0),
4886 GATE(CLK_ACLK_ASYNCAXIM_LITE_B, "aclk_asyncaxim_lite_b",
4887 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4888 10, CLK_IGNORE_UNUSED, 0),
4889 GATE(CLK_ACLK_ASYNCAXIS_LITE_B, "aclk_asyncaxis_lite_b",
4890 "div_aclk_lite_b", ENABLE_ACLK_CAM01,
4891 9, CLK_IGNORE_UNUSED, 0),
4892 GATE(CLK_ACLK_ASYNCAXIM_LITE_A, "aclk_asyncaxim_lite_a",
4893 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4894 8, CLK_IGNORE_UNUSED, 0),
4895 GATE(CLK_ACLK_ASYNCAXIS_LITE_A, "aclk_asyncaxis_lite_a",
4896 "div_aclk_lite_a", ENABLE_ACLK_CAM01,
4897 7, CLK_IGNORE_UNUSED, 0),
4898 GATE(CLK_ACLK_AHB2APB_ISPSFRP, "aclk_ahb2apb_ispsfrp",
4899 "div_pclk_cam0_50", ENABLE_ACLK_CAM01,
4900 6, CLK_IGNORE_UNUSED, 0),
4901 GATE(CLK_ACLK_AXI2APB_ISP0P, "aclk_axi2apb_isp0p", "div_aclk_cam0_200",
4902 ENABLE_ACLK_CAM01, 5, CLK_IGNORE_UNUSED, 0),
4903 GATE(CLK_ACLK_AXI2AHB_ISP0P, "aclk_axi2ahb_isp0p", "div_aclk_cam0_200",
4904 ENABLE_ACLK_CAM01, 4, CLK_IGNORE_UNUSED, 0),
4905 GATE(CLK_ACLK_XIU_IS0X, "aclk_xiu_is0x", "div_aclk_cam0_200",
4906 ENABLE_ACLK_CAM01, 3, CLK_IGNORE_UNUSED, 0),
4907 GATE(CLK_ACLK_XIU_ISP0EX, "aclk_xiu_isp0ex", "div_aclk_cam0_bus_400",
4908 ENABLE_ACLK_CAM01, 2, CLK_IGNORE_UNUSED, 0),
4909 GATE(CLK_ACLK_CAM0NP_276, "aclk_cam0np_276", "div_aclk_cam0_200",
4910 ENABLE_ACLK_CAM01, 1, CLK_IGNORE_UNUSED, 0),
4911 GATE(CLK_ACLK_CAM0ND_400, "aclk_cam0nd_400", "div_aclk_cam0_bus_400",
4912 ENABLE_ACLK_CAM01, 0, CLK_IGNORE_UNUSED, 0),
4914 /* ENABLE_ACLK_CAM02 */
4915 GATE(CLK_ACLK_SMMU_3AA1, "aclk_smmu_3aa1", "div_aclk_cam0_bus_400",
4916 ENABLE_ACLK_CAM02, 9, CLK_IGNORE_UNUSED, 0),
4917 GATE(CLK_ACLK_SMMU_3AA0, "aclk_smmu_3aa0", "div_aclk_cam0_bus_400",
4918 ENABLE_ACLK_CAM02, 8, CLK_IGNORE_UNUSED, 0),
4919 GATE(CLK_ACLK_SMMU_LITE_D, "aclk_smmu_lite_d", "div_aclk_cam0_bus_400",
4920 ENABLE_ACLK_CAM02, 7, CLK_IGNORE_UNUSED, 0),
4921 GATE(CLK_ACLK_SMMU_LITE_B, "aclk_smmu_lite_b", "div_aclk_cam0_bus_400",
4922 ENABLE_ACLK_CAM02, 6, CLK_IGNORE_UNUSED, 0),
4923 GATE(CLK_ACLK_SMMU_LITE_A, "aclk_smmu_lite_a", "div_aclk_cam0_bus_400",
4924 ENABLE_ACLK_CAM02, 5, CLK_IGNORE_UNUSED, 0),
4925 GATE(CLK_ACLK_BTS_3AA1, "aclk_bts_3aa1", "div_aclk_cam0_bus_400",
4926 ENABLE_ACLK_CAM02, 4, CLK_IGNORE_UNUSED, 0),
4927 GATE(CLK_ACLK_BTS_3AA0, "aclk_bts_3aa0", "div_aclk_cam0_bus_400",
4928 ENABLE_ACLK_CAM02, 3, CLK_IGNORE_UNUSED, 0),
4929 GATE(CLK_ACLK_BTS_LITE_D, "aclk_bts_lite_d", "div_aclk_cam0_bus_400",
4930 ENABLE_ACLK_CAM02, 2, CLK_IGNORE_UNUSED, 0),
4931 GATE(CLK_ACLK_BTS_LITE_B, "aclk_bts_lite_b", "div_aclk_cam0_bus_400",
4932 ENABLE_ACLK_CAM02, 1, CLK_IGNORE_UNUSED, 0),
4933 GATE(CLK_ACLK_BTS_LITE_A, "aclk_bts_lite_a", "div_aclk_cam0_bus_400",
4934 ENABLE_ACLK_CAM02, 0, CLK_IGNORE_UNUSED, 0),
4936 /* ENABLE_PCLK_CAM0 */
4937 GATE(CLK_PCLK_SMMU_3AA1, "pclk_smmu_3aa1", "div_aclk_cam0_200",
4938 ENABLE_PCLK_CAM0, 25, CLK_IGNORE_UNUSED, 0),
4939 GATE(CLK_PCLK_SMMU_3AA0, "pclk_smmu_3aa0", "div_aclk_cam0_200",
4940 ENABLE_PCLK_CAM0, 24, CLK_IGNORE_UNUSED, 0),
4941 GATE(CLK_PCLK_SMMU_LITE_D, "pclk_smmu_lite_d", "div_aclk_cam0_200",
4942 ENABLE_PCLK_CAM0, 23, CLK_IGNORE_UNUSED, 0),
4943 GATE(CLK_PCLK_SMMU_LITE_B, "pclk_smmu_lite_b", "div_aclk_cam0_200",
4944 ENABLE_PCLK_CAM0, 22, CLK_IGNORE_UNUSED, 0),
4945 GATE(CLK_PCLK_SMMU_LITE_A, "pclk_smmu_lite_a", "div_aclk_cam0_200",
4946 ENABLE_PCLK_CAM0, 21, CLK_IGNORE_UNUSED, 0),
4947 GATE(CLK_PCLK_BTS_3AA1, "pclk_bts_3aa1", "div_pclk_cam0_50",
4948 ENABLE_PCLK_CAM0, 20, CLK_IGNORE_UNUSED, 0),
4949 GATE(CLK_PCLK_BTS_3AA0, "pclk_bts_3aa0", "div_pclk_cam0_50",
4950 ENABLE_PCLK_CAM0, 19, CLK_IGNORE_UNUSED, 0),
4951 GATE(CLK_PCLK_BTS_LITE_D, "pclk_bts_lite_d", "div_pclk_cam0_50",
4952 ENABLE_PCLK_CAM0, 18, CLK_IGNORE_UNUSED, 0),
4953 GATE(CLK_PCLK_BTS_LITE_B, "pclk_bts_lite_b", "div_pclk_cam0_50",
4954 ENABLE_PCLK_CAM0, 17, CLK_IGNORE_UNUSED, 0),
4955 GATE(CLK_PCLK_BTS_LITE_A, "pclk_bts_lite_a", "div_pclk_cam0_50",
4956 ENABLE_PCLK_CAM0, 16, CLK_IGNORE_UNUSED, 0),
4957 GATE(CLK_PCLK_ASYNCAXI_CAM1, "pclk_asyncaxi_cam1", "div_pclk_cam0_50",
4958 ENABLE_PCLK_CAM0, 15, CLK_IGNORE_UNUSED, 0),
4959 GATE(CLK_PCLK_ASYNCAXI_3AA1, "pclk_asyncaxi_3aa1", "div_pclk_cam0_50",
4960 ENABLE_PCLK_CAM0, 14, CLK_IGNORE_UNUSED, 0),
4961 GATE(CLK_PCLK_ASYNCAXI_3AA0, "pclk_asyncaxi_3aa0", "div_pclk_cam0_50",
4962 ENABLE_PCLK_CAM0, 13, CLK_IGNORE_UNUSED, 0),
4963 GATE(CLK_PCLK_ASYNCAXI_LITE_D, "pclk_asyncaxi_lite_d",
4964 "div_pclk_cam0_50", ENABLE_PCLK_CAM0,
4965 12, CLK_IGNORE_UNUSED, 0),
4966 GATE(CLK_PCLK_ASYNCAXI_LITE_B, "pclk_asyncaxi_lite_b",
4967 "div_pclk_cam0_50", ENABLE_PCLK_CAM0,
4968 11, CLK_IGNORE_UNUSED, 0),
4969 GATE(CLK_PCLK_ASYNCAXI_LITE_A, "pclk_asyncaxi_lite_a",
4970 "div_pclk_cam0_50", ENABLE_PCLK_CAM0,
4971 10, CLK_IGNORE_UNUSED, 0),
4972 GATE(CLK_PCLK_PMU_CAM0, "pclk_pmu_cam0", "div_pclk_cam0_50",
4973 ENABLE_PCLK_CAM0, 9, CLK_IGNORE_UNUSED, 0),
4974 GATE(CLK_PCLK_SYSREG_CAM0, "pclk_sysreg_cam0", "div_pclk_cam0_50",
4975 ENABLE_PCLK_CAM0, 8, CLK_IGNORE_UNUSED, 0),
4976 GATE(CLK_PCLK_CMU_CAM0_LOCAL, "pclk_cmu_cam0_local",
4977 "div_aclk_cam0_200", ENABLE_PCLK_CAM0,
4978 7, CLK_IGNORE_UNUSED, 0),
4979 GATE(CLK_PCLK_CSIS1, "pclk_csis1", "div_aclk_cam0_200",
4980 ENABLE_PCLK_CAM0, 6, CLK_IGNORE_UNUSED, 0),
4981 GATE(CLK_PCLK_CSIS0, "pclk_csis0", "div_aclk_cam0_200",
4982 ENABLE_PCLK_CAM0, 5, CLK_IGNORE_UNUSED, 0),
4983 GATE(CLK_PCLK_3AA1, "pclk_3aa1", "div_pclk_3aa1",
4984 ENABLE_PCLK_CAM0, 4, CLK_IGNORE_UNUSED, 0),
4985 GATE(CLK_PCLK_3AA0, "pclk_3aa0", "div_pclk_3aa0",
4986 ENABLE_PCLK_CAM0, 3, CLK_IGNORE_UNUSED, 0),
4987 GATE(CLK_PCLK_LITE_D, "pclk_lite_d", "div_pclk_lite_d",
4988 ENABLE_PCLK_CAM0, 2, CLK_IGNORE_UNUSED, 0),
4989 GATE(CLK_PCLK_LITE_B, "pclk_lite_b", "div_pclk_lite_b",
4990 ENABLE_PCLK_CAM0, 1, CLK_IGNORE_UNUSED, 0),
4991 GATE(CLK_PCLK_LITE_A, "pclk_lite_a", "div_pclk_lite_a",
4992 ENABLE_PCLK_CAM0, 0, CLK_IGNORE_UNUSED, 0),
4994 /* ENABLE_SCLK_CAM0 */
4995 GATE(CLK_PHYCLK_RXBYTECLKHS0_S4, "phyclk_rxbyteclkhs0_s4",
4996 "mout_phyclk_rxbyteclkhs0_s4_user",
4997 ENABLE_SCLK_CAM0, 8, 0, 0),
4998 GATE(CLK_PHYCLK_RXBYTECLKHS0_S2A, "phyclk_rxbyteclkhs0_s2a",
4999 "mout_phyclk_rxbyteclkhs0_s2a_user",
5000 ENABLE_SCLK_CAM0, 7, 0, 0),
5001 GATE(CLK_SCLK_LITE_FREECNT, "sclk_lite_freecnt",
5002 "mout_sclk_lite_freecnt_c", ENABLE_SCLK_CAM0, 6, 0, 0),
5003 GATE(CLK_SCLK_PIXELASYNCM_3AA1, "sclk_pixelasycm_3aa1",
5004 "div_aclk_3aa1", ENABLE_SCLK_CAM0, 5, 0, 0),
5005 GATE(CLK_SCLK_PIXELASYNCM_3AA0, "sclk_pixelasycm_3aa0",
5006 "div_aclk_3aa0", ENABLE_SCLK_CAM0, 4, 0, 0),
5007 GATE(CLK_SCLK_PIXELASYNCS_3AA0, "sclk_pixelasycs_3aa0",
5008 "div_aclk_3aa0", ENABLE_SCLK_CAM0, 3, 0, 0),
5009 GATE(CLK_SCLK_PIXELASYNCM_LITE_C, "sclk_pixelasyncm_lite_c",
5010 "div_sclk_pixelasync_lite_c",
5011 ENABLE_SCLK_CAM0, 2, 0, 0),
5012 GATE(CLK_SCLK_PIXELASYNCM_LITE_C_INIT, "sclk_pixelasyncm_lite_c_init",
5013 "div_sclk_pixelasync_lite_c_init",
5014 ENABLE_SCLK_CAM0, 1, 0, 0),
5015 GATE(CLK_SCLK_PIXELASYNCS_LITE_C_INIT, "sclk_pixelasyncs_lite_c_init",
5016 "div_sclk_pixelasync_lite_c",
5017 ENABLE_SCLK_CAM0, 0, 0, 0),
5020 static const struct samsung_cmu_info cam0_cmu_info __initconst = {
5021 .mux_clks = cam0_mux_clks,
5022 .nr_mux_clks = ARRAY_SIZE(cam0_mux_clks),
5023 .div_clks = cam0_div_clks,
5024 .nr_div_clks = ARRAY_SIZE(cam0_div_clks),
5025 .gate_clks = cam0_gate_clks,
5026 .nr_gate_clks = ARRAY_SIZE(cam0_gate_clks),
5027 .fixed_clks = cam0_fixed_clks,
5028 .nr_fixed_clks = ARRAY_SIZE(cam0_fixed_clks),
5029 .nr_clk_ids = CAM0_NR_CLK,
5030 .clk_regs = cam0_clk_regs,
5031 .nr_clk_regs = ARRAY_SIZE(cam0_clk_regs),
5034 static void __init exynos5433_cmu_cam0_init(struct device_node *np)
5036 samsung_cmu_register_one(np, &cam0_cmu_info);
5038 CLK_OF_DECLARE(exynos5433_cmu_cam0, "samsung,exynos5433-cmu-cam0",
5039 exynos5433_cmu_cam0_init);
5042 * Register offset definitions for CMU_CAM1
5044 #define MUX_SEL_CAM10 0x0200
5045 #define MUX_SEL_CAM11 0x0204
5046 #define MUX_SEL_CAM12 0x0208
5047 #define MUX_ENABLE_CAM10 0x0300
5048 #define MUX_ENABLE_CAM11 0x0304
5049 #define MUX_ENABLE_CAM12 0x0308
5050 #define MUX_STAT_CAM10 0x0400
5051 #define MUX_STAT_CAM11 0x0404
5052 #define MUX_STAT_CAM12 0x0408
5053 #define MUX_IGNORE_CAM11 0x0504
5054 #define DIV_CAM10 0x0600
5055 #define DIV_CAM11 0x0604
5056 #define DIV_STAT_CAM10 0x0700
5057 #define DIV_STAT_CAM11 0x0704
5058 #define ENABLE_ACLK_CAM10 0X0800
5059 #define ENABLE_ACLK_CAM11 0X0804
5060 #define ENABLE_ACLK_CAM12 0X0808
5061 #define ENABLE_PCLK_CAM1 0X0900
5062 #define ENABLE_SCLK_CAM1 0X0a00
5063 #define ENABLE_IP_CAM10 0X0b00
5064 #define ENABLE_IP_CAM11 0X0b04
5065 #define ENABLE_IP_CAM12 0X0b08
5067 static const unsigned long cam1_clk_regs[] __initconst = {
5087 PNAME(mout_sclk_isp_uart_user_p) = { "oscclk", "sclk_isp_uart_cam1", };
5088 PNAME(mout_sclk_isp_spi1_user_p) = { "oscclk", "sclk_isp_spi1_cam1", };
5089 PNAME(mout_sclk_isp_spi0_user_p) = { "oscclk", "sclk_isp_spi0_cam1", };
5091 PNAME(mout_aclk_cam1_333_user_p) = { "oscclk", "aclk_cam1_333", };
5092 PNAME(mout_aclk_cam1_400_user_p) = { "oscclk", "aclk_cam1_400", };
5093 PNAME(mout_aclk_cam1_552_user_p) = { "oscclk", "aclk_cam1_552", };
5095 PNAME(mout_phyclk_rxbyteclkhs0_s2b_user_p) = { "oscclk",
5096 "phyclk_rxbyteclkhs0_s2b_phy", };
5098 PNAME(mout_aclk_csis2_b_p) = { "mout_aclk_csis2_a",
5099 "mout_aclk_cam1_333_user", };
5100 PNAME(mout_aclk_csis2_a_p) = { "mout_aclk_cam1_552_user",
5101 "mout_aclk_cam1_400_user", };
5103 PNAME(mout_aclk_fd_b_p) = { "mout_aclk_fd_a",
5104 "mout_aclk_cam1_333_user", };
5105 PNAME(mout_aclk_fd_a_p) = { "mout_aclk_cam1_552_user",
5106 "mout_aclk_cam1_400_user", };
5108 PNAME(mout_aclk_lite_c_b_p) = { "mout_aclk_lite_c_a",
5109 "mout_aclk_cam1_333_user", };
5110 PNAME(mout_aclk_lite_c_a_p) = { "mout_aclk_cam1_552_user",
5111 "mout_aclk_cam1_400_user", };
5113 static const struct samsung_fixed_rate_clock cam1_fixed_clks[] __initconst = {
5114 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2B, "phyclk_rxbyteclkhs0_s2b_phy", NULL,
5118 static const struct samsung_mux_clock cam1_mux_clks[] __initconst = {
5120 MUX(CLK_MOUT_SCLK_ISP_UART_USER, "mout_sclk_isp_uart_user",
5121 mout_sclk_isp_uart_user_p, MUX_SEL_CAM10, 20, 1),
5122 MUX(CLK_MOUT_SCLK_ISP_SPI1_USER, "mout_sclk_isp_spi1_user",
5123 mout_sclk_isp_spi1_user_p, MUX_SEL_CAM10, 16, 1),
5124 MUX(CLK_MOUT_SCLK_ISP_SPI0_USER, "mout_sclk_isp_spi0_user",
5125 mout_sclk_isp_spi0_user_p, MUX_SEL_CAM10, 12, 1),
5126 MUX(CLK_MOUT_ACLK_CAM1_333_USER, "mout_aclk_cam1_333_user",
5127 mout_aclk_cam1_333_user_p, MUX_SEL_CAM10, 8, 1),
5128 MUX(CLK_MOUT_ACLK_CAM1_400_USER, "mout_aclk_cam1_400_user",
5129 mout_aclk_cam1_400_user_p, MUX_SEL_CAM10, 4, 1),
5130 MUX(CLK_MOUT_ACLK_CAM1_552_USER, "mout_aclk_cam1_552_user",
5131 mout_aclk_cam1_552_user_p, MUX_SEL_CAM10, 0, 1),
5134 MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2B_USER,
5135 "mout_phyclk_rxbyteclkhs0_s2b_user",
5136 mout_phyclk_rxbyteclkhs0_s2b_user_p,
5137 MUX_SEL_CAM11, 0, 1),
5140 MUX(CLK_MOUT_ACLK_CSIS2_B, "mout_aclk_csis2_b", mout_aclk_csis2_b_p,
5141 MUX_SEL_CAM12, 20, 1),
5142 MUX(CLK_MOUT_ACLK_CSIS2_A, "mout_aclk_csis2_a", mout_aclk_csis2_a_p,
5143 MUX_SEL_CAM12, 16, 1),
5144 MUX(CLK_MOUT_ACLK_FD_B, "mout_aclk_fd_b", mout_aclk_fd_b_p,
5145 MUX_SEL_CAM12, 12, 1),
5146 MUX(CLK_MOUT_ACLK_FD_A, "mout_aclk_fd_a", mout_aclk_fd_a_p,
5147 MUX_SEL_CAM12, 8, 1),
5148 MUX(CLK_MOUT_ACLK_LITE_C_B, "mout_aclk_lite_c_b", mout_aclk_lite_c_b_p,
5149 MUX_SEL_CAM12, 4, 1),
5150 MUX(CLK_MOUT_ACLK_LITE_C_A, "mout_aclk_lite_c_a", mout_aclk_lite_c_a_p,
5151 MUX_SEL_CAM12, 0, 1),
5154 static const struct samsung_div_clock cam1_div_clks[] __initconst = {
5156 DIV(CLK_DIV_SCLK_ISP_MPWM, "div_sclk_isp_mpwm",
5157 "div_pclk_cam1_83", DIV_CAM10, 16, 2),
5158 DIV(CLK_DIV_PCLK_CAM1_83, "div_pclk_cam1_83",
5159 "mout_aclk_cam1_333_user", DIV_CAM10, 12, 2),
5160 DIV(CLK_DIV_PCLK_CAM1_166, "div_pclk_cam1_166",
5161 "mout_aclk_cam1_333_user", DIV_CAM10, 8, 2),
5162 DIV(CLK_DIV_PCLK_DBG_CAM1, "div_pclk_dbg_cam1",
5163 "mout_aclk_cam1_552_user", DIV_CAM10, 4, 3),
5164 DIV(CLK_DIV_ATCLK_CAM1, "div_atclk_cam1", "mout_aclk_cam1_552_user",
5168 DIV(CLK_DIV_ACLK_CSIS2, "div_aclk_csis2", "mout_aclk_csis2_b",
5170 DIV(CLK_DIV_PCLK_FD, "div_pclk_fd", "div_aclk_fd", DIV_CAM11, 12, 2),
5171 DIV(CLK_DIV_ACLK_FD, "div_aclk_fd", "mout_aclk_fd_b", DIV_CAM11, 8, 3),
5172 DIV(CLK_DIV_PCLK_LITE_C, "div_pclk_lite_c", "div_aclk_lite_c",
5174 DIV(CLK_DIV_ACLK_LITE_C, "div_aclk_lite_c", "mout_aclk_lite_c_b",
5178 static const struct samsung_gate_clock cam1_gate_clks[] __initconst = {
5179 /* ENABLE_ACLK_CAM10 */
5180 GATE(CLK_ACLK_ISP_GIC, "aclk_isp_gic", "mout_aclk_cam1_333_user",
5181 ENABLE_ACLK_CAM10, 4, 0, 0),
5182 GATE(CLK_ACLK_FD, "aclk_fd", "div_aclk_fd",
5183 ENABLE_ACLK_CAM10, 3, 0, 0),
5184 GATE(CLK_ACLK_LITE_C, "aclk_lite_c", "div_aclk_lite_c",
5185 ENABLE_ACLK_CAM10, 1, 0, 0),
5186 GATE(CLK_ACLK_CSIS2, "aclk_csis2", "div_aclk_csis2",
5187 ENABLE_ACLK_CAM10, 0, 0, 0),
5189 /* ENABLE_ACLK_CAM11 */
5190 GATE(CLK_ACLK_ASYNCAPBM_FD, "aclk_asyncapbm_fd", "div_pclk_fd",
5191 ENABLE_ACLK_CAM11, 29, CLK_IGNORE_UNUSED, 0),
5192 GATE(CLK_ACLK_ASYNCAPBS_FD, "aclk_asyncapbs_fd", "div_pclk_cam1_166",
5193 ENABLE_ACLK_CAM11, 28, CLK_IGNORE_UNUSED, 0),
5194 GATE(CLK_ACLK_ASYNCAPBM_LITE_C, "aclk_asyncapbm_lite_c",
5195 "div_pclk_lite_c", ENABLE_ACLK_CAM11,
5196 27, CLK_IGNORE_UNUSED, 0),
5197 GATE(CLK_ACLK_ASYNCAPBS_LITE_C, "aclk_asyncapbs_lite_c",
5198 "div_pclk_cam1_166", ENABLE_ACLK_CAM11,
5199 26, CLK_IGNORE_UNUSED, 0),
5200 GATE(CLK_ACLK_ASYNCAHBS_SFRISP2H2, "aclk_asyncahbs_sfrisp2h2",
5201 "div_pclk_cam1_83", ENABLE_ACLK_CAM11,
5202 25, CLK_IGNORE_UNUSED, 0),
5203 GATE(CLK_ACLK_ASYNCAHBS_SFRISP2H1, "aclk_asyncahbs_sfrisp2h1",
5204 "div_pclk_cam1_83", ENABLE_ACLK_CAM11,
5205 24, CLK_IGNORE_UNUSED, 0),
5206 GATE(CLK_ACLK_ASYNCAXIM_CA5, "aclk_asyncaxim_ca5",
5207 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5208 23, CLK_IGNORE_UNUSED, 0),
5209 GATE(CLK_ACLK_ASYNCAXIS_CA5, "aclk_asyncaxis_ca5",
5210 "mout_aclk_cam1_552_user", ENABLE_ACLK_CAM11,
5211 22, CLK_IGNORE_UNUSED, 0),
5212 GATE(CLK_ACLK_ASYNCAXIS_ISPX2, "aclk_asyncaxis_ispx2",
5213 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5214 21, CLK_IGNORE_UNUSED, 0),
5215 GATE(CLK_ACLK_ASYNCAXIS_ISPX1, "aclk_asyncaxis_ispx1",
5216 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5217 20, CLK_IGNORE_UNUSED, 0),
5218 GATE(CLK_ACLK_ASYNCAXIS_ISPX0, "aclk_asyncaxis_ispx0",
5219 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5220 19, CLK_IGNORE_UNUSED, 0),
5221 GATE(CLK_ACLK_ASYNCAXIM_ISPEX, "aclk_asyncaxim_ispex",
5222 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
5223 18, CLK_IGNORE_UNUSED, 0),
5224 GATE(CLK_ACLK_ASYNCAXIM_ISP3P, "aclk_asyncaxim_isp3p",
5225 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
5226 17, CLK_IGNORE_UNUSED, 0),
5227 GATE(CLK_ACLK_ASYNCAXIS_ISP3P, "aclk_asyncaxis_isp3p",
5228 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5229 16, CLK_IGNORE_UNUSED, 0),
5230 GATE(CLK_ACLK_ASYNCAXIM_FD, "aclk_asyncaxim_fd",
5231 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
5232 15, CLK_IGNORE_UNUSED, 0),
5233 GATE(CLK_ACLK_ASYNCAXIS_FD, "aclk_asyncaxis_fd", "div_aclk_fd",
5234 ENABLE_ACLK_CAM11, 14, CLK_IGNORE_UNUSED, 0),
5235 GATE(CLK_ACLK_ASYNCAXIM_LITE_C, "aclk_asyncaxim_lite_c",
5236 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
5237 13, CLK_IGNORE_UNUSED, 0),
5238 GATE(CLK_ACLK_ASYNCAXIS_LITE_C, "aclk_asyncaxis_lite_c",
5239 "div_aclk_lite_c", ENABLE_ACLK_CAM11,
5240 12, CLK_IGNORE_UNUSED, 0),
5241 GATE(CLK_ACLK_AHB2APB_ISP5P, "aclk_ahb2apb_isp5p", "div_pclk_cam1_83",
5242 ENABLE_ACLK_CAM11, 11, CLK_IGNORE_UNUSED, 0),
5243 GATE(CLK_ACLK_AHB2APB_ISP3P, "aclk_ahb2apb_isp3p", "div_pclk_cam1_83",
5244 ENABLE_ACLK_CAM11, 10, CLK_IGNORE_UNUSED, 0),
5245 GATE(CLK_ACLK_AXI2APB_ISP3P, "aclk_axi2apb_isp3p",
5246 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5247 9, CLK_IGNORE_UNUSED, 0),
5248 GATE(CLK_ACLK_AHB_SFRISP2H, "aclk_ahb_sfrisp2h", "div_pclk_cam1_83",
5249 ENABLE_ACLK_CAM11, 8, CLK_IGNORE_UNUSED, 0),
5250 GATE(CLK_ACLK_AXI_ISP_HX_R, "aclk_axi_isp_hx_r", "div_pclk_cam1_166",
5251 ENABLE_ACLK_CAM11, 7, CLK_IGNORE_UNUSED, 0),
5252 GATE(CLK_ACLK_AXI_ISP_CX_R, "aclk_axi_isp_cx_r", "div_pclk_cam1_166",
5253 ENABLE_ACLK_CAM11, 6, CLK_IGNORE_UNUSED, 0),
5254 GATE(CLK_ACLK_AXI_ISP_HX, "aclk_axi_isp_hx", "mout_aclk_cam1_333_user",
5255 ENABLE_ACLK_CAM11, 5, CLK_IGNORE_UNUSED, 0),
5256 GATE(CLK_ACLK_AXI_ISP_CX, "aclk_axi_isp_cx", "mout_aclk_cam1_333_user",
5257 ENABLE_ACLK_CAM11, 4, CLK_IGNORE_UNUSED, 0),
5258 GATE(CLK_ACLK_XIU_ISPX, "aclk_xiu_ispx", "mout_aclk_cam1_333_user",
5259 ENABLE_ACLK_CAM11, 3, CLK_IGNORE_UNUSED, 0),
5260 GATE(CLK_ACLK_XIU_ISPEX, "aclk_xiu_ispex", "mout_aclk_cam1_400_user",
5261 ENABLE_ACLK_CAM11, 2, CLK_IGNORE_UNUSED, 0),
5262 GATE(CLK_ACLK_CAM1NP_333, "aclk_cam1np_333", "mout_aclk_cam1_333_user",
5263 ENABLE_ACLK_CAM11, 1, CLK_IGNORE_UNUSED, 0),
5264 GATE(CLK_ACLK_CAM1ND_400, "aclk_cam1nd_400", "mout_aclk_cam1_400_user",
5265 ENABLE_ACLK_CAM11, 0, CLK_IGNORE_UNUSED, 0),
5267 /* ENABLE_ACLK_CAM12 */
5268 GATE(CLK_ACLK_SMMU_ISPCPU, "aclk_smmu_ispcpu",
5269 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
5270 10, CLK_IGNORE_UNUSED, 0),
5271 GATE(CLK_ACLK_SMMU_FD, "aclk_smmu_fd", "mout_aclk_cam1_400_user",
5272 ENABLE_ACLK_CAM12, 9, CLK_IGNORE_UNUSED, 0),
5273 GATE(CLK_ACLK_SMMU_LITE_C, "aclk_smmu_lite_c",
5274 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
5275 8, CLK_IGNORE_UNUSED, 0),
5276 GATE(CLK_ACLK_BTS_ISP3P, "aclk_bts_isp3p", "mout_aclk_cam1_400_user",
5277 ENABLE_ACLK_CAM12, 7, CLK_IGNORE_UNUSED, 0),
5278 GATE(CLK_ACLK_BTS_FD, "aclk_bts_fd", "mout_aclk_cam1_400_user",
5279 ENABLE_ACLK_CAM12, 6, CLK_IGNORE_UNUSED, 0),
5280 GATE(CLK_ACLK_BTS_LITE_C, "aclk_bts_lite_c", "mout_aclk_cam1_400_user",
5281 ENABLE_ACLK_CAM12, 5, CLK_IGNORE_UNUSED, 0),
5282 GATE(CLK_ACLK_AHBDN_SFRISP2H, "aclk_ahbdn_sfrisp2h",
5283 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM12,
5284 4, CLK_IGNORE_UNUSED, 0),
5285 GATE(CLK_ACLK_AHBDN_ISP5P, "aclk_aclk-shbdn_isp5p",
5286 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM12,
5287 3, CLK_IGNORE_UNUSED, 0),
5288 GATE(CLK_ACLK_AXIUS_ISP3P, "aclk_axius_isp3p",
5289 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
5290 2, CLK_IGNORE_UNUSED, 0),
5291 GATE(CLK_ACLK_AXIUS_FD, "aclk_axius_fd", "mout_aclk_cam1_400_user",
5292 ENABLE_ACLK_CAM12, 1, CLK_IGNORE_UNUSED, 0),
5293 GATE(CLK_ACLK_AXIUS_LITE_C, "aclk_axius_lite_c",
5294 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
5295 0, CLK_IGNORE_UNUSED, 0),
5297 /* ENABLE_PCLK_CAM1 */
5298 GATE(CLK_PCLK_SMMU_ISPCPU, "pclk_smmu_ispcpu", "div_pclk_cam1_166",
5299 ENABLE_PCLK_CAM1, 27, CLK_IGNORE_UNUSED, 0),
5300 GATE(CLK_PCLK_SMMU_FD, "pclk_smmu_fd", "div_pclk_cam1_166",
5301 ENABLE_PCLK_CAM1, 26, CLK_IGNORE_UNUSED, 0),
5302 GATE(CLK_PCLK_SMMU_LITE_C, "pclk_smmu_lite_c", "div_pclk_cam1_166",
5303 ENABLE_PCLK_CAM1, 25, CLK_IGNORE_UNUSED, 0),
5304 GATE(CLK_PCLK_BTS_ISP3P, "pclk_bts_isp3p", "div_pclk_cam1_83",
5305 ENABLE_PCLK_CAM1, 24, CLK_IGNORE_UNUSED, 0),
5306 GATE(CLK_PCLK_BTS_FD, "pclk_bts_fd", "div_pclk_cam1_83",
5307 ENABLE_PCLK_CAM1, 23, CLK_IGNORE_UNUSED, 0),
5308 GATE(CLK_PCLK_BTS_LITE_C, "pclk_bts_lite_c", "div_pclk_cam1_83",
5309 ENABLE_PCLK_CAM1, 22, CLK_IGNORE_UNUSED, 0),
5310 GATE(CLK_PCLK_ASYNCAXIM_CA5, "pclk_asyncaxim_ca5", "div_pclk_cam1_166",
5311 ENABLE_PCLK_CAM1, 21, CLK_IGNORE_UNUSED, 0),
5312 GATE(CLK_PCLK_ASYNCAXIM_ISPEX, "pclk_asyncaxim_ispex",
5313 "div_pclk_cam1_83", ENABLE_PCLK_CAM1,
5314 20, CLK_IGNORE_UNUSED, 0),
5315 GATE(CLK_PCLK_ASYNCAXIM_ISP3P, "pclk_asyncaxim_isp3p",
5316 "div_pclk_cam1_83", ENABLE_PCLK_CAM1,
5317 19, CLK_IGNORE_UNUSED, 0),
5318 GATE(CLK_PCLK_ASYNCAXIM_FD, "pclk_asyncaxim_fd", "div_pclk_cam1_83",
5319 ENABLE_PCLK_CAM1, 18, CLK_IGNORE_UNUSED, 0),
5320 GATE(CLK_PCLK_ASYNCAXIM_LITE_C, "pclk_asyncaxim_lite_c",
5321 "div_pclk_cam1_83", ENABLE_PCLK_CAM1,
5322 17, CLK_IGNORE_UNUSED, 0),
5323 GATE(CLK_PCLK_PMU_CAM1, "pclk_pmu_cam1", "div_pclk_cam1_83",
5324 ENABLE_PCLK_CAM1, 16, CLK_IGNORE_UNUSED, 0),
5325 GATE(CLK_PCLK_SYSREG_CAM1, "pclk_sysreg_cam1", "div_pclk_cam1_83",
5326 ENABLE_PCLK_CAM1, 15, CLK_IGNORE_UNUSED, 0),
5327 GATE(CLK_PCLK_CMU_CAM1_LOCAL, "pclk_cmu_cam1_local",
5328 "div_pclk_cam1_166", ENABLE_PCLK_CAM1,
5329 14, CLK_IGNORE_UNUSED, 0),
5330 GATE(CLK_PCLK_ISP_MCTADC, "pclk_isp_mctadc", "div_pclk_cam1_83",
5331 ENABLE_PCLK_CAM1, 13, CLK_IGNORE_UNUSED, 0),
5332 GATE(CLK_PCLK_ISP_WDT, "pclk_isp_wdt", "div_pclk_cam1_83",
5333 ENABLE_PCLK_CAM1, 12, CLK_IGNORE_UNUSED, 0),
5334 GATE(CLK_PCLK_ISP_PWM, "pclk_isp_pwm", "div_pclk_cam1_83",
5335 ENABLE_PCLK_CAM1, 11, CLK_IGNORE_UNUSED, 0),
5336 GATE(CLK_PCLK_ISP_UART, "pclk_isp_uart", "div_pclk_cam1_83",
5337 ENABLE_PCLK_CAM1, 10, CLK_IGNORE_UNUSED, 0),
5338 GATE(CLK_PCLK_ISP_MCUCTL, "pclk_isp_mcuctl", "div_pclk_cam1_83",
5339 ENABLE_PCLK_CAM1, 9, CLK_IGNORE_UNUSED, 0),
5340 GATE(CLK_PCLK_ISP_SPI1, "pclk_isp_spi1", "div_pclk_cam1_83",
5341 ENABLE_PCLK_CAM1, 8, CLK_IGNORE_UNUSED, 0),
5342 GATE(CLK_PCLK_ISP_SPI0, "pclk_isp_spi0", "div_pclk_cam1_83",
5343 ENABLE_PCLK_CAM1, 7, CLK_IGNORE_UNUSED, 0),
5344 GATE(CLK_PCLK_ISP_I2C2, "pclk_isp_i2c2", "div_pclk_cam1_83",
5345 ENABLE_PCLK_CAM1, 6, CLK_IGNORE_UNUSED, 0),
5346 GATE(CLK_PCLK_ISP_I2C1, "pclk_isp_i2c1", "div_pclk_cam1_83",
5347 ENABLE_PCLK_CAM1, 5, CLK_IGNORE_UNUSED, 0),
5348 GATE(CLK_PCLK_ISP_I2C0, "pclk_isp_i2c0", "div_pclk_cam1_83",
5349 ENABLE_PCLK_CAM1, 4, CLK_IGNORE_UNUSED, 0),
5350 GATE(CLK_PCLK_ISP_MPWM, "pclk_isp_mpwm", "div_pclk_cam1_83",
5351 ENABLE_PCLK_CAM1, 3, CLK_IGNORE_UNUSED, 0),
5352 GATE(CLK_PCLK_FD, "pclk_fd", "div_pclk_fd",
5353 ENABLE_PCLK_CAM1, 3, CLK_IGNORE_UNUSED, 0),
5354 GATE(CLK_PCLK_LITE_C, "pclk_lite_c", "div_pclk_lite_c",
5355 ENABLE_PCLK_CAM1, 1, CLK_IGNORE_UNUSED, 0),
5356 GATE(CLK_PCLK_CSIS2, "pclk_csis2", "div_pclk_cam1_166",
5357 ENABLE_PCLK_CAM1, 0, CLK_IGNORE_UNUSED, 0),
5359 /* ENABLE_SCLK_CAM1 */
5360 GATE(CLK_SCLK_ISP_I2C2, "sclk_isp_i2c2", "oscclk", ENABLE_SCLK_CAM1,
5362 GATE(CLK_SCLK_ISP_I2C1, "sclk_isp_i2c1", "oscclk", ENABLE_SCLK_CAM1,
5364 GATE(CLK_SCLK_ISP_I2C0, "sclk_isp_i2c0", "oscclk", ENABLE_SCLK_CAM1,
5366 GATE(CLK_SCLK_ISP_PWM, "sclk_isp_pwm", "oscclk", ENABLE_SCLK_CAM1,
5368 GATE(CLK_PHYCLK_RXBYTECLKHS0_S2B, "phyclk_rxbyteclkhs0_s2b",
5369 "mout_phyclk_rxbyteclkhs0_s2b_user",
5370 ENABLE_SCLK_CAM1, 11, 0, 0),
5371 GATE(CLK_SCLK_LITE_C_FREECNT, "sclk_lite_c_freecnt", "div_pclk_lite_c",
5372 ENABLE_SCLK_CAM1, 10, 0, 0),
5373 GATE(CLK_SCLK_PIXELASYNCM_FD, "sclk_pixelasyncm_fd", "div_aclk_fd",
5374 ENABLE_SCLK_CAM1, 9, 0, 0),
5375 GATE(CLK_SCLK_ISP_MCTADC, "sclk_isp_mctadc", "sclk_isp_mctadc_cam1",
5376 ENABLE_SCLK_CAM1, 7, 0, 0),
5377 GATE(CLK_SCLK_ISP_UART, "sclk_isp_uart", "mout_sclk_isp_uart_user",
5378 ENABLE_SCLK_CAM1, 6, 0, 0),
5379 GATE(CLK_SCLK_ISP_SPI1, "sclk_isp_spi1", "mout_sclk_isp_spi1_user",
5380 ENABLE_SCLK_CAM1, 5, 0, 0),
5381 GATE(CLK_SCLK_ISP_SPI0, "sclk_isp_spi0", "mout_sclk_isp_spi0_user",
5382 ENABLE_SCLK_CAM1, 4, 0, 0),
5383 GATE(CLK_SCLK_ISP_MPWM, "sclk_isp_mpwm", "div_sclk_isp_mpwm",
5384 ENABLE_SCLK_CAM1, 3, 0, 0),
5385 GATE(CLK_PCLK_DBG_ISP, "sclk_dbg_isp", "div_pclk_dbg_cam1",
5386 ENABLE_SCLK_CAM1, 2, 0, 0),
5387 GATE(CLK_ATCLK_ISP, "atclk_isp", "div_atclk_cam1",
5388 ENABLE_SCLK_CAM1, 1, 0, 0),
5389 GATE(CLK_SCLK_ISP_CA5, "sclk_isp_ca5", "mout_aclk_cam1_552_user",
5390 ENABLE_SCLK_CAM1, 0, 0, 0),
5393 static const struct samsung_cmu_info cam1_cmu_info __initconst = {
5394 .mux_clks = cam1_mux_clks,
5395 .nr_mux_clks = ARRAY_SIZE(cam1_mux_clks),
5396 .div_clks = cam1_div_clks,
5397 .nr_div_clks = ARRAY_SIZE(cam1_div_clks),
5398 .gate_clks = cam1_gate_clks,
5399 .nr_gate_clks = ARRAY_SIZE(cam1_gate_clks),
5400 .fixed_clks = cam1_fixed_clks,
5401 .nr_fixed_clks = ARRAY_SIZE(cam1_fixed_clks),
5402 .nr_clk_ids = CAM1_NR_CLK,
5403 .clk_regs = cam1_clk_regs,
5404 .nr_clk_regs = ARRAY_SIZE(cam1_clk_regs),
5407 static void __init exynos5433_cmu_cam1_init(struct device_node *np)
5409 samsung_cmu_register_one(np, &cam1_cmu_info);
5411 CLK_OF_DECLARE(exynos5433_cmu_cam1, "samsung,exynos5433-cmu-cam1",
5412 exynos5433_cmu_cam1_init);