2 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3 * Authors: Thomas Abraham <thomas.ab@samsung.com>
4 * Chander Kashyap <k.chander@samsung.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * Common Clock Framework support for Exynos5420 SoC.
13 #include <dt-bindings/clock/exynos5420.h>
14 #include <linux/slab.h>
15 #include <linux/clk-provider.h>
17 #include <linux/of_address.h>
18 #include <linux/syscore_ops.h>
23 #define APLL_CON0 0x100
25 #define DIV_CPU0 0x500
26 #define DIV_CPU1 0x504
27 #define GATE_BUS_CPU 0x700
28 #define GATE_SCLK_CPU 0x800
29 #define CLKOUT_CMU_CPU 0xa00
30 #define SRC_MASK_CPERI 0x4300
31 #define GATE_IP_G2D 0x8800
32 #define CPLL_LOCK 0x10020
33 #define DPLL_LOCK 0x10030
34 #define EPLL_LOCK 0x10040
35 #define RPLL_LOCK 0x10050
36 #define IPLL_LOCK 0x10060
37 #define SPLL_LOCK 0x10070
38 #define VPLL_LOCK 0x10080
39 #define MPLL_LOCK 0x10090
40 #define CPLL_CON0 0x10120
41 #define DPLL_CON0 0x10128
42 #define EPLL_CON0 0x10130
43 #define EPLL_CON1 0x10134
44 #define EPLL_CON2 0x10138
45 #define RPLL_CON0 0x10140
46 #define RPLL_CON1 0x10144
47 #define RPLL_CON2 0x10148
48 #define IPLL_CON0 0x10150
49 #define SPLL_CON0 0x10160
50 #define VPLL_CON0 0x10170
51 #define MPLL_CON0 0x10180
52 #define SRC_TOP0 0x10200
53 #define SRC_TOP1 0x10204
54 #define SRC_TOP2 0x10208
55 #define SRC_TOP3 0x1020c
56 #define SRC_TOP4 0x10210
57 #define SRC_TOP5 0x10214
58 #define SRC_TOP6 0x10218
59 #define SRC_TOP7 0x1021c
60 #define SRC_TOP8 0x10220 /* 5800 specific */
61 #define SRC_TOP9 0x10224 /* 5800 specific */
62 #define SRC_DISP10 0x1022c
63 #define SRC_MAU 0x10240
64 #define SRC_FSYS 0x10244
65 #define SRC_PERIC0 0x10250
66 #define SRC_PERIC1 0x10254
67 #define SRC_ISP 0x10270
68 #define SRC_CAM 0x10274 /* 5800 specific */
69 #define SRC_TOP10 0x10280
70 #define SRC_TOP11 0x10284
71 #define SRC_TOP12 0x10288
72 #define SRC_TOP13 0x1028c /* 5800 specific */
73 #define SRC_MASK_TOP0 0x10300
74 #define SRC_MASK_TOP1 0x10304
75 #define SRC_MASK_TOP2 0x10308
76 #define SRC_MASK_TOP7 0x1031c
77 #define SRC_MASK_DISP10 0x1032c
78 #define SRC_MASK_MAU 0x10334
79 #define SRC_MASK_FSYS 0x10340
80 #define SRC_MASK_PERIC0 0x10350
81 #define SRC_MASK_PERIC1 0x10354
82 #define SRC_MASK_ISP 0x10370
83 #define DIV_TOP0 0x10500
84 #define DIV_TOP1 0x10504
85 #define DIV_TOP2 0x10508
86 #define DIV_TOP8 0x10520 /* 5800 specific */
87 #define DIV_TOP9 0x10524 /* 5800 specific */
88 #define DIV_DISP10 0x1052c
89 #define DIV_MAU 0x10544
90 #define DIV_FSYS0 0x10548
91 #define DIV_FSYS1 0x1054c
92 #define DIV_FSYS2 0x10550
93 #define DIV_PERIC0 0x10558
94 #define DIV_PERIC1 0x1055c
95 #define DIV_PERIC2 0x10560
96 #define DIV_PERIC3 0x10564
97 #define DIV_PERIC4 0x10568
98 #define DIV_CAM 0x10574 /* 5800 specific */
99 #define SCLK_DIV_ISP0 0x10580
100 #define SCLK_DIV_ISP1 0x10584
101 #define DIV2_RATIO0 0x10590
102 #define DIV4_RATIO 0x105a0
103 #define GATE_BUS_TOP 0x10700
104 #define GATE_BUS_DISP1 0x10728
105 #define GATE_BUS_GEN 0x1073c
106 #define GATE_BUS_FSYS0 0x10740
107 #define GATE_BUS_FSYS2 0x10748
108 #define GATE_BUS_PERIC 0x10750
109 #define GATE_BUS_PERIC1 0x10754
110 #define GATE_BUS_PERIS0 0x10760
111 #define GATE_BUS_PERIS1 0x10764
112 #define GATE_BUS_NOC 0x10770
113 #define GATE_TOP_SCLK_ISP 0x10870
114 #define GATE_IP_GSCL0 0x10910
115 #define GATE_IP_GSCL1 0x10920
116 #define GATE_IP_CAM 0x10924 /* 5800 specific */
117 #define GATE_IP_MFC 0x1092c
118 #define GATE_IP_DISP1 0x10928
119 #define GATE_IP_G3D 0x10930
120 #define GATE_IP_GEN 0x10934
121 #define GATE_IP_FSYS 0x10944
122 #define GATE_IP_PERIC 0x10950
123 #define GATE_IP_PERIS 0x10960
124 #define GATE_IP_MSCL 0x10970
125 #define GATE_TOP_SCLK_GSCL 0x10820
126 #define GATE_TOP_SCLK_DISP1 0x10828
127 #define GATE_TOP_SCLK_MAU 0x1083c
128 #define GATE_TOP_SCLK_FSYS 0x10840
129 #define GATE_TOP_SCLK_PERIC 0x10850
130 #define TOP_SPARE2 0x10b08
131 #define BPLL_LOCK 0x20010
132 #define BPLL_CON0 0x20110
133 #define KPLL_LOCK 0x28000
134 #define KPLL_CON0 0x28100
135 #define SRC_KFC 0x28200
136 #define DIV_KFC0 0x28500
138 /* Exynos5x SoC type */
146 apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll,
148 nr_plls /* number of PLLs */
151 static void __iomem *reg_base;
152 static enum exynos5x_soc exynos5x_soc;
154 #ifdef CONFIG_PM_SLEEP
155 static struct samsung_clk_reg_dump *exynos5x_save;
156 static struct samsung_clk_reg_dump *exynos5800_save;
159 * list of controller registers to be saved and restored during a
160 * suspend/resume cycle.
162 static unsigned long exynos5x_clk_regs[] __initdata = {
258 static unsigned long exynos5800_clk_regs[] __initdata = {
269 static const struct samsung_clk_reg_dump exynos5420_set_clksrc[] = {
270 { .offset = SRC_MASK_CPERI, .value = 0xffffffff, },
271 { .offset = SRC_MASK_TOP0, .value = 0x11111111, },
272 { .offset = SRC_MASK_TOP1, .value = 0x11101111, },
273 { .offset = SRC_MASK_TOP2, .value = 0x11111110, },
274 { .offset = SRC_MASK_TOP7, .value = 0x00111100, },
275 { .offset = SRC_MASK_DISP10, .value = 0x11111110, },
276 { .offset = SRC_MASK_MAU, .value = 0x10000000, },
277 { .offset = SRC_MASK_FSYS, .value = 0x11111110, },
278 { .offset = SRC_MASK_PERIC0, .value = 0x11111110, },
279 { .offset = SRC_MASK_PERIC1, .value = 0x11111100, },
280 { .offset = SRC_MASK_ISP, .value = 0x11111000, },
281 { .offset = GATE_BUS_TOP, .value = 0xffffffff, },
282 { .offset = GATE_BUS_DISP1, .value = 0xffffffff, },
283 { .offset = GATE_IP_PERIC, .value = 0xffffffff, },
284 { .offset = GATE_IP_PERIS, .value = 0xffffffff, },
287 static int exynos5420_clk_suspend(void)
289 samsung_clk_save(reg_base, exynos5x_save,
290 ARRAY_SIZE(exynos5x_clk_regs));
292 if (exynos5x_soc == EXYNOS5800)
293 samsung_clk_save(reg_base, exynos5800_save,
294 ARRAY_SIZE(exynos5800_clk_regs));
296 samsung_clk_restore(reg_base, exynos5420_set_clksrc,
297 ARRAY_SIZE(exynos5420_set_clksrc));
302 static void exynos5420_clk_resume(void)
304 samsung_clk_restore(reg_base, exynos5x_save,
305 ARRAY_SIZE(exynos5x_clk_regs));
307 if (exynos5x_soc == EXYNOS5800)
308 samsung_clk_restore(reg_base, exynos5800_save,
309 ARRAY_SIZE(exynos5800_clk_regs));
312 static struct syscore_ops exynos5420_clk_syscore_ops = {
313 .suspend = exynos5420_clk_suspend,
314 .resume = exynos5420_clk_resume,
317 static void exynos5420_clk_sleep_init(void)
319 exynos5x_save = samsung_clk_alloc_reg_dump(exynos5x_clk_regs,
320 ARRAY_SIZE(exynos5x_clk_regs));
321 if (!exynos5x_save) {
322 pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
327 if (exynos5x_soc == EXYNOS5800) {
329 samsung_clk_alloc_reg_dump(exynos5800_clk_regs,
330 ARRAY_SIZE(exynos5800_clk_regs));
331 if (!exynos5800_save)
335 register_syscore_ops(&exynos5420_clk_syscore_ops);
338 kfree(exynos5x_save);
339 pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
344 static void exynos5420_clk_sleep_init(void) {}
347 /* list of all parent clocks */
348 PNAME(mout_mspll_cpu_p) = {"mout_sclk_cpll", "mout_sclk_dpll",
349 "mout_sclk_mpll", "mout_sclk_spll"};
350 PNAME(mout_cpu_p) = {"mout_apll" , "mout_mspll_cpu"};
351 PNAME(mout_kfc_p) = {"mout_kpll" , "mout_mspll_kfc"};
352 PNAME(mout_apll_p) = {"fin_pll", "fout_apll"};
353 PNAME(mout_bpll_p) = {"fin_pll", "fout_bpll"};
354 PNAME(mout_cpll_p) = {"fin_pll", "fout_cpll"};
355 PNAME(mout_dpll_p) = {"fin_pll", "fout_dpll"};
356 PNAME(mout_epll_p) = {"fin_pll", "fout_epll"};
357 PNAME(mout_ipll_p) = {"fin_pll", "fout_ipll"};
358 PNAME(mout_kpll_p) = {"fin_pll", "fout_kpll"};
359 PNAME(mout_mpll_p) = {"fin_pll", "fout_mpll"};
360 PNAME(mout_rpll_p) = {"fin_pll", "fout_rpll"};
361 PNAME(mout_spll_p) = {"fin_pll", "fout_spll"};
362 PNAME(mout_vpll_p) = {"fin_pll", "fout_vpll"};
364 PNAME(mout_group1_p) = {"mout_sclk_cpll", "mout_sclk_dpll",
366 PNAME(mout_group2_p) = {"fin_pll", "mout_sclk_cpll",
367 "mout_sclk_dpll", "mout_sclk_mpll", "mout_sclk_spll",
368 "mout_sclk_ipll", "mout_sclk_epll", "mout_sclk_rpll"};
369 PNAME(mout_group3_p) = {"mout_sclk_rpll", "mout_sclk_spll"};
370 PNAME(mout_group4_p) = {"mout_sclk_ipll", "mout_sclk_dpll", "mout_sclk_mpll"};
371 PNAME(mout_group5_p) = {"mout_sclk_vpll", "mout_sclk_dpll"};
373 PNAME(mout_fimd1_final_p) = {"mout_fimd1", "mout_fimd1_opt"};
374 PNAME(mout_sw_aclk66_p) = {"dout_aclk66", "mout_sclk_spll"};
375 PNAME(mout_user_aclk66_peric_p) = { "fin_pll", "mout_sw_aclk66"};
376 PNAME(mout_user_pclk66_gpio_p) = {"mout_sw_aclk66", "ff_sw_aclk66"};
378 PNAME(mout_sw_aclk200_fsys_p) = {"dout_aclk200_fsys", "mout_sclk_spll"};
379 PNAME(mout_sw_pclk200_fsys_p) = {"dout_pclk200_fsys", "mout_sclk_spll"};
380 PNAME(mout_user_pclk200_fsys_p) = {"fin_pll", "mout_sw_pclk200_fsys"};
381 PNAME(mout_user_aclk200_fsys_p) = {"fin_pll", "mout_sw_aclk200_fsys"};
383 PNAME(mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2", "mout_sclk_spll"};
384 PNAME(mout_user_aclk200_fsys2_p) = {"fin_pll", "mout_sw_aclk200_fsys2"};
385 PNAME(mout_sw_aclk100_noc_p) = {"dout_aclk100_noc", "mout_sclk_spll"};
386 PNAME(mout_user_aclk100_noc_p) = {"fin_pll", "mout_sw_aclk100_noc"};
388 PNAME(mout_sw_aclk400_wcore_p) = {"dout_aclk400_wcore", "mout_sclk_spll"};
389 PNAME(mout_aclk400_wcore_bpll_p) = {"mout_aclk400_wcore", "sclk_bpll"};
390 PNAME(mout_user_aclk400_wcore_p) = {"fin_pll", "mout_sw_aclk400_wcore"};
392 PNAME(mout_sw_aclk400_isp_p) = {"dout_aclk400_isp", "mout_sclk_spll"};
393 PNAME(mout_user_aclk400_isp_p) = {"fin_pll", "mout_sw_aclk400_isp"};
395 PNAME(mout_sw_aclk333_432_isp0_p) = {"dout_aclk333_432_isp0",
397 PNAME(mout_user_aclk333_432_isp0_p) = {"fin_pll", "mout_sw_aclk333_432_isp0"};
399 PNAME(mout_sw_aclk333_432_isp_p) = {"dout_aclk333_432_isp", "mout_sclk_spll"};
400 PNAME(mout_user_aclk333_432_isp_p) = {"fin_pll", "mout_sw_aclk333_432_isp"};
402 PNAME(mout_sw_aclk200_p) = {"dout_aclk200", "mout_sclk_spll"};
403 PNAME(mout_user_aclk200_disp1_p) = {"fin_pll", "mout_sw_aclk200"};
405 PNAME(mout_sw_aclk400_mscl_p) = {"dout_aclk400_mscl", "mout_sclk_spll"};
406 PNAME(mout_user_aclk400_mscl_p) = {"fin_pll", "mout_sw_aclk400_mscl"};
408 PNAME(mout_sw_aclk333_p) = {"dout_aclk333", "mout_sclk_spll"};
409 PNAME(mout_user_aclk333_p) = {"fin_pll", "mout_sw_aclk333"};
411 PNAME(mout_sw_aclk166_p) = {"dout_aclk166", "mout_sclk_spll"};
412 PNAME(mout_user_aclk166_p) = {"fin_pll", "mout_sw_aclk166"};
414 PNAME(mout_sw_aclk266_p) = {"dout_aclk266", "mout_sclk_spll"};
415 PNAME(mout_user_aclk266_p) = {"fin_pll", "mout_sw_aclk266"};
416 PNAME(mout_user_aclk266_isp_p) = {"fin_pll", "mout_sw_aclk266"};
418 PNAME(mout_sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl", "mout_sclk_spll"};
419 PNAME(mout_user_aclk333_432_gscl_p) = {"fin_pll", "mout_sw_aclk333_432_gscl"};
421 PNAME(mout_sw_aclk300_gscl_p) = {"dout_aclk300_gscl", "mout_sclk_spll"};
422 PNAME(mout_user_aclk300_gscl_p) = {"fin_pll", "mout_sw_aclk300_gscl"};
424 PNAME(mout_sw_aclk300_disp1_p) = {"dout_aclk300_disp1", "mout_sclk_spll"};
425 PNAME(mout_sw_aclk400_disp1_p) = {"dout_aclk400_disp1", "mout_sclk_spll"};
426 PNAME(mout_user_aclk300_disp1_p) = {"fin_pll", "mout_sw_aclk300_disp1"};
427 PNAME(mout_user_aclk400_disp1_p) = {"fin_pll", "mout_sw_aclk400_disp1"};
429 PNAME(mout_sw_aclk300_jpeg_p) = {"dout_aclk300_jpeg", "mout_sclk_spll"};
430 PNAME(mout_user_aclk300_jpeg_p) = {"fin_pll", "mout_sw_aclk300_jpeg"};
432 PNAME(mout_sw_aclk_g3d_p) = {"dout_aclk_g3d", "mout_sclk_spll"};
433 PNAME(mout_user_aclk_g3d_p) = {"fin_pll", "mout_sw_aclk_g3d"};
435 PNAME(mout_sw_aclk266_g2d_p) = {"dout_aclk266_g2d", "mout_sclk_spll"};
436 PNAME(mout_user_aclk266_g2d_p) = {"fin_pll", "mout_sw_aclk266_g2d"};
438 PNAME(mout_sw_aclk333_g2d_p) = {"dout_aclk333_g2d", "mout_sclk_spll"};
439 PNAME(mout_user_aclk333_g2d_p) = {"fin_pll", "mout_sw_aclk333_g2d"};
441 PNAME(mout_audio0_p) = {"fin_pll", "cdclk0", "mout_sclk_dpll",
442 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
443 "mout_sclk_epll", "mout_sclk_rpll"};
444 PNAME(mout_audio1_p) = {"fin_pll", "cdclk1", "mout_sclk_dpll",
445 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
446 "mout_sclk_epll", "mout_sclk_rpll"};
447 PNAME(mout_audio2_p) = {"fin_pll", "cdclk2", "mout_sclk_dpll",
448 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
449 "mout_sclk_epll", "mout_sclk_rpll"};
450 PNAME(mout_spdif_p) = {"fin_pll", "dout_audio0", "dout_audio1",
451 "dout_audio2", "spdif_extclk", "mout_sclk_ipll",
452 "mout_sclk_epll", "mout_sclk_rpll"};
453 PNAME(mout_hdmi_p) = {"dout_hdmi_pixel", "sclk_hdmiphy"};
454 PNAME(mout_maudio0_p) = {"fin_pll", "maudio_clk", "mout_sclk_dpll",
455 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
456 "mout_sclk_epll", "mout_sclk_rpll"};
457 PNAME(mout_mau_epll_clk_p) = {"mout_sclk_epll", "mout_sclk_dpll",
458 "mout_sclk_mpll", "mout_sclk_spll"};
459 /* List of parents specific to exynos5800 */
460 PNAME(mout_epll2_5800_p) = { "mout_sclk_epll", "ff_dout_epll2" };
461 PNAME(mout_group1_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
462 "mout_sclk_mpll", "ff_dout_spll2" };
463 PNAME(mout_group2_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
464 "mout_sclk_mpll", "ff_dout_spll2",
465 "mout_epll2", "mout_sclk_ipll" };
466 PNAME(mout_group3_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
467 "mout_sclk_mpll", "ff_dout_spll2",
469 PNAME(mout_group5_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
470 "mout_sclk_mpll", "mout_sclk_spll" };
471 PNAME(mout_group6_5800_p) = { "mout_sclk_ipll", "mout_sclk_dpll",
472 "mout_sclk_mpll", "ff_dout_spll2" };
473 PNAME(mout_group7_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
474 "mout_sclk_mpll", "mout_sclk_spll",
475 "mout_epll2", "mout_sclk_ipll" };
476 PNAME(mout_mau_epll_clk_5800_p) = { "mout_sclk_epll", "mout_sclk_dpll",
479 PNAME(mout_group8_5800_p) = { "dout_aclk432_scaler", "dout_sclk_sw" };
480 PNAME(mout_group9_5800_p) = { "dout_osc_div", "mout_sw_aclk432_scaler" };
481 PNAME(mout_group10_5800_p) = { "dout_aclk432_cam", "dout_sclk_sw" };
482 PNAME(mout_group11_5800_p) = { "dout_osc_div", "mout_sw_aclk432_cam" };
483 PNAME(mout_group12_5800_p) = { "dout_aclkfl1_550_cam", "dout_sclk_sw" };
484 PNAME(mout_group13_5800_p) = { "dout_osc_div", "mout_sw_aclkfl1_550_cam" };
485 PNAME(mout_group14_5800_p) = { "dout_aclk550_cam", "dout_sclk_sw" };
486 PNAME(mout_group15_5800_p) = { "dout_osc_div", "mout_sw_aclk550_cam" };
488 /* fixed rate clocks generated outside the soc */
489 static struct samsung_fixed_rate_clock
490 exynos5x_fixed_rate_ext_clks[] __initdata = {
491 FRATE(CLK_FIN_PLL, "fin_pll", NULL, CLK_IS_ROOT, 0),
494 /* fixed rate clocks generated inside the soc */
495 static struct samsung_fixed_rate_clock exynos5x_fixed_rate_clks[] __initdata = {
496 FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000),
497 FRATE(0, "sclk_pwi", NULL, CLK_IS_ROOT, 24000000),
498 FRATE(0, "sclk_usbh20", NULL, CLK_IS_ROOT, 48000000),
499 FRATE(0, "mphy_refclk_ixtal24", NULL, CLK_IS_ROOT, 48000000),
500 FRATE(0, "sclk_usbh20_scan_clk", NULL, CLK_IS_ROOT, 480000000),
503 static struct samsung_fixed_factor_clock
504 exynos5x_fixed_factor_clks[] __initdata = {
505 FFACTOR(0, "ff_hsic_12m", "fin_pll", 1, 2, 0),
506 FFACTOR(0, "ff_sw_aclk66", "mout_sw_aclk66", 1, 2, 0),
509 static struct samsung_fixed_factor_clock
510 exynos5800_fixed_factor_clks[] __initdata = {
511 FFACTOR(0, "ff_dout_epll2", "mout_sclk_epll", 1, 2, 0),
512 FFACTOR(0, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0),
515 static struct samsung_mux_clock exynos5800_mux_clks[] __initdata = {
516 MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3),
517 MUX(0, "mout_aclk400_mscl", mout_group3_5800_p, SRC_TOP0, 4, 3),
518 MUX(0, "mout_aclk400_wcore", mout_group2_5800_p, SRC_TOP0, 16, 3),
519 MUX(0, "mout_aclk100_noc", mout_group1_5800_p, SRC_TOP0, 20, 2),
521 MUX(0, "mout_aclk333_432_gscl", mout_group6_5800_p, SRC_TOP1, 0, 2),
522 MUX(0, "mout_aclk333_432_isp", mout_group6_5800_p, SRC_TOP1, 4, 2),
523 MUX(0, "mout_aclk333_432_isp0", mout_group6_5800_p, SRC_TOP1, 12, 2),
524 MUX(0, "mout_aclk266", mout_group5_5800_p, SRC_TOP1, 20, 2),
525 MUX(0, "mout_aclk333", mout_group1_5800_p, SRC_TOP1, 28, 2),
527 MUX(0, "mout_aclk400_disp1", mout_group7_5800_p, SRC_TOP2, 4, 3),
528 MUX(0, "mout_aclk333_g2d", mout_group5_5800_p, SRC_TOP2, 8, 2),
529 MUX(0, "mout_aclk266_g2d", mout_group5_5800_p, SRC_TOP2, 12, 2),
530 MUX(0, "mout_aclk300_jpeg", mout_group5_5800_p, SRC_TOP2, 20, 2),
531 MUX(0, "mout_aclk300_disp1", mout_group5_5800_p, SRC_TOP2, 24, 2),
532 MUX(0, "mout_aclk300_gscl", mout_group5_5800_p, SRC_TOP2, 28, 2),
534 MUX(0, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p, SRC_TOP7,
536 MUX(0, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1),
537 MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1),
539 MUX(0, "mout_aclk550_cam", mout_group3_5800_p, SRC_TOP8, 16, 3),
540 MUX(0, "mout_aclkfl1_550_cam", mout_group3_5800_p, SRC_TOP8, 20, 3),
541 MUX(0, "mout_aclk432_cam", mout_group6_5800_p, SRC_TOP8, 24, 2),
542 MUX(0, "mout_aclk432_scaler", mout_group6_5800_p, SRC_TOP8, 28, 2),
544 MUX(0, "mout_user_aclk550_cam", mout_group15_5800_p,
546 MUX(0, "mout_user_aclkfl1_550_cam", mout_group13_5800_p,
548 MUX(0, "mout_user_aclk432_cam", mout_group11_5800_p,
550 MUX(0, "mout_user_aclk432_scaler", mout_group9_5800_p,
553 MUX(0, "mout_sw_aclk550_cam", mout_group14_5800_p, SRC_TOP13, 16, 1),
554 MUX(0, "mout_sw_aclkfl1_550_cam", mout_group12_5800_p,
556 MUX(0, "mout_sw_aclk432_cam", mout_group10_5800_p,
558 MUX(0, "mout_sw_aclk432_scaler", mout_group8_5800_p,
561 MUX(0, "mout_fimd1", mout_group2_p, SRC_DISP10, 4, 3),
564 static struct samsung_div_clock exynos5800_div_clks[] __initdata = {
565 DIV(0, "dout_aclk400_wcore", "mout_aclk400_wcore", DIV_TOP0, 16, 3),
567 DIV(0, "dout_aclk550_cam", "mout_aclk550_cam",
569 DIV(0, "dout_aclkfl1_550_cam", "mout_aclkfl1_550_cam",
571 DIV(0, "dout_aclk432_cam", "mout_aclk432_cam",
573 DIV(0, "dout_aclk432_scaler", "mout_aclk432_scaler",
576 DIV(0, "dout_osc_div", "fin_pll", DIV_TOP9, 20, 3),
577 DIV(0, "dout_sclk_sw", "sclk_spll", DIV_TOP9, 24, 6),
580 static struct samsung_gate_clock exynos5800_gate_clks[] __initdata = {
581 GATE(CLK_ACLK550_CAM, "aclk550_cam", "mout_user_aclk550_cam",
582 GATE_BUS_TOP, 24, 0, 0),
583 GATE(CLK_ACLK432_SCALER, "aclk432_scaler", "mout_user_aclk432_scaler",
584 GATE_BUS_TOP, 27, 0, 0),
587 static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
588 MUX(0, "sclk_bpll", mout_bpll_p, TOP_SPARE2, 0, 1),
589 MUX(0, "mout_aclk400_wcore_bpll", mout_aclk400_wcore_bpll_p,
592 MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2),
593 MUX_A(0, "mout_aclk400_mscl", mout_group1_p,
594 SRC_TOP0, 4, 2, "aclk400_mscl"),
595 MUX(0, "mout_aclk400_wcore", mout_group1_p, SRC_TOP0, 16, 2),
596 MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2),
598 MUX(0, "mout_aclk333_432_gscl", mout_group4_p, SRC_TOP1, 0, 2),
599 MUX(0, "mout_aclk333_432_isp", mout_group4_p,
601 MUX(0, "mout_aclk333_432_isp0", mout_group4_p, SRC_TOP1, 12, 2),
602 MUX(0, "mout_aclk266", mout_group1_p, SRC_TOP1, 20, 2),
603 MUX(0, "mout_aclk333", mout_group1_p, SRC_TOP1, 28, 2),
605 MUX(0, "mout_aclk400_disp1", mout_group1_p, SRC_TOP2, 4, 2),
606 MUX(0, "mout_aclk333_g2d", mout_group1_p, SRC_TOP2, 8, 2),
607 MUX(0, "mout_aclk266_g2d", mout_group1_p, SRC_TOP2, 12, 2),
608 MUX(0, "mout_aclk300_jpeg", mout_group1_p, SRC_TOP2, 20, 2),
609 MUX(0, "mout_aclk300_disp1", mout_group1_p, SRC_TOP2, 24, 2),
610 MUX(0, "mout_aclk300_gscl", mout_group1_p, SRC_TOP2, 28, 2),
612 MUX(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2),
614 MUX(0, "mout_fimd1", mout_group3_p, SRC_DISP10, 4, 1),
617 static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
618 DIV(0, "dout_aclk400_wcore", "mout_aclk400_wcore_bpll",
622 static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
623 MUX(0, "mout_user_pclk66_gpio", mout_user_pclk66_gpio_p,
625 MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2),
626 MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2),
628 MUX(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1),
629 MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
630 MUX(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1),
631 MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
633 MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2),
634 MUX(0, "mout_aclk200_fsys2", mout_group1_p, SRC_TOP0, 12, 2),
635 MUX(0, "mout_pclk200_fsys", mout_group1_p, SRC_TOP0, 24, 2),
636 MUX(0, "mout_aclk200_fsys", mout_group1_p, SRC_TOP0, 28, 2),
638 MUX(0, "mout_aclk66", mout_group1_p, SRC_TOP1, 8, 2),
639 MUX(0, "mout_aclk166", mout_group1_p, SRC_TOP1, 24, 2),
641 MUX(0, "mout_aclk_g3d", mout_group5_p, SRC_TOP2, 16, 1),
643 MUX(0, "mout_user_aclk400_isp", mout_user_aclk400_isp_p,
645 MUX(0, "mout_user_aclk400_mscl", mout_user_aclk400_mscl_p,
647 MUX(CLK_MOUT_USER_ACLK200_DISP1, "mout_user_aclk200_disp1",
648 mout_user_aclk200_disp1_p, SRC_TOP3, 8, 1),
649 MUX(0, "mout_user_aclk200_fsys2", mout_user_aclk200_fsys2_p,
651 MUX(0, "mout_user_aclk400_wcore", mout_user_aclk400_wcore_p,
653 MUX(0, "mout_user_aclk100_noc", mout_user_aclk100_noc_p,
655 MUX(0, "mout_user_pclk200_fsys", mout_user_pclk200_fsys_p,
657 MUX(0, "mout_user_aclk200_fsys", mout_user_aclk200_fsys_p,
660 MUX(0, "mout_user_aclk333_432_gscl", mout_user_aclk333_432_gscl_p,
662 MUX(0, "mout_user_aclk333_432_isp", mout_user_aclk333_432_isp_p,
664 MUX(0, "mout_user_aclk66_peric", mout_user_aclk66_peric_p,
666 MUX(0, "mout_user_aclk333_432_isp0", mout_user_aclk333_432_isp0_p,
668 MUX(0, "mout_user_aclk266_isp", mout_user_aclk266_isp_p,
670 MUX(0, "mout_user_aclk266", mout_user_aclk266_p, SRC_TOP4, 20, 1),
671 MUX(0, "mout_user_aclk166", mout_user_aclk166_p, SRC_TOP4, 24, 1),
672 MUX(CLK_MOUT_USER_ACLK333, "mout_user_aclk333", mout_user_aclk333_p,
675 MUX(CLK_MOUT_USER_ACLK400_DISP1, "mout_user_aclk400_disp1",
676 mout_user_aclk400_disp1_p, SRC_TOP5, 0, 1),
677 MUX(0, "mout_user_aclk66_psgen", mout_user_aclk66_peric_p,
679 MUX(0, "mout_user_aclk333_g2d", mout_user_aclk333_g2d_p,
681 MUX(0, "mout_user_aclk266_g2d", mout_user_aclk266_g2d_p,
683 MUX(CLK_MOUT_G3D, "mout_user_aclk_g3d", mout_user_aclk_g3d_p,
685 MUX(0, "mout_user_aclk300_jpeg", mout_user_aclk300_jpeg_p,
687 MUX(CLK_MOUT_USER_ACLK300_DISP1, "mout_user_aclk300_disp1",
688 mout_user_aclk300_disp1_p, SRC_TOP5, 24, 1),
689 MUX(0, "mout_user_aclk300_gscl", mout_user_aclk300_gscl_p,
692 MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1),
693 MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1),
694 MUX(0, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1),
695 MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1),
696 MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1),
697 MUX(0, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1),
698 MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1),
699 MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1),
701 MUX(0, "mout_sw_aclk400_isp", mout_sw_aclk400_isp_p,
703 MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p,
705 MUX(CLK_MOUT_SW_ACLK200, "mout_sw_aclk200", mout_sw_aclk200_p,
707 MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p,
709 MUX(0, "mout_sw_aclk400_wcore", mout_sw_aclk400_wcore_p,
711 MUX(0, "mout_sw_aclk100_noc", mout_sw_aclk100_noc_p,
713 MUX(0, "mout_sw_pclk200_fsys", mout_sw_pclk200_fsys_p,
715 MUX(0, "mout_sw_aclk200_fsys", mout_sw_aclk200_fsys_p,
718 MUX(0, "mout_sw_aclk333_432_gscl", mout_sw_aclk333_432_gscl_p,
720 MUX(0, "mout_sw_aclk333_432_isp", mout_sw_aclk333_432_isp_p,
722 MUX(0, "mout_sw_aclk66", mout_sw_aclk66_p, SRC_TOP11, 8, 1),
723 MUX(0, "mout_sw_aclk333_432_isp0", mout_sw_aclk333_432_isp0_p,
725 MUX(0, "mout_sw_aclk266", mout_sw_aclk266_p, SRC_TOP11, 20, 1),
726 MUX(0, "mout_sw_aclk166", mout_sw_aclk166_p, SRC_TOP11, 24, 1),
727 MUX(CLK_MOUT_SW_ACLK333, "mout_sw_aclk333", mout_sw_aclk333_p,
730 MUX(CLK_MOUT_SW_ACLK400, "mout_sw_aclk400_disp1",
731 mout_sw_aclk400_disp1_p, SRC_TOP12, 4, 1),
732 MUX(0, "mout_sw_aclk333_g2d", mout_sw_aclk333_g2d_p,
734 MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p,
736 MUX(0, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, SRC_TOP12, 16, 1),
737 MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p,
739 MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1",
740 mout_sw_aclk300_disp1_p, SRC_TOP12, 24, 1),
741 MUX(0, "mout_sw_aclk300_gscl", mout_sw_aclk300_gscl_p,
745 MUX(0, "mout_mipi1", mout_group2_p, SRC_DISP10, 16, 3),
746 MUX(0, "mout_dp1", mout_group2_p, SRC_DISP10, 20, 3),
747 MUX(0, "mout_pixel", mout_group2_p, SRC_DISP10, 24, 3),
748 MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP10, 28, 1),
749 MUX(0, "mout_fimd1_opt", mout_group2_p, SRC_DISP10, 8, 3),
751 MUX(0, "mout_fimd1_final", mout_fimd1_final_p, TOP_SPARE2, 8, 1),
754 MUX(CLK_MOUT_MAUDIO0, "mout_maudio0", mout_maudio0_p, SRC_MAU, 28, 3),
757 MUX(0, "mout_usbd301", mout_group2_p, SRC_FSYS, 4, 3),
758 MUX(0, "mout_mmc0", mout_group2_p, SRC_FSYS, 8, 3),
759 MUX(0, "mout_mmc1", mout_group2_p, SRC_FSYS, 12, 3),
760 MUX(0, "mout_mmc2", mout_group2_p, SRC_FSYS, 16, 3),
761 MUX(0, "mout_usbd300", mout_group2_p, SRC_FSYS, 20, 3),
762 MUX(0, "mout_unipro", mout_group2_p, SRC_FSYS, 24, 3),
763 MUX(0, "mout_mphy_refclk", mout_group2_p, SRC_FSYS, 28, 3),
766 MUX(0, "mout_uart0", mout_group2_p, SRC_PERIC0, 4, 3),
767 MUX(0, "mout_uart1", mout_group2_p, SRC_PERIC0, 8, 3),
768 MUX(0, "mout_uart2", mout_group2_p, SRC_PERIC0, 12, 3),
769 MUX(0, "mout_uart3", mout_group2_p, SRC_PERIC0, 16, 3),
770 MUX(0, "mout_pwm", mout_group2_p, SRC_PERIC0, 24, 3),
771 MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC0, 28, 3),
772 MUX(0, "mout_audio0", mout_audio0_p, SRC_PERIC1, 8, 3),
773 MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 12, 3),
774 MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 16, 3),
775 MUX(0, "mout_spi0", mout_group2_p, SRC_PERIC1, 20, 3),
776 MUX(0, "mout_spi1", mout_group2_p, SRC_PERIC1, 24, 3),
777 MUX(0, "mout_spi2", mout_group2_p, SRC_PERIC1, 28, 3),
780 MUX(0, "mout_pwm_isp", mout_group2_p, SRC_ISP, 24, 3),
781 MUX(0, "mout_uart_isp", mout_group2_p, SRC_ISP, 20, 3),
782 MUX(0, "mout_spi0_isp", mout_group2_p, SRC_ISP, 12, 3),
783 MUX(0, "mout_spi1_isp", mout_group2_p, SRC_ISP, 16, 3),
784 MUX(0, "mout_isp_sensor", mout_group2_p, SRC_ISP, 28, 3),
787 static struct samsung_div_clock exynos5x_div_clks[] __initdata = {
788 DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
789 DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
790 DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3),
791 DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3),
792 DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3),
794 DIV(0, "dout_aclk400_isp", "mout_aclk400_isp", DIV_TOP0, 0, 3),
795 DIV(0, "dout_aclk400_mscl", "mout_aclk400_mscl", DIV_TOP0, 4, 3),
796 DIV(0, "dout_aclk200", "mout_aclk200", DIV_TOP0, 8, 3),
797 DIV(0, "dout_aclk200_fsys2", "mout_aclk200_fsys2", DIV_TOP0, 12, 3),
798 DIV(0, "dout_aclk100_noc", "mout_aclk100_noc", DIV_TOP0, 20, 3),
799 DIV(0, "dout_pclk200_fsys", "mout_pclk200_fsys", DIV_TOP0, 24, 3),
800 DIV(0, "dout_aclk200_fsys", "mout_aclk200_fsys", DIV_TOP0, 28, 3),
802 DIV(0, "dout_aclk333_432_gscl", "mout_aclk333_432_gscl",
804 DIV(0, "dout_aclk333_432_isp", "mout_aclk333_432_isp",
806 DIV(0, "dout_aclk66", "mout_aclk66", DIV_TOP1, 8, 6),
807 DIV(0, "dout_aclk333_432_isp0", "mout_aclk333_432_isp0",
809 DIV(0, "dout_aclk266", "mout_aclk266", DIV_TOP1, 20, 3),
810 DIV(0, "dout_aclk166", "mout_aclk166", DIV_TOP1, 24, 3),
811 DIV(0, "dout_aclk333", "mout_aclk333", DIV_TOP1, 28, 3),
813 DIV(0, "dout_aclk333_g2d", "mout_aclk333_g2d", DIV_TOP2, 8, 3),
814 DIV(0, "dout_aclk266_g2d", "mout_aclk266_g2d", DIV_TOP2, 12, 3),
815 DIV(0, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 16, 3),
816 DIV(0, "dout_aclk300_jpeg", "mout_aclk300_jpeg", DIV_TOP2, 20, 3),
817 DIV(0, "dout_aclk300_disp1", "mout_aclk300_disp1", DIV_TOP2, 24, 3),
818 DIV(0, "dout_aclk300_gscl", "mout_aclk300_gscl", DIV_TOP2, 28, 3),
821 DIV(0, "dout_fimd1", "mout_fimd1_final", DIV_DISP10, 0, 4),
822 DIV(0, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8),
823 DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4),
824 DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4),
825 DIV(0, "dout_disp1_blk", "aclk200_disp1", DIV2_RATIO0, 16, 2),
826 DIV(0, "dout_aclk400_disp1", "mout_aclk400_disp1", DIV_TOP2, 4, 3),
829 DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
830 DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8),
833 DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4),
834 DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
835 DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4),
836 DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),
839 DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10),
840 DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10),
841 DIV(0, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10),
843 DIV(0, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8),
844 DIV(0, "dout_mphy_refclk", "mout_mphy_refclk", DIV_FSYS2, 16, 8),
847 DIV(0, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4),
848 DIV(0, "dout_uart1", "mout_uart1", DIV_PERIC0, 12, 4),
849 DIV(0, "dout_uart2", "mout_uart2", DIV_PERIC0, 16, 4),
850 DIV(0, "dout_uart3", "mout_uart3", DIV_PERIC0, 20, 4),
851 DIV(0, "dout_pwm", "mout_pwm", DIV_PERIC0, 28, 4),
854 DIV(0, "dout_spi0", "mout_spi0", DIV_PERIC1, 20, 4),
855 DIV(0, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4),
856 DIV(0, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4),
859 DIV(0, "dout_mfc_blk", "mout_user_aclk333", DIV4_RATIO, 0, 2),
862 DIV(0, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8),
863 DIV(0, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8),
866 DIV(0, "dout_i2s1", "dout_audio1", DIV_PERIC3, 6, 6),
867 DIV(0, "dout_i2s2", "dout_audio2", DIV_PERIC3, 12, 6),
868 DIV(0, "dout_audio0", "mout_audio0", DIV_PERIC3, 20, 4),
869 DIV(0, "dout_audio1", "mout_audio1", DIV_PERIC3, 24, 4),
870 DIV(0, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4),
873 DIV(0, "dout_spi0_pre", "dout_spi0", DIV_PERIC4, 8, 8),
874 DIV(0, "dout_spi1_pre", "dout_spi1", DIV_PERIC4, 16, 8),
875 DIV(0, "dout_spi2_pre", "dout_spi2", DIV_PERIC4, 24, 8),
878 DIV(0, "dout_gscl_blk_300", "mout_user_aclk300_gscl",
880 DIV(0, "dout_gscl_blk_333", "aclk333_432_gscl", DIV2_RATIO0, 6, 2),
883 DIV(0, "dout_mscl_blk", "aclk400_mscl", DIV2_RATIO0, 28, 2),
886 DIV(0, "dout_gen_blk", "mout_user_aclk266", DIV2_RATIO0, 8, 1),
887 DIV(0, "dout_jpg_blk", "aclk166", DIV2_RATIO0, 20, 1),
890 DIV(0, "dout_isp_sensor0", "mout_isp_sensor", SCLK_DIV_ISP0, 8, 8),
891 DIV(0, "dout_isp_sensor1", "mout_isp_sensor", SCLK_DIV_ISP0, 16, 8),
892 DIV(0, "dout_isp_sensor2", "mout_isp_sensor", SCLK_DIV_ISP0, 24, 8),
893 DIV(0, "dout_pwm_isp", "mout_pwm_isp", SCLK_DIV_ISP1, 28, 4),
894 DIV(0, "dout_uart_isp", "mout_uart_isp", SCLK_DIV_ISP1, 24, 4),
895 DIV(0, "dout_spi0_isp", "mout_spi0_isp", SCLK_DIV_ISP1, 16, 4),
896 DIV(0, "dout_spi1_isp", "mout_spi1_isp", SCLK_DIV_ISP1, 20, 4),
897 DIV_F(0, "dout_spi0_isp_pre", "dout_spi0_isp", SCLK_DIV_ISP1, 0, 8,
898 CLK_SET_RATE_PARENT, 0),
899 DIV_F(0, "dout_spi1_isp_pre", "dout_spi1_isp", SCLK_DIV_ISP1, 8, 8,
900 CLK_SET_RATE_PARENT, 0),
903 static struct samsung_gate_clock exynos5x_gate_clks[] __initdata = {
905 GATE(CLK_MDMA0, "mdma0", "aclk266_g2d", GATE_IP_G2D, 1, 0, 0),
906 GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0),
907 GATE(CLK_G2D, "g2d", "aclk333_g2d", GATE_IP_G2D, 3, 0, 0),
908 GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "aclk266_g2d", GATE_IP_G2D, 5, 0, 0),
909 GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk333_g2d", GATE_IP_G2D, 7, 0, 0),
911 GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys",
912 GATE_BUS_FSYS0, 9, CLK_IGNORE_UNUSED, 0),
913 GATE(0, "aclk200_fsys2", "mout_user_aclk200_fsys2",
914 GATE_BUS_FSYS0, 10, CLK_IGNORE_UNUSED, 0),
916 GATE(0, "aclk333_g2d", "mout_user_aclk333_g2d",
917 GATE_BUS_TOP, 0, CLK_IGNORE_UNUSED, 0),
918 GATE(0, "aclk266_g2d", "mout_user_aclk266_g2d",
919 GATE_BUS_TOP, 1, CLK_IGNORE_UNUSED, 0),
920 GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg",
921 GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0),
922 GATE(0, "aclk333_432_isp0", "mout_user_aclk333_432_isp0",
923 GATE_BUS_TOP, 5, 0, 0),
924 GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl",
925 GATE_BUS_TOP, 6, CLK_IGNORE_UNUSED, 0),
926 GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl",
927 GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0),
928 GATE(0, "aclk333_432_isp", "mout_user_aclk333_432_isp",
929 GATE_BUS_TOP, 8, 0, 0),
930 GATE(CLK_PCLK66_GPIO, "pclk66_gpio", "mout_user_pclk66_gpio",
931 GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0),
932 GATE(0, "aclk66_psgen", "mout_user_aclk66_psgen",
933 GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0),
934 GATE(0, "aclk266_isp", "mout_user_aclk266_isp",
935 GATE_BUS_TOP, 13, 0, 0),
936 GATE(0, "aclk166", "mout_user_aclk166",
937 GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0),
938 GATE(0, "aclk333", "mout_aclk333",
939 GATE_BUS_TOP, 15, CLK_IGNORE_UNUSED, 0),
940 GATE(0, "aclk400_isp", "mout_user_aclk400_isp",
941 GATE_BUS_TOP, 16, 0, 0),
942 GATE(0, "aclk400_mscl", "mout_user_aclk400_mscl",
943 GATE_BUS_TOP, 17, 0, 0),
944 GATE(0, "aclk200_disp1", "mout_user_aclk200_disp1",
945 GATE_BUS_TOP, 18, 0, 0),
946 GATE(CLK_SCLK_MPHY_IXTAL24, "sclk_mphy_ixtal24", "mphy_refclk_ixtal24",
947 GATE_BUS_TOP, 28, 0, 0),
948 GATE(CLK_SCLK_HSIC_12M, "sclk_hsic_12m", "ff_hsic_12m",
949 GATE_BUS_TOP, 29, 0, 0),
951 GATE(0, "aclk300_disp1", "mout_user_aclk300_disp1",
952 SRC_MASK_TOP2, 24, 0, 0),
954 GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk",
955 SRC_MASK_TOP7, 20, 0, 0),
958 GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0",
959 GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0),
960 GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_uart1",
961 GATE_TOP_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0),
962 GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_uart2",
963 GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0),
964 GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_uart3",
965 GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0),
966 GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_spi0_pre",
967 GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0),
968 GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_spi1_pre",
969 GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
970 GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_spi2_pre",
971 GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
972 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif",
973 GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0),
974 GATE(CLK_SCLK_PWM, "sclk_pwm", "dout_pwm",
975 GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
976 GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_pcm1",
977 GATE_TOP_SCLK_PERIC, 15, CLK_SET_RATE_PARENT, 0),
978 GATE(CLK_SCLK_PCM2, "sclk_pcm2", "dout_pcm2",
979 GATE_TOP_SCLK_PERIC, 16, CLK_SET_RATE_PARENT, 0),
980 GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_i2s1",
981 GATE_TOP_SCLK_PERIC, 17, CLK_SET_RATE_PARENT, 0),
982 GATE(CLK_SCLK_I2S2, "sclk_i2s2", "dout_i2s2",
983 GATE_TOP_SCLK_PERIC, 18, CLK_SET_RATE_PARENT, 0),
985 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_mmc0",
986 GATE_TOP_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
987 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_mmc1",
988 GATE_TOP_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
989 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_mmc2",
990 GATE_TOP_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
991 GATE(CLK_SCLK_USBPHY301, "sclk_usbphy301", "dout_usbphy301",
992 GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0),
993 GATE(CLK_SCLK_USBPHY300, "sclk_usbphy300", "dout_usbphy300",
994 GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
995 GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300",
996 GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
997 GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301",
998 GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0),
1001 GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "dout_fimd1",
1002 GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0),
1003 GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "dout_mipi1",
1004 GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0),
1005 GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi",
1006 GATE_TOP_SCLK_DISP1, 9, 0, 0),
1007 GATE(CLK_SCLK_PIXEL, "sclk_pixel", "dout_hdmi_pixel",
1008 GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0),
1009 GATE(CLK_SCLK_DP1, "sclk_dp1", "dout_dp1",
1010 GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0),
1013 GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0",
1014 GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0),
1015 GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0",
1016 GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0),
1019 GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0),
1020 GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
1021 GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
1022 GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0),
1023 GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0),
1024 GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0),
1025 GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_IP_FSYS, 13, 0, 0),
1026 GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0),
1027 GATE(CLK_SROMC, "sromc", "aclk200_fsys2",
1028 GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0),
1029 GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
1030 GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0),
1031 GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0),
1032 GATE(CLK_SCLK_UNIPRO, "sclk_unipro", "dout_unipro",
1033 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
1036 GATE(CLK_UART0, "uart0", "mout_user_aclk66_peric",
1037 GATE_IP_PERIC, 0, 0, 0),
1038 GATE(CLK_UART1, "uart1", "mout_user_aclk66_peric",
1039 GATE_IP_PERIC, 1, 0, 0),
1040 GATE(CLK_UART2, "uart2", "mout_user_aclk66_peric",
1041 GATE_IP_PERIC, 2, 0, 0),
1042 GATE(CLK_UART3, "uart3", "mout_user_aclk66_peric",
1043 GATE_IP_PERIC, 3, 0, 0),
1044 GATE(CLK_I2C0, "i2c0", "mout_user_aclk66_peric",
1045 GATE_IP_PERIC, 6, 0, 0),
1046 GATE(CLK_I2C1, "i2c1", "mout_user_aclk66_peric",
1047 GATE_IP_PERIC, 7, 0, 0),
1048 GATE(CLK_I2C2, "i2c2", "mout_user_aclk66_peric",
1049 GATE_IP_PERIC, 8, 0, 0),
1050 GATE(CLK_I2C3, "i2c3", "mout_user_aclk66_peric",
1051 GATE_IP_PERIC, 9, 0, 0),
1052 GATE(CLK_USI0, "usi0", "mout_user_aclk66_peric",
1053 GATE_IP_PERIC, 10, 0, 0),
1054 GATE(CLK_USI1, "usi1", "mout_user_aclk66_peric",
1055 GATE_IP_PERIC, 11, 0, 0),
1056 GATE(CLK_USI2, "usi2", "mout_user_aclk66_peric",
1057 GATE_IP_PERIC, 12, 0, 0),
1058 GATE(CLK_USI3, "usi3", "mout_user_aclk66_peric",
1059 GATE_IP_PERIC, 13, 0, 0),
1060 GATE(CLK_I2C_HDMI, "i2c_hdmi", "mout_user_aclk66_peric",
1061 GATE_IP_PERIC, 14, 0, 0),
1062 GATE(CLK_TSADC, "tsadc", "mout_user_aclk66_peric",
1063 GATE_IP_PERIC, 15, 0, 0),
1064 GATE(CLK_SPI0, "spi0", "mout_user_aclk66_peric",
1065 GATE_IP_PERIC, 16, 0, 0),
1066 GATE(CLK_SPI1, "spi1", "mout_user_aclk66_peric",
1067 GATE_IP_PERIC, 17, 0, 0),
1068 GATE(CLK_SPI2, "spi2", "mout_user_aclk66_peric",
1069 GATE_IP_PERIC, 18, 0, 0),
1070 GATE(CLK_I2S1, "i2s1", "mout_user_aclk66_peric",
1071 GATE_IP_PERIC, 20, 0, 0),
1072 GATE(CLK_I2S2, "i2s2", "mout_user_aclk66_peric",
1073 GATE_IP_PERIC, 21, 0, 0),
1074 GATE(CLK_PCM1, "pcm1", "mout_user_aclk66_peric",
1075 GATE_IP_PERIC, 22, 0, 0),
1076 GATE(CLK_PCM2, "pcm2", "mout_user_aclk66_peric",
1077 GATE_IP_PERIC, 23, 0, 0),
1078 GATE(CLK_PWM, "pwm", "mout_user_aclk66_peric",
1079 GATE_IP_PERIC, 24, 0, 0),
1080 GATE(CLK_SPDIF, "spdif", "mout_user_aclk66_peric",
1081 GATE_IP_PERIC, 26, 0, 0),
1082 GATE(CLK_USI4, "usi4", "mout_user_aclk66_peric",
1083 GATE_IP_PERIC, 28, 0, 0),
1084 GATE(CLK_USI5, "usi5", "mout_user_aclk66_peric",
1085 GATE_IP_PERIC, 30, 0, 0),
1086 GATE(CLK_USI6, "usi6", "mout_user_aclk66_peric",
1087 GATE_IP_PERIC, 31, 0, 0),
1089 GATE(CLK_KEYIF, "keyif", "mout_user_aclk66_peric",
1090 GATE_BUS_PERIC, 22, 0, 0),
1093 GATE(CLK_CHIPID, "chipid", "aclk66_psgen",
1094 GATE_IP_PERIS, 0, CLK_IGNORE_UNUSED, 0),
1095 GATE(CLK_SYSREG, "sysreg", "aclk66_psgen",
1096 GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0),
1097 GATE(CLK_TZPC0, "tzpc0", "aclk66_psgen", GATE_IP_PERIS, 6, 0, 0),
1098 GATE(CLK_TZPC1, "tzpc1", "aclk66_psgen", GATE_IP_PERIS, 7, 0, 0),
1099 GATE(CLK_TZPC2, "tzpc2", "aclk66_psgen", GATE_IP_PERIS, 8, 0, 0),
1100 GATE(CLK_TZPC3, "tzpc3", "aclk66_psgen", GATE_IP_PERIS, 9, 0, 0),
1101 GATE(CLK_TZPC4, "tzpc4", "aclk66_psgen", GATE_IP_PERIS, 10, 0, 0),
1102 GATE(CLK_TZPC5, "tzpc5", "aclk66_psgen", GATE_IP_PERIS, 11, 0, 0),
1103 GATE(CLK_TZPC6, "tzpc6", "aclk66_psgen", GATE_IP_PERIS, 12, 0, 0),
1104 GATE(CLK_TZPC7, "tzpc7", "aclk66_psgen", GATE_IP_PERIS, 13, 0, 0),
1105 GATE(CLK_TZPC8, "tzpc8", "aclk66_psgen", GATE_IP_PERIS, 14, 0, 0),
1106 GATE(CLK_TZPC9, "tzpc9", "aclk66_psgen", GATE_IP_PERIS, 15, 0, 0),
1107 GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk66_psgen", GATE_IP_PERIS, 16, 0, 0),
1108 GATE(CLK_MCT, "mct", "aclk66_psgen", GATE_IP_PERIS, 18, 0, 0),
1109 GATE(CLK_WDT, "wdt", "aclk66_psgen", GATE_IP_PERIS, 19, 0, 0),
1110 GATE(CLK_RTC, "rtc", "aclk66_psgen", GATE_IP_PERIS, 20, 0, 0),
1111 GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_IP_PERIS, 21, 0, 0),
1112 GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_IP_PERIS, 22, 0, 0),
1114 GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0),
1117 GATE(CLK_ROTATOR, "rotator", "mout_user_aclk266", GATE_IP_GEN, 1, 0, 0),
1118 GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0),
1119 GATE(CLK_JPEG2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0),
1120 GATE(CLK_MDMA1, "mdma1", "mout_user_aclk266", GATE_IP_GEN, 4, 0, 0),
1121 GATE(CLK_TOP_RTC, "top_rtc", "aclk66_psgen", GATE_IP_GEN, 5, 0, 0),
1122 GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "dout_gen_blk",
1123 GATE_IP_GEN, 6, 0, 0),
1124 GATE(CLK_SMMU_JPEG, "smmu_jpeg", "dout_jpg_blk", GATE_IP_GEN, 7, 0, 0),
1125 GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "dout_gen_blk",
1126 GATE_IP_GEN, 9, 0, 0),
1128 /* GATE_IP_GEN doesn't list gates for smmu_jpeg2 and mc */
1129 GATE(CLK_SMMU_JPEG2, "smmu_jpeg2", "dout_jpg_blk",
1130 GATE_BUS_GEN, 28, 0, 0),
1131 GATE(CLK_MC, "mc", "aclk66_psgen", GATE_BUS_GEN, 12, 0, 0),
1134 GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "mout_user_aclk333_432_gscl",
1135 GATE_TOP_SCLK_GSCL, 6, 0, 0),
1136 GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "mout_user_aclk333_432_gscl",
1137 GATE_TOP_SCLK_GSCL, 7, 0, 0),
1139 GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0),
1140 GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0),
1141 GATE(CLK_FIMC_3AA, "fimc_3aa", "aclk333_432_gscl",
1142 GATE_IP_GSCL0, 4, 0, 0),
1143 GATE(CLK_FIMC_LITE0, "fimc_lite0", "aclk333_432_gscl",
1144 GATE_IP_GSCL0, 5, 0, 0),
1145 GATE(CLK_FIMC_LITE1, "fimc_lite1", "aclk333_432_gscl",
1146 GATE_IP_GSCL0, 6, 0, 0),
1148 GATE(CLK_SMMU_3AA, "smmu_3aa", "dout_gscl_blk_333",
1149 GATE_IP_GSCL1, 2, 0, 0),
1150 GATE(CLK_SMMU_FIMCL0, "smmu_fimcl0", "dout_gscl_blk_333",
1151 GATE_IP_GSCL1, 3, 0, 0),
1152 GATE(CLK_SMMU_FIMCL1, "smmu_fimcl1", "dout_gscl_blk_333",
1153 GATE_IP_GSCL1, 4, 0, 0),
1154 GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "dout_gscl_blk_300",
1155 GATE_IP_GSCL1, 6, 0, 0),
1156 GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "dout_gscl_blk_300",
1157 GATE_IP_GSCL1, 7, 0, 0),
1158 GATE(CLK_GSCL_WA, "gscl_wa", "sclk_gscl_wa", GATE_IP_GSCL1, 12, 0, 0),
1159 GATE(CLK_GSCL_WB, "gscl_wb", "sclk_gscl_wb", GATE_IP_GSCL1, 13, 0, 0),
1160 GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3,", "dout_gscl_blk_333",
1161 GATE_IP_GSCL1, 16, 0, 0),
1162 GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl",
1163 GATE_IP_GSCL1, 17, 0, 0),
1166 GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0),
1167 GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0),
1168 GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0),
1169 GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "dout_mscl_blk",
1170 GATE_IP_MSCL, 8, 0, 0),
1171 GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "dout_mscl_blk",
1172 GATE_IP_MSCL, 9, 0, 0),
1173 GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "dout_mscl_blk",
1174 GATE_IP_MSCL, 10, 0, 0),
1176 GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0),
1177 GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0),
1178 GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0),
1179 GATE(CLK_MIXER, "mixer", "aclk200_disp1", GATE_IP_DISP1, 5, 0, 0),
1180 GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0),
1181 GATE(CLK_SMMU_FIMD1M0, "smmu_fimd1m0", "dout_disp1_blk",
1182 GATE_IP_DISP1, 7, 0, 0),
1183 GATE(CLK_SMMU_FIMD1M1, "smmu_fimd1m1", "dout_disp1_blk",
1184 GATE_IP_DISP1, 8, 0, 0),
1185 GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1",
1186 GATE_IP_DISP1, 9, 0, 0),
1189 GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "dout_uart_isp",
1190 GATE_TOP_SCLK_ISP, 0, CLK_SET_RATE_PARENT, 0),
1191 GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "dout_spi0_isp_pre",
1192 GATE_TOP_SCLK_ISP, 1, CLK_SET_RATE_PARENT, 0),
1193 GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "dout_spi1_isp_pre",
1194 GATE_TOP_SCLK_ISP, 2, CLK_SET_RATE_PARENT, 0),
1195 GATE(CLK_SCLK_PWM_ISP, "sclk_pwm_isp", "dout_pwm_isp",
1196 GATE_TOP_SCLK_ISP, 3, CLK_SET_RATE_PARENT, 0),
1197 GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "dout_isp_sensor0",
1198 GATE_TOP_SCLK_ISP, 4, CLK_SET_RATE_PARENT, 0),
1199 GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "dout_isp_sensor1",
1200 GATE_TOP_SCLK_ISP, 8, CLK_SET_RATE_PARENT, 0),
1201 GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "dout_isp_sensor2",
1202 GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0),
1204 GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0),
1205 GATE(CLK_SMMU_MFCL, "smmu_mfcl", "dout_mfc_blk", GATE_IP_MFC, 1, 0, 0),
1206 GATE(CLK_SMMU_MFCR, "smmu_mfcr", "dout_mfc_blk", GATE_IP_MFC, 2, 0, 0),
1208 GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0),
1211 static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] = {
1212 PLL_35XX_RATE(2000000000, 250, 3, 0),
1213 PLL_35XX_RATE(1900000000, 475, 6, 0),
1214 PLL_35XX_RATE(1800000000, 225, 3, 0),
1215 PLL_35XX_RATE(1700000000, 425, 6, 0),
1216 PLL_35XX_RATE(1600000000, 200, 3, 0),
1217 PLL_35XX_RATE(1500000000, 250, 4, 0),
1218 PLL_35XX_RATE(1400000000, 175, 3, 0),
1219 PLL_35XX_RATE(1300000000, 325, 6, 0),
1220 PLL_35XX_RATE(1200000000, 200, 2, 1),
1221 PLL_35XX_RATE(1100000000, 275, 3, 1),
1222 PLL_35XX_RATE(1000000000, 250, 3, 1),
1223 PLL_35XX_RATE(900000000, 150, 2, 1),
1224 PLL_35XX_RATE(800000000, 200, 3, 1),
1225 PLL_35XX_RATE(700000000, 175, 3, 1),
1226 PLL_35XX_RATE(600000000, 200, 2, 2),
1227 PLL_35XX_RATE(500000000, 250, 3, 2),
1228 PLL_35XX_RATE(400000000, 200, 3, 2),
1229 PLL_35XX_RATE(300000000, 200, 2, 3),
1230 PLL_35XX_RATE(200000000, 200, 3, 3),
1233 static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = {
1234 [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
1236 [cpll] = PLL(pll_2550, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
1238 [dpll] = PLL(pll_2550, CLK_FOUT_DPLL, "fout_dpll", "fin_pll", DPLL_LOCK,
1240 [epll] = PLL(pll_2650, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK,
1242 [rpll] = PLL(pll_2650, CLK_FOUT_RPLL, "fout_rpll", "fin_pll", RPLL_LOCK,
1244 [ipll] = PLL(pll_2550, CLK_FOUT_IPLL, "fout_ipll", "fin_pll", IPLL_LOCK,
1246 [spll] = PLL(pll_2550, CLK_FOUT_SPLL, "fout_spll", "fin_pll", SPLL_LOCK,
1248 [vpll] = PLL(pll_2550, CLK_FOUT_VPLL, "fout_vpll", "fin_pll", VPLL_LOCK,
1250 [mpll] = PLL(pll_2550, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
1252 [bpll] = PLL(pll_2550, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
1254 [kpll] = PLL(pll_2550, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK,
1258 static const struct of_device_id ext_clk_match[] __initconst = {
1259 { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, },
1263 /* register exynos5420 clocks */
1264 static void __init exynos5x_clk_init(struct device_node *np,
1265 enum exynos5x_soc soc)
1267 struct samsung_clk_provider *ctx;
1270 reg_base = of_iomap(np, 0);
1272 panic("%s: failed to map registers\n", __func__);
1274 panic("%s: unable to determine soc\n", __func__);
1279 ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
1281 panic("%s: unable to allocate context.\n", __func__);
1283 samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks,
1284 ARRAY_SIZE(exynos5x_fixed_rate_ext_clks),
1287 if (_get_rate("fin_pll") == 24 * MHZ) {
1288 exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl;
1289 exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
1292 samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls),
1294 samsung_clk_register_fixed_rate(ctx, exynos5x_fixed_rate_clks,
1295 ARRAY_SIZE(exynos5x_fixed_rate_clks));
1296 samsung_clk_register_fixed_factor(ctx, exynos5x_fixed_factor_clks,
1297 ARRAY_SIZE(exynos5x_fixed_factor_clks));
1298 samsung_clk_register_mux(ctx, exynos5x_mux_clks,
1299 ARRAY_SIZE(exynos5x_mux_clks));
1300 samsung_clk_register_div(ctx, exynos5x_div_clks,
1301 ARRAY_SIZE(exynos5x_div_clks));
1302 samsung_clk_register_gate(ctx, exynos5x_gate_clks,
1303 ARRAY_SIZE(exynos5x_gate_clks));
1305 if (soc == EXYNOS5420) {
1306 samsung_clk_register_mux(ctx, exynos5420_mux_clks,
1307 ARRAY_SIZE(exynos5420_mux_clks));
1308 samsung_clk_register_div(ctx, exynos5420_div_clks,
1309 ARRAY_SIZE(exynos5420_div_clks));
1311 samsung_clk_register_fixed_factor(
1312 ctx, exynos5800_fixed_factor_clks,
1313 ARRAY_SIZE(exynos5800_fixed_factor_clks));
1314 samsung_clk_register_mux(ctx, exynos5800_mux_clks,
1315 ARRAY_SIZE(exynos5800_mux_clks));
1316 samsung_clk_register_div(ctx, exynos5800_div_clks,
1317 ARRAY_SIZE(exynos5800_div_clks));
1318 samsung_clk_register_gate(ctx, exynos5800_gate_clks,
1319 ARRAY_SIZE(exynos5800_gate_clks));
1322 exynos5420_clk_sleep_init();
1324 samsung_clk_of_add_provider(np, ctx);
1327 static void __init exynos5420_clk_init(struct device_node *np)
1329 exynos5x_clk_init(np, EXYNOS5420);
1331 CLK_OF_DECLARE(exynos5420_clk, "samsung,exynos5420-clock", exynos5420_clk_init);
1333 static void __init exynos5800_clk_init(struct device_node *np)
1335 exynos5x_clk_init(np, EXYNOS5800);
1337 CLK_OF_DECLARE(exynos5800_clk, "samsung,exynos5800-clock", exynos5800_clk_init);