1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
4 * Author: Tomasz Figa <t.figa@samsung.com>
6 * Clock driver for Exynos clock output
9 #include <linux/slab.h>
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
14 #include <linux/of_address.h>
15 #include <linux/syscore_ops.h>
17 #define EXYNOS_CLKOUT_NR_CLKS 1
18 #define EXYNOS_CLKOUT_PARENTS 32
20 #define EXYNOS_PMU_DEBUG_REG 0xa00
21 #define EXYNOS_CLKOUT_DISABLE_SHIFT 0
22 #define EXYNOS_CLKOUT_MUX_SHIFT 8
23 #define EXYNOS4_CLKOUT_MUX_MASK 0xf
24 #define EXYNOS5_CLKOUT_MUX_MASK 0x1f
26 struct exynos_clkout {
32 struct clk_hw_onecell_data data;
35 static struct exynos_clkout *clkout;
37 static int exynos_clkout_suspend(void)
39 clkout->pmu_debug_save = readl(clkout->reg + EXYNOS_PMU_DEBUG_REG);
44 static void exynos_clkout_resume(void)
46 writel(clkout->pmu_debug_save, clkout->reg + EXYNOS_PMU_DEBUG_REG);
49 static struct syscore_ops exynos_clkout_syscore_ops = {
50 .suspend = exynos_clkout_suspend,
51 .resume = exynos_clkout_resume,
54 static void __init exynos_clkout_init(struct device_node *node, u32 mux_mask)
56 const char *parent_names[EXYNOS_CLKOUT_PARENTS];
57 struct clk *parents[EXYNOS_CLKOUT_PARENTS];
62 clkout = kzalloc(struct_size(clkout, data.hws, EXYNOS_CLKOUT_NR_CLKS),
67 spin_lock_init(&clkout->slock);
70 for (i = 0; i < EXYNOS_CLKOUT_PARENTS; ++i) {
71 char name[] = "clkoutXX";
73 snprintf(name, sizeof(name), "clkout%d", i);
74 parents[i] = of_clk_get_by_name(node, name);
75 if (IS_ERR(parents[i])) {
76 parent_names[i] = "none";
80 parent_names[i] = __clk_get_name(parents[i]);
87 clkout->reg = of_iomap(node, 0);
91 clkout->gate.reg = clkout->reg + EXYNOS_PMU_DEBUG_REG;
92 clkout->gate.bit_idx = EXYNOS_CLKOUT_DISABLE_SHIFT;
93 clkout->gate.flags = CLK_GATE_SET_TO_DISABLE;
94 clkout->gate.lock = &clkout->slock;
96 clkout->mux.reg = clkout->reg + EXYNOS_PMU_DEBUG_REG;
97 clkout->mux.mask = mux_mask;
98 clkout->mux.shift = EXYNOS_CLKOUT_MUX_SHIFT;
99 clkout->mux.lock = &clkout->slock;
101 clkout->data.hws[0] = clk_hw_register_composite(NULL, "clkout",
102 parent_names, parent_count, &clkout->mux.hw,
103 &clk_mux_ops, NULL, NULL, &clkout->gate.hw,
104 &clk_gate_ops, CLK_SET_RATE_PARENT
105 | CLK_SET_RATE_NO_REPARENT);
106 if (IS_ERR(clkout->data.hws[0]))
109 clkout->data.num = EXYNOS_CLKOUT_NR_CLKS;
110 ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, &clkout->data);
114 register_syscore_ops(&exynos_clkout_syscore_ops);
119 clk_hw_unregister(clkout->data.hws[0]);
121 iounmap(clkout->reg);
123 for (i = 0; i < EXYNOS_CLKOUT_PARENTS; ++i)
124 if (!IS_ERR(parents[i]))
129 pr_err("%s: failed to register clkout clock\n", __func__);
133 * We use CLK_OF_DECLARE_DRIVER initialization method to avoid setting
134 * the OF_POPULATED flag on the pmu device tree node, so later the
135 * Exynos PMU platform device can be properly probed with PMU driver.
138 static void __init exynos4_clkout_init(struct device_node *node)
140 exynos_clkout_init(node, EXYNOS4_CLKOUT_MUX_MASK);
142 CLK_OF_DECLARE_DRIVER(exynos4210_clkout, "samsung,exynos4210-pmu",
143 exynos4_clkout_init);
144 CLK_OF_DECLARE_DRIVER(exynos4412_clkout, "samsung,exynos4412-pmu",
145 exynos4_clkout_init);
146 CLK_OF_DECLARE_DRIVER(exynos3250_clkout, "samsung,exynos3250-pmu",
147 exynos4_clkout_init);
149 static void __init exynos5_clkout_init(struct device_node *node)
151 exynos_clkout_init(node, EXYNOS5_CLKOUT_MUX_MASK);
153 CLK_OF_DECLARE_DRIVER(exynos5250_clkout, "samsung,exynos5250-pmu",
154 exynos5_clkout_init);
155 CLK_OF_DECLARE_DRIVER(exynos5410_clkout, "samsung,exynos5410-pmu",
156 exynos5_clkout_init);
157 CLK_OF_DECLARE_DRIVER(exynos5420_clkout, "samsung,exynos5420-pmu",
158 exynos5_clkout_init);
159 CLK_OF_DECLARE_DRIVER(exynos5433_clkout, "samsung,exynos5433-pmu",
160 exynos5_clkout_init);