drivers/clk/rockchip/clk-rk3288.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright (c) 2014 MundoReader S.L.
   4  * Author: Heiko Stuebner <heiko@sntech.de>
   5  */
   6
   7 #include <linux/clk-provider.h>
   8 #include <linux/io.h>
   9 #include <linux/of.h>
  10 #include <linux/of_address.h>
  11 #include <linux/syscore_ops.h>
  12 #include <dt-bindings/clock/rk3288-cru.h>
  13 #include "clk.h"
  14
  15 #define RK3288_GRF_SOC_CON(x)   (0x244 + x * 4)
  16 #define RK3288_GRF_SOC_STATUS1  0x284
  17
  18 enum rk3288_variant {
  19         RK3288_CRU,
  20         RK3288W_CRU,
  21 };
  22
  23 enum rk3288_plls {
  24         apll, dpll, cpll, gpll, npll,
  25 };
  26
  27 static struct rockchip_pll_rate_table rk3288_pll_rates[] = {
  28         RK3066_PLL_RATE(2208000000, 1, 92, 1),
  29         RK3066_PLL_RATE(2184000000, 1, 91, 1),
  30         RK3066_PLL_RATE(2160000000, 1, 90, 1),
  31         RK3066_PLL_RATE(2136000000, 1, 89, 1),
  32         RK3066_PLL_RATE(2112000000, 1, 88, 1),
  33         RK3066_PLL_RATE(2088000000, 1, 87, 1),
  34         RK3066_PLL_RATE(2064000000, 1, 86, 1),
  35         RK3066_PLL_RATE(2040000000, 1, 85, 1),
  36         RK3066_PLL_RATE(2016000000, 1, 84, 1),
  37         RK3066_PLL_RATE(1992000000, 1, 83, 1),
  38         RK3066_PLL_RATE(1968000000, 1, 82, 1),
  39         RK3066_PLL_RATE(1944000000, 1, 81, 1),
  40         RK3066_PLL_RATE(1920000000, 1, 80, 1),
  41         RK3066_PLL_RATE(1896000000, 1, 79, 1),
  42         RK3066_PLL_RATE(1872000000, 1, 78, 1),
  43         RK3066_PLL_RATE(1848000000, 1, 77, 1),
  44         RK3066_PLL_RATE(1824000000, 1, 76, 1),
  45         RK3066_PLL_RATE(1800000000, 1, 75, 1),
  46         RK3066_PLL_RATE(1776000000, 1, 74, 1),
  47         RK3066_PLL_RATE(1752000000, 1, 73, 1),
  48         RK3066_PLL_RATE(1728000000, 1, 72, 1),
  49         RK3066_PLL_RATE(1704000000, 1, 71, 1),
  50         RK3066_PLL_RATE(1680000000, 1, 70, 1),
  51         RK3066_PLL_RATE(1656000000, 1, 69, 1),
  52         RK3066_PLL_RATE(1632000000, 1, 68, 1),
  53         RK3066_PLL_RATE(1608000000, 1, 67, 1),
  54         RK3066_PLL_RATE(1560000000, 1, 65, 1),
  55         RK3066_PLL_RATE(1512000000, 1, 63, 1),
  56         RK3066_PLL_RATE(1488000000, 1, 62, 1),
  57         RK3066_PLL_RATE(1464000000, 1, 61, 1),
  58         RK3066_PLL_RATE(1440000000, 1, 60, 1),
  59         RK3066_PLL_RATE(1416000000, 1, 59, 1),
  60         RK3066_PLL_RATE(1392000000, 1, 58, 1),
  61         RK3066_PLL_RATE(1368000000, 1, 57, 1),
  62         RK3066_PLL_RATE(1344000000, 1, 56, 1),
  63         RK3066_PLL_RATE(1320000000, 1, 55, 1),
  64         RK3066_PLL_RATE(1296000000, 1, 54, 1),
  65         RK3066_PLL_RATE(1272000000, 1, 53, 1),
  66         RK3066_PLL_RATE(1248000000, 1, 52, 1),
  67         RK3066_PLL_RATE(1224000000, 1, 51, 1),
  68         RK3066_PLL_RATE(1200000000, 1, 50, 1),
  69         RK3066_PLL_RATE(1188000000, 2, 99, 1),
  70         RK3066_PLL_RATE(1176000000, 1, 49, 1),
  71         RK3066_PLL_RATE(1128000000, 1, 47, 1),
  72         RK3066_PLL_RATE(1104000000, 1, 46, 1),
  73         RK3066_PLL_RATE(1008000000, 1, 84, 2),
  74         RK3066_PLL_RATE( 912000000, 1, 76, 2),
  75         RK3066_PLL_RATE( 891000000, 8, 594, 2),
  76         RK3066_PLL_RATE( 888000000, 1, 74, 2),
  77         RK3066_PLL_RATE( 816000000, 1, 68, 2),
  78         RK3066_PLL_RATE( 798000000, 2, 133, 2),
  79         RK3066_PLL_RATE( 792000000, 1, 66, 2),
  80         RK3066_PLL_RATE( 768000000, 1, 64, 2),
  81         RK3066_PLL_RATE( 742500000, 8, 495, 2),
  82         RK3066_PLL_RATE( 696000000, 1, 58, 2),
  83         RK3066_PLL_RATE_NB(621000000, 1, 207, 8, 1),
  84         RK3066_PLL_RATE( 600000000, 1, 50, 2),
  85         RK3066_PLL_RATE_NB(594000000, 1, 198, 8, 1),
  86         RK3066_PLL_RATE( 552000000, 1, 46, 2),
  87         RK3066_PLL_RATE( 504000000, 1, 84, 4),
  88         RK3066_PLL_RATE( 500000000, 3, 125, 2),
  89         RK3066_PLL_RATE( 456000000, 1, 76, 4),
  90         RK3066_PLL_RATE( 428000000, 1, 107, 6),
  91         RK3066_PLL_RATE( 408000000, 1, 68, 4),
  92         RK3066_PLL_RATE( 400000000, 3, 100, 2),
  93         RK3066_PLL_RATE_NB( 394000000, 1, 197, 12, 1),
  94         RK3066_PLL_RATE( 384000000, 2, 128, 4),
  95         RK3066_PLL_RATE( 360000000, 1, 60, 4),
  96         RK3066_PLL_RATE_NB( 356000000, 1, 178, 12, 1),
  97         RK3066_PLL_RATE_NB( 324000000, 1, 189, 14, 1),
  98         RK3066_PLL_RATE( 312000000, 1, 52, 4),
  99         RK3066_PLL_RATE_NB( 308000000, 1, 154, 12, 1),
 100         RK3066_PLL_RATE_NB( 303000000, 1, 202, 16, 1),
 101         RK3066_PLL_RATE( 300000000, 1, 75, 6),
 102         RK3066_PLL_RATE_NB( 297750000, 2, 397, 16, 1),
 103         RK3066_PLL_RATE_NB( 293250000, 2, 391, 16, 1),
 104         RK3066_PLL_RATE_NB( 292500000, 1, 195, 16, 1),
 105         RK3066_PLL_RATE( 273600000, 1, 114, 10),
 106         RK3066_PLL_RATE_NB( 273000000, 1, 182, 16, 1),
 107         RK3066_PLL_RATE_NB( 270000000, 1, 180, 16, 1),
 108         RK3066_PLL_RATE_NB( 266250000, 2, 355, 16, 1),
 109         RK3066_PLL_RATE_NB( 256500000, 1, 171, 16, 1),
 110         RK3066_PLL_RATE( 252000000, 1, 84, 8),
 111         RK3066_PLL_RATE_NB( 250500000, 1, 167, 16, 1),
 112         RK3066_PLL_RATE_NB( 243428571, 1, 142, 14, 1),
 113         RK3066_PLL_RATE( 238000000, 1, 119, 12),
 114         RK3066_PLL_RATE_NB( 219750000, 2, 293, 16, 1),
 115         RK3066_PLL_RATE_NB( 216000000, 1, 144, 16, 1),
 116         RK3066_PLL_RATE_NB( 213000000, 1, 142, 16, 1),
 117         RK3066_PLL_RATE( 195428571, 1, 114, 14),
 118         RK3066_PLL_RATE( 160000000, 1, 80, 12),
 119         RK3066_PLL_RATE( 157500000, 1, 105, 16),
 120         RK3066_PLL_RATE( 126000000, 1, 84, 16),
 121         { /* sentinel */ },
 122 };
 123
 124 #define RK3288_DIV_ACLK_CORE_M0_MASK    0xf
 125 #define RK3288_DIV_ACLK_CORE_M0_SHIFT   0
 126 #define RK3288_DIV_ACLK_CORE_MP_MASK    0xf
 127 #define RK3288_DIV_ACLK_CORE_MP_SHIFT   4
 128 #define RK3288_DIV_L2RAM_MASK           0x7
 129 #define RK3288_DIV_L2RAM_SHIFT          0
 130 #define RK3288_DIV_ATCLK_MASK           0x1f
 131 #define RK3288_DIV_ATCLK_SHIFT          4
 132 #define RK3288_DIV_PCLK_DBGPRE_MASK     0x1f
 133 #define RK3288_DIV_PCLK_DBGPRE_SHIFT    9
 134
 135 #define RK3288_CLKSEL0(_core_m0, _core_mp)                              \
 136         {                                                               \
 137                 .reg = RK3288_CLKSEL_CON(0),                            \
 138                 .val = HIWORD_UPDATE(_core_m0, RK3288_DIV_ACLK_CORE_M0_MASK, \
 139                                 RK3288_DIV_ACLK_CORE_M0_SHIFT) |        \
 140                        HIWORD_UPDATE(_core_mp, RK3288_DIV_ACLK_CORE_MP_MASK, \
 141                                 RK3288_DIV_ACLK_CORE_MP_SHIFT),         \
 142         }
 143 #define RK3288_CLKSEL37(_l2ram, _atclk, _pclk_dbg_pre)                  \
 144         {                                                               \
 145                 .reg = RK3288_CLKSEL_CON(37),                           \
 146                 .val = HIWORD_UPDATE(_l2ram, RK3288_DIV_L2RAM_MASK,     \
 147                                 RK3288_DIV_L2RAM_SHIFT) |               \
 148                        HIWORD_UPDATE(_atclk, RK3288_DIV_ATCLK_MASK,     \
 149                                 RK3288_DIV_ATCLK_SHIFT) |               \
 150                        HIWORD_UPDATE(_pclk_dbg_pre,                     \
 151                                 RK3288_DIV_PCLK_DBGPRE_MASK,            \
 152                                 RK3288_DIV_PCLK_DBGPRE_SHIFT),          \
 153         }
 154
 155 #define RK3288_CPUCLK_RATE(_prate, _core_m0, _core_mp, _l2ram, _atclk, _pdbg) \
 156         {                                                               \
 157                 .prate = _prate,                                        \
 158                 .divs = {                                               \
 159                         RK3288_CLKSEL0(_core_m0, _core_mp),             \
 160                         RK3288_CLKSEL37(_l2ram, _atclk, _pdbg),         \
 161                 },                                                      \
 162         }
 163
 164 static struct rockchip_cpuclk_rate_table rk3288_cpuclk_rates[] __initdata = {
 165         RK3288_CPUCLK_RATE(1800000000, 1, 3, 1, 3, 3),
 166         RK3288_CPUCLK_RATE(1704000000, 1, 3, 1, 3, 3),
 167         RK3288_CPUCLK_RATE(1608000000, 1, 3, 1, 3, 3),
 168         RK3288_CPUCLK_RATE(1512000000, 1, 3, 1, 3, 3),
 169         RK3288_CPUCLK_RATE(1416000000, 1, 3, 1, 3, 3),
 170         RK3288_CPUCLK_RATE(1200000000, 1, 3, 1, 3, 3),
 171         RK3288_CPUCLK_RATE(1008000000, 1, 3, 1, 3, 3),
 172         RK3288_CPUCLK_RATE( 816000000, 1, 3, 1, 3, 3),
 173         RK3288_CPUCLK_RATE( 696000000, 1, 3, 1, 3, 3),
 174         RK3288_CPUCLK_RATE( 600000000, 1, 3, 1, 3, 3),
 175         RK3288_CPUCLK_RATE( 408000000, 1, 3, 1, 3, 3),
 176         RK3288_CPUCLK_RATE( 312000000, 1, 3, 1, 3, 3),
 177         RK3288_CPUCLK_RATE( 216000000, 1, 3, 1, 3, 3),
 178         RK3288_CPUCLK_RATE( 126000000, 1, 3, 1, 3, 3),
 179 };
 180
 181 static const struct rockchip_cpuclk_reg_data rk3288_cpuclk_data = {
 182         .core_reg = RK3288_CLKSEL_CON(0),
 183         .div_core_shift = 8,
 184         .div_core_mask = 0x1f,
 185         .mux_core_alt = 1,
 186         .mux_core_main = 0,
 187         .mux_core_shift = 15,
 188         .mux_core_mask = 0x1,
 189 };
 190
 191 PNAME(mux_pll_p)                = { "xin24m", "xin32k" };
 192 PNAME(mux_armclk_p)             = { "apll_core", "gpll_core" };
 193 PNAME(mux_ddrphy_p)             = { "dpll_ddr", "gpll_ddr" };
 194 PNAME(mux_aclk_cpu_src_p)       = { "cpll_aclk_cpu", "gpll_aclk_cpu" };
 195
 196 PNAME(mux_pll_src_cpll_gpll_p)          = { "cpll", "gpll" };
 197 PNAME(mux_pll_src_npll_cpll_gpll_p)     = { "npll", "cpll", "gpll" };
 198 PNAME(mux_pll_src_cpll_gpll_npll_p)     = { "cpll", "gpll", "npll" };
 199 PNAME(mux_pll_src_cpll_gpll_usb480m_p)  = { "cpll", "gpll", "unstable:usbphy480m_src" };
 200 PNAME(mux_pll_src_cpll_gll_usb_npll_p)  = { "cpll", "gpll", "unstable:usbphy480m_src", "npll" };
 201
 202 PNAME(mux_mmc_src_p)    = { "cpll", "gpll", "xin24m", "xin24m" };
 203 PNAME(mux_i2s_pre_p)    = { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" };
 204 PNAME(mux_i2s_clkout_p) = { "i2s_pre", "xin12m" };
 205 PNAME(mux_spdif_p)      = { "spdif_pre", "spdif_frac", "xin12m" };
 206 PNAME(mux_spdif_8ch_p)  = { "spdif_8ch_pre", "spdif_8ch_frac", "xin12m" };
 207 PNAME(mux_uart0_p)      = { "uart0_src", "uart0_frac", "xin24m" };
 208 PNAME(mux_uart1_p)      = { "uart1_src", "uart1_frac", "xin24m" };
 209 PNAME(mux_uart2_p)      = { "uart2_src", "uart2_frac", "xin24m" };
 210 PNAME(mux_uart3_p)      = { "uart3_src", "uart3_frac", "xin24m" };
 211 PNAME(mux_uart4_p)      = { "uart4_src", "uart4_frac", "xin24m" };
 212 PNAME(mux_vip_out_p)    = { "vip_src", "xin24m" };
 213 PNAME(mux_mac_p)        = { "mac_pll_src", "ext_gmac" };
 214 PNAME(mux_hsadcout_p)   = { "hsadc_src", "ext_hsadc" };
 215 PNAME(mux_edp_24m_p)    = { "ext_edp_24m", "xin24m" };
 216 PNAME(mux_tspout_p)     = { "cpll", "gpll", "npll", "xin27m" };
 217
 218 PNAME(mux_aclk_vcodec_pre_p)    = { "aclk_vdpu", "aclk_vepu" };
 219 PNAME(mux_usbphy480m_p)         = { "sclk_otgphy1_480m", "sclk_otgphy2_480m",
 220                                     "sclk_otgphy0_480m" };
 221 PNAME(mux_hsicphy480m_p)        = { "cpll", "gpll", "usbphy480m_src" };
 222 PNAME(mux_hsicphy12m_p)         = { "hsicphy12m_xin12m", "hsicphy12m_usbphy" };
 223
 224 static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = {
 225         [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK3288_PLL_CON(0),
 226                      RK3288_MODE_CON, 0, 6, 0, rk3288_pll_rates),
 227         [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK3288_PLL_CON(4),
 228                      RK3288_MODE_CON, 4, 5, 0, NULL),
 229         [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3288_PLL_CON(8),
 230                      RK3288_MODE_CON, 8, 7, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),
 231         [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12),
 232                      RK3288_MODE_CON, 12, 8, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),
 233         [npll] = PLL(pll_rk3066, PLL_NPLL, "npll",  mux_pll_p, 0, RK3288_PLL_CON(16),
 234                      RK3288_MODE_CON, 14, 9, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),
 235 };
 236
 237 static struct clk_div_table div_hclk_cpu_t[] = {
 238         { .val = 0, .div = 1 },
 239         { .val = 1, .div = 2 },
 240         { .val = 3, .div = 4 },
 241         { /* sentinel */},
 242 };
 243
 244 #define MFLAGS CLK_MUX_HIWORD_MASK
 245 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
 246 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
 247 #define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK
 248
 249 static struct rockchip_clk_branch rk3288_i2s_fracmux __initdata =
 250         MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT,
 251                         RK3288_CLKSEL_CON(4), 8, 2, MFLAGS);
 252
 253 static struct rockchip_clk_branch rk3288_spdif_fracmux __initdata =
 254         MUX(0, "spdif_mux", mux_spdif_p, CLK_SET_RATE_PARENT,
 255                         RK3288_CLKSEL_CON(5), 8, 2, MFLAGS);
 256
 257 static struct rockchip_clk_branch rk3288_spdif_8ch_fracmux __initdata =
 258         MUX(0, "spdif_8ch_mux", mux_spdif_8ch_p, CLK_SET_RATE_PARENT,
 259                         RK3288_CLKSEL_CON(40), 8, 2, MFLAGS);
 260
 261 static struct rockchip_clk_branch rk3288_uart0_fracmux __initdata =
 262         MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
 263                         RK3288_CLKSEL_CON(13), 8, 2, MFLAGS);
 264
 265 static struct rockchip_clk_branch rk3288_uart1_fracmux __initdata =
 266         MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
 267                         RK3288_CLKSEL_CON(14), 8, 2, MFLAGS);
 268
 269 static struct rockchip_clk_branch rk3288_uart2_fracmux __initdata =
 270         MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
 271                         RK3288_CLKSEL_CON(15), 8, 2, MFLAGS);
 272
 273 static struct rockchip_clk_branch rk3288_uart3_fracmux __initdata =
 274         MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
 275                         RK3288_CLKSEL_CON(16), 8, 2, MFLAGS);
 276
 277 static struct rockchip_clk_branch rk3288_uart4_fracmux __initdata =
 278         MUX(SCLK_UART4, "sclk_uart4", mux_uart4_p, CLK_SET_RATE_PARENT,
 279                         RK3288_CLKSEL_CON(3), 8, 2, MFLAGS);
 280
 281 static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
 282         /*
 283          * Clock-Architecture Diagram 1
 284          */
 285
 286         GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
 287                         RK3288_CLKGATE_CON(0), 1, GFLAGS),
 288         GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
 289                         RK3288_CLKGATE_CON(0), 2, GFLAGS),
 290
 291         COMPOSITE_NOMUX(0, "armcore0", "armclk", CLK_IGNORE_UNUSED,
 292                         RK3288_CLKSEL_CON(36), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
 293                         RK3288_CLKGATE_CON(12), 0, GFLAGS),
 294         COMPOSITE_NOMUX(0, "armcore1", "armclk", CLK_IGNORE_UNUSED,
 295                         RK3288_CLKSEL_CON(36), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
 296                         RK3288_CLKGATE_CON(12), 1, GFLAGS),
 297         COMPOSITE_NOMUX(0, "armcore2", "armclk", CLK_IGNORE_UNUSED,
 298                         RK3288_CLKSEL_CON(36), 8, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
 299                         RK3288_CLKGATE_CON(12), 2, GFLAGS),
 300         COMPOSITE_NOMUX(0, "armcore3", "armclk", CLK_IGNORE_UNUSED,
 301                         RK3288_CLKSEL_CON(36), 12, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
 302                         RK3288_CLKGATE_CON(12), 3, GFLAGS),
 303         COMPOSITE_NOMUX(0, "l2ram", "armclk", CLK_IGNORE_UNUSED,
 304                         RK3288_CLKSEL_CON(37), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
 305                         RK3288_CLKGATE_CON(12), 4, GFLAGS),
 306         COMPOSITE_NOMUX(0, "aclk_core_m0", "armclk", CLK_IGNORE_UNUSED,
 307                         RK3288_CLKSEL_CON(0), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
 308                         RK3288_CLKGATE_CON(12), 5, GFLAGS),
 309         COMPOSITE_NOMUX(0, "aclk_core_mp", "armclk", CLK_IGNORE_UNUSED,
 310                         RK3288_CLKSEL_CON(0), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
 311                         RK3288_CLKGATE_CON(12), 6, GFLAGS),
 312         COMPOSITE_NOMUX(0, "atclk", "armclk", 0,
 313                         RK3288_CLKSEL_CON(37), 4, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
 314                         RK3288_CLKGATE_CON(12), 7, GFLAGS),
 315         COMPOSITE_NOMUX(0, "pclk_dbg_pre", "armclk", CLK_IGNORE_UNUSED,
 316                         RK3288_CLKSEL_CON(37), 9, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
 317                         RK3288_CLKGATE_CON(12), 8, GFLAGS),
 318         GATE(0, "pclk_dbg", "pclk_dbg_pre", 0,
 319                         RK3288_CLKGATE_CON(12), 9, GFLAGS),
 320         GATE(0, "cs_dbg", "pclk_dbg_pre", CLK_IGNORE_UNUSED,
 321                         RK3288_CLKGATE_CON(12), 10, GFLAGS),
 322         GATE(0, "pclk_core_niu", "pclk_dbg_pre", 0,
 323                         RK3288_CLKGATE_CON(12), 11, GFLAGS),
 324
 325         GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
 326                         RK3288_CLKGATE_CON(0), 8, GFLAGS),
 327         GATE(0, "gpll_ddr", "gpll", 0,
 328                         RK3288_CLKGATE_CON(0), 9, GFLAGS),
 329         COMPOSITE_NOGATE(0, "ddrphy", mux_ddrphy_p, CLK_IGNORE_UNUSED,
 330                         RK3288_CLKSEL_CON(26), 2, 1, MFLAGS, 0, 2,
 331                                         DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
 332
 333         GATE(0, "gpll_aclk_cpu", "gpll", CLK_IGNORE_UNUSED,
 334                         RK3288_CLKGATE_CON(0), 10, GFLAGS),
 335         GATE(0, "cpll_aclk_cpu", "cpll", CLK_IGNORE_UNUSED,
 336                         RK3288_CLKGATE_CON(0), 11, GFLAGS),
 337         COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, CLK_IGNORE_UNUSED,
 338                         RK3288_CLKSEL_CON(1), 15, 1, MFLAGS, 3, 5, DFLAGS),
 339         DIV(0, "aclk_cpu_pre", "aclk_cpu_src", CLK_SET_RATE_PARENT,
 340                         RK3288_CLKSEL_CON(1), 0, 3, DFLAGS),
 341         GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,
 342                         RK3288_CLKGATE_CON(0), 3, GFLAGS),
 343         COMPOSITE_NOMUX(PCLK_CPU, "pclk_cpu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,
 344                         RK3288_CLKSEL_CON(1), 12, 3, DFLAGS,
 345                         RK3288_CLKGATE_CON(0), 5, GFLAGS),
 346         COMPOSITE_NOMUX_DIVTBL(HCLK_CPU, "hclk_cpu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,
 347                         RK3288_CLKSEL_CON(1), 8, 2, DFLAGS, div_hclk_cpu_t,
 348                         RK3288_CLKGATE_CON(0), 4, GFLAGS),
 349         GATE(0, "c2c_host", "aclk_cpu_src", 0,
 350                         RK3288_CLKGATE_CON(13), 8, GFLAGS),
 351         COMPOSITE_NOMUX(SCLK_CRYPTO, "crypto", "aclk_cpu_pre", 0,
 352                         RK3288_CLKSEL_CON(26), 6, 2, DFLAGS,
 353                         RK3288_CLKGATE_CON(5), 4, GFLAGS),
 354         GATE(0, "aclk_bus_2pmu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,
 355                         RK3288_CLKGATE_CON(0), 7, GFLAGS),
 356
 357         FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
 358
 359         COMPOSITE(0, "i2s_src", mux_pll_src_cpll_gpll_p, 0,
 360                         RK3288_CLKSEL_CON(4), 15, 1, MFLAGS, 0, 7, DFLAGS,
 361                         RK3288_CLKGATE_CON(4), 1, GFLAGS),
 362         COMPOSITE_FRACMUX(0, "i2s_frac", "i2s_src", CLK_SET_RATE_PARENT,
 363                         RK3288_CLKSEL_CON(8), 0,
 364                         RK3288_CLKGATE_CON(4), 2, GFLAGS,
 365                         &rk3288_i2s_fracmux),
 366         COMPOSITE_NODIV(SCLK_I2S0_OUT, "i2s0_clkout", mux_i2s_clkout_p, 0,
 367                         RK3288_CLKSEL_CON(4), 12, 1, MFLAGS,
 368                         RK3288_CLKGATE_CON(4), 0, GFLAGS),
 369         GATE(SCLK_I2S0, "sclk_i2s0", "i2s_pre", CLK_SET_RATE_PARENT,
 370                         RK3288_CLKGATE_CON(4), 3, GFLAGS),
 371
 372         MUX(0, "spdif_src", mux_pll_src_cpll_gpll_p, 0,
 373                         RK3288_CLKSEL_CON(5), 15, 1, MFLAGS),
 374         COMPOSITE_NOMUX(0, "spdif_pre", "spdif_src", CLK_SET_RATE_PARENT,
 375                         RK3288_CLKSEL_CON(5), 0, 7, DFLAGS,
 376                         RK3288_CLKGATE_CON(4), 4, GFLAGS),
 377         COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_src", CLK_SET_RATE_PARENT,
 378                         RK3288_CLKSEL_CON(9), 0,
 379                         RK3288_CLKGATE_CON(4), 5, GFLAGS,
 380                         &rk3288_spdif_fracmux),
 381         GATE(SCLK_SPDIF, "sclk_spdif", "spdif_mux", CLK_SET_RATE_PARENT,
 382                         RK3288_CLKGATE_CON(4), 6, GFLAGS),
 383         COMPOSITE_NOMUX(0, "spdif_8ch_pre", "spdif_src", CLK_SET_RATE_PARENT,
 384                         RK3288_CLKSEL_CON(40), 0, 7, DFLAGS,
 385                         RK3288_CLKGATE_CON(4), 7, GFLAGS),
 386         COMPOSITE_FRACMUX(0, "spdif_8ch_frac", "spdif_8ch_pre", CLK_SET_RATE_PARENT,
 387                         RK3288_CLKSEL_CON(41), 0,
 388                         RK3288_CLKGATE_CON(4), 8, GFLAGS,
 389                         &rk3288_spdif_8ch_fracmux),
 390         GATE(SCLK_SPDIF8CH, "sclk_spdif_8ch", "spdif_8ch_mux", CLK_SET_RATE_PARENT,
 391                         RK3288_CLKGATE_CON(4), 9, GFLAGS),
 392
 393         GATE(0, "sclk_acc_efuse", "xin24m", 0,
 394                         RK3288_CLKGATE_CON(0), 12, GFLAGS),
 395
 396         GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
 397                         RK3288_CLKGATE_CON(1), 0, GFLAGS),
 398         GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
 399                         RK3288_CLKGATE_CON(1), 1, GFLAGS),
 400         GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
 401                         RK3288_CLKGATE_CON(1), 2, GFLAGS),
 402         GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
 403                         RK3288_CLKGATE_CON(1), 3, GFLAGS),
 404         GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
 405                         RK3288_CLKGATE_CON(1), 4, GFLAGS),
 406         GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
 407                         RK3288_CLKGATE_CON(1), 5, GFLAGS),
 408
 409         /*
 410          * Clock-Architecture Diagram 2
 411          */
 412
 413         COMPOSITE(0, "aclk_vepu", mux_pll_src_cpll_gpll_usb480m_p, 0,
 414                         RK3288_CLKSEL_CON(32), 6, 2, MFLAGS, 0, 5, DFLAGS,
 415                         RK3288_CLKGATE_CON(3), 9, GFLAGS),
 416         COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_usb480m_p, 0,
 417                         RK3288_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS,
 418                         RK3288_CLKGATE_CON(3), 11, GFLAGS),
 419         MUXGRF(0, "aclk_vcodec_pre", mux_aclk_vcodec_pre_p, CLK_SET_RATE_PARENT,
 420                         RK3288_GRF_SOC_CON(0), 7, 1, MFLAGS),
 421         GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vcodec_pre", 0,
 422                 RK3288_CLKGATE_CON(9), 0, GFLAGS),
 423
 424         FACTOR_GATE(0, "hclk_vcodec_pre", "aclk_vcodec_pre", 0, 1, 4,
 425                 RK3288_CLKGATE_CON(3), 10, GFLAGS),
 426
 427         GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0,
 428                 RK3288_CLKGATE_CON(9), 1, GFLAGS),
 429
 430         COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
 431                         RK3288_CLKSEL_CON(31), 6, 2, MFLAGS, 0, 5, DFLAGS,
 432                         RK3288_CLKGATE_CON(3), 0, GFLAGS),
 433         COMPOSITE(0, "aclk_vio1", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
 434                         RK3288_CLKSEL_CON(31), 14, 2, MFLAGS, 8, 5, DFLAGS,
 435                         RK3288_CLKGATE_CON(3), 2, GFLAGS),
 436
 437         COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_usb480m_p, 0,
 438                         RK3288_CLKSEL_CON(30), 6, 2, MFLAGS, 0, 5, DFLAGS,
 439                         RK3288_CLKGATE_CON(3), 5, GFLAGS),
 440         COMPOSITE(SCLK_RGA, "sclk_rga", mux_pll_src_cpll_gpll_usb480m_p, 0,
 441                         RK3288_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS,
 442                         RK3288_CLKGATE_CON(3), 4, GFLAGS),
 443
 444         COMPOSITE(DCLK_VOP0, "dclk_vop0", mux_pll_src_cpll_gpll_npll_p, 0,
 445                         RK3288_CLKSEL_CON(27), 0, 2, MFLAGS, 8, 8, DFLAGS,
 446                         RK3288_CLKGATE_CON(3), 1, GFLAGS),
 447         COMPOSITE(DCLK_VOP1, "dclk_vop1", mux_pll_src_cpll_gpll_npll_p, 0,
 448                         RK3288_CLKSEL_CON(29), 6, 2, MFLAGS, 8, 8, DFLAGS,
 449                         RK3288_CLKGATE_CON(3), 3, GFLAGS),
 450
 451         COMPOSITE_NODIV(SCLK_EDP_24M, "sclk_edp_24m", mux_edp_24m_p, 0,
 452                         RK3288_CLKSEL_CON(28), 15, 1, MFLAGS,
 453                         RK3288_CLKGATE_CON(3), 12, GFLAGS),
 454         COMPOSITE(SCLK_EDP, "sclk_edp", mux_pll_src_cpll_gpll_npll_p, 0,
 455                         RK3288_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 6, DFLAGS,
 456                         RK3288_CLKGATE_CON(3), 13, GFLAGS),
 457
 458         COMPOSITE(SCLK_ISP, "sclk_isp", mux_pll_src_cpll_gpll_npll_p, 0,
 459                         RK3288_CLKSEL_CON(6), 6, 2, MFLAGS, 0, 6, DFLAGS,
 460                         RK3288_CLKGATE_CON(3), 14, GFLAGS),
 461         COMPOSITE(SCLK_ISP_JPE, "sclk_isp_jpe", mux_pll_src_cpll_gpll_npll_p, 0,
 462                         RK3288_CLKSEL_CON(6), 14, 2, MFLAGS, 8, 6, DFLAGS,
 463                         RK3288_CLKGATE_CON(3), 15, GFLAGS),
 464
 465         GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0,
 466                         RK3288_CLKGATE_CON(5), 12, GFLAGS),
 467         GATE(SCLK_HDMI_CEC, "sclk_hdmi_cec", "xin32k", 0,
 468                         RK3288_CLKGATE_CON(5), 11, GFLAGS),
 469
 470         COMPOSITE(ACLK_HEVC, "aclk_hevc", mux_pll_src_cpll_gpll_npll_p, 0,
 471                         RK3288_CLKSEL_CON(39), 14, 2, MFLAGS, 8, 5, DFLAGS,
 472                         RK3288_CLKGATE_CON(13), 13, GFLAGS),
 473         DIV(HCLK_HEVC, "hclk_hevc", "aclk_hevc", 0,
 474                         RK3288_CLKSEL_CON(40), 12, 2, DFLAGS),
 475
 476         COMPOSITE(SCLK_HEVC_CABAC, "sclk_hevc_cabac", mux_pll_src_cpll_gpll_npll_p, 0,
 477                         RK3288_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS,
 478                         RK3288_CLKGATE_CON(13), 14, GFLAGS),
 479         COMPOSITE(SCLK_HEVC_CORE, "sclk_hevc_core", mux_pll_src_cpll_gpll_npll_p, 0,
 480                         RK3288_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS,
 481                         RK3288_CLKGATE_CON(13), 15, GFLAGS),
 482
 483         COMPOSITE_NODIV(0, "vip_src", mux_pll_src_cpll_gpll_p, 0,
 484                         RK3288_CLKSEL_CON(26), 8, 1, MFLAGS,
 485                         RK3288_CLKGATE_CON(3), 7, GFLAGS),
 486         COMPOSITE_NOGATE(SCLK_VIP_OUT, "sclk_vip_out", mux_vip_out_p, 0,
 487                         RK3288_CLKSEL_CON(26), 15, 1, MFLAGS, 9, 5, DFLAGS),
 488
 489         DIV(0, "pclk_pd_alive", "gpll", 0,
 490                         RK3288_CLKSEL_CON(33), 8, 5, DFLAGS),
 491         COMPOSITE_NOMUX(0, "pclk_pd_pmu", "gpll", CLK_IGNORE_UNUSED,
 492                         RK3288_CLKSEL_CON(33), 0, 5, DFLAGS,
 493                         RK3288_CLKGATE_CON(5), 8, GFLAGS),
 494
 495         COMPOSITE(SCLK_GPU, "sclk_gpu", mux_pll_src_cpll_gll_usb_npll_p, 0,
 496                         RK3288_CLKSEL_CON(34), 6, 2, MFLAGS, 0, 5, DFLAGS,
 497                         RK3288_CLKGATE_CON(5), 7, GFLAGS),
 498
 499         COMPOSITE(0, "aclk_peri_src", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
 500                         RK3288_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS,
 501                         RK3288_CLKGATE_CON(2), 0, GFLAGS),
 502         COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0,
 503                         RK3288_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
 504                         RK3288_CLKGATE_CON(2), 3, GFLAGS),
 505         COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", CLK_IGNORE_UNUSED,
 506                         RK3288_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
 507                         RK3288_CLKGATE_CON(2), 2, GFLAGS),
 508         GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", CLK_IGNORE_UNUSED,
 509                         RK3288_CLKGATE_CON(2), 1, GFLAGS),
 510
 511         /*
 512          * Clock-Architecture Diagram 3
 513          */
 514
 515         COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_cpll_gpll_p, 0,
 516                         RK3288_CLKSEL_CON(25), 7, 1, MFLAGS, 0, 7, DFLAGS,
 517                         RK3288_CLKGATE_CON(2), 9, GFLAGS),
 518         COMPOSITE(SCLK_SPI1, "sclk_spi1", mux_pll_src_cpll_gpll_p, 0,
 519                         RK3288_CLKSEL_CON(25), 15, 1, MFLAGS, 8, 7, DFLAGS,
 520                         RK3288_CLKGATE_CON(2), 10, GFLAGS),
 521         COMPOSITE(SCLK_SPI2, "sclk_spi2", mux_pll_src_cpll_gpll_p, 0,
 522                         RK3288_CLKSEL_CON(39), 7, 1, MFLAGS, 0, 7, DFLAGS,
 523                         RK3288_CLKGATE_CON(2), 11, GFLAGS),
 524
 525         COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,
 526                         RK3288_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 6, DFLAGS,
 527                         RK3288_CLKGATE_CON(13), 0, GFLAGS),
 528         COMPOSITE(SCLK_SDIO0, "sclk_sdio0", mux_mmc_src_p, 0,
 529                         RK3288_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 6, DFLAGS,
 530                         RK3288_CLKGATE_CON(13), 1, GFLAGS),
 531         COMPOSITE(SCLK_SDIO1, "sclk_sdio1", mux_mmc_src_p, 0,
 532                         RK3288_CLKSEL_CON(34), 14, 2, MFLAGS, 8, 6, DFLAGS,
 533                         RK3288_CLKGATE_CON(13), 2, GFLAGS),
 534         COMPOSITE(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0,
 535                         RK3288_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 6, DFLAGS,
 536                         RK3288_CLKGATE_CON(13), 3, GFLAGS),
 537
 538         MMC(SCLK_SDMMC_DRV,    "sdmmc_drv",    "sclk_sdmmc", RK3288_SDMMC_CON0, 1),
 539         MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3288_SDMMC_CON1, 0),
 540
 541         MMC(SCLK_SDIO0_DRV,    "sdio0_drv",    "sclk_sdio0", RK3288_SDIO0_CON0, 1),
 542         MMC(SCLK_SDIO0_SAMPLE, "sdio0_sample", "sclk_sdio0", RK3288_SDIO0_CON1, 0),
 543
 544         MMC(SCLK_SDIO1_DRV,    "sdio1_drv",    "sclk_sdio1", RK3288_SDIO1_CON0, 1),
 545         MMC(SCLK_SDIO1_SAMPLE, "sdio1_sample", "sclk_sdio1", RK3288_SDIO1_CON1, 0),
 546
 547         MMC(SCLK_EMMC_DRV,     "emmc_drv",     "sclk_emmc",  RK3288_EMMC_CON0,  1),
 548         MMC(SCLK_EMMC_SAMPLE,  "emmc_sample",  "sclk_emmc",  RK3288_EMMC_CON1,  0),
 549
 550         COMPOSITE(0, "sclk_tspout", mux_tspout_p, 0,
 551                         RK3288_CLKSEL_CON(35), 14, 2, MFLAGS, 8, 5, DFLAGS,
 552                         RK3288_CLKGATE_CON(4), 11, GFLAGS),
 553         COMPOSITE(0, "sclk_tsp", mux_pll_src_cpll_gpll_npll_p, 0,
 554                         RK3288_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS,
 555                         RK3288_CLKGATE_CON(4), 10, GFLAGS),
 556
 557         GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", CLK_IGNORE_UNUSED,
 558                         RK3288_CLKGATE_CON(13), 4, GFLAGS),
 559         GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin24m", CLK_IGNORE_UNUSED,
 560                         RK3288_CLKGATE_CON(13), 5, GFLAGS),
 561         GATE(SCLK_OTGPHY2, "sclk_otgphy2", "xin24m", CLK_IGNORE_UNUSED,
 562                         RK3288_CLKGATE_CON(13), 6, GFLAGS),
 563         GATE(SCLK_OTG_ADP, "sclk_otg_adp", "xin32k", CLK_IGNORE_UNUSED,
 564                         RK3288_CLKGATE_CON(13), 7, GFLAGS),
 565
 566         COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin32k", 0,
 567                         RK3288_CLKSEL_CON(2), 0, 6, DFLAGS,
 568                         RK3288_CLKGATE_CON(2), 7, GFLAGS),
 569
 570         COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0,
 571                         RK3288_CLKSEL_CON(24), 8, 8, DFLAGS,
 572                         RK3288_CLKGATE_CON(2), 8, GFLAGS),
 573
 574         GATE(SCLK_PS2C, "sclk_ps2c", "xin24m", 0,
 575                         RK3288_CLKGATE_CON(5), 13, GFLAGS),
 576
 577         COMPOSITE(SCLK_NANDC0, "sclk_nandc0", mux_pll_src_cpll_gpll_p, 0,
 578                         RK3288_CLKSEL_CON(38), 7, 1, MFLAGS, 0, 5, DFLAGS,
 579                         RK3288_CLKGATE_CON(5), 5, GFLAGS),
 580         COMPOSITE(SCLK_NANDC1, "sclk_nandc1", mux_pll_src_cpll_gpll_p, 0,
 581                         RK3288_CLKSEL_CON(38), 15, 1, MFLAGS, 8, 5, DFLAGS,
 582                         RK3288_CLKGATE_CON(5), 6, GFLAGS),
 583
 584         COMPOSITE(0, "uart0_src", mux_pll_src_cpll_gll_usb_npll_p, 0,
 585                         RK3288_CLKSEL_CON(13), 13, 2, MFLAGS, 0, 7, DFLAGS,
 586                         RK3288_CLKGATE_CON(1), 8, GFLAGS),
 587         COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
 588                         RK3288_CLKSEL_CON(17), 0,
 589                         RK3288_CLKGATE_CON(1), 9, GFLAGS,
 590                         &rk3288_uart0_fracmux),
 591         MUX(0, "uart_src", mux_pll_src_cpll_gpll_p, 0,
 592                         RK3288_CLKSEL_CON(13), 15, 1, MFLAGS),
 593         COMPOSITE_NOMUX(0, "uart1_src", "uart_src", 0,
 594                         RK3288_CLKSEL_CON(14), 0, 7, DFLAGS,
 595                         RK3288_CLKGATE_CON(1), 10, GFLAGS),
 596         COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
 597                         RK3288_CLKSEL_CON(18), 0,
 598                         RK3288_CLKGATE_CON(1), 11, GFLAGS,
 599                         &rk3288_uart1_fracmux),
 600         COMPOSITE_NOMUX(0, "uart2_src", "uart_src", 0,
 601                         RK3288_CLKSEL_CON(15), 0, 7, DFLAGS,
 602                         RK3288_CLKGATE_CON(1), 12, GFLAGS),
 603         COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
 604                         RK3288_CLKSEL_CON(19), 0,
 605                         RK3288_CLKGATE_CON(1), 13, GFLAGS,
 606                         &rk3288_uart2_fracmux),
 607         COMPOSITE_NOMUX(0, "uart3_src", "uart_src", 0,
 608                         RK3288_CLKSEL_CON(16), 0, 7, DFLAGS,
 609                         RK3288_CLKGATE_CON(1), 14, GFLAGS),
 610         COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_src", CLK_SET_RATE_PARENT,
 611                         RK3288_CLKSEL_CON(20), 0,
 612                         RK3288_CLKGATE_CON(1), 15, GFLAGS,
 613                         &rk3288_uart3_fracmux),
 614         COMPOSITE_NOMUX(0, "uart4_src", "uart_src", 0,
 615                         RK3288_CLKSEL_CON(3), 0, 7, DFLAGS,
 616                         RK3288_CLKGATE_CON(2), 12, GFLAGS),
 617         COMPOSITE_FRACMUX(0, "uart4_frac", "uart4_src", CLK_SET_RATE_PARENT,
 618                         RK3288_CLKSEL_CON(7), 0,
 619                         RK3288_CLKGATE_CON(2), 13, GFLAGS,
 620                         &rk3288_uart4_fracmux),
 621
 622         COMPOSITE(0, "mac_pll_src", mux_pll_src_npll_cpll_gpll_p, 0,
 623                         RK3288_CLKSEL_CON(21), 0, 2, MFLAGS, 8, 5, DFLAGS,
 624                         RK3288_CLKGATE_CON(2), 5, GFLAGS),
 625         MUX(SCLK_MAC, "mac_clk", mux_mac_p, CLK_SET_RATE_PARENT,
 626                         RK3288_CLKSEL_CON(21), 4, 1, MFLAGS),
 627         GATE(SCLK_MACREF_OUT, "sclk_macref_out", "mac_clk", 0,
 628                         RK3288_CLKGATE_CON(5), 3, GFLAGS),
 629         GATE(SCLK_MACREF, "sclk_macref", "mac_clk", 0,
 630                         RK3288_CLKGATE_CON(5), 2, GFLAGS),
 631         GATE(SCLK_MAC_RX, "sclk_mac_rx", "mac_clk", 0,
 632                         RK3288_CLKGATE_CON(5), 0, GFLAGS),
 633         GATE(SCLK_MAC_TX, "sclk_mac_tx", "mac_clk", 0,
 634                         RK3288_CLKGATE_CON(5), 1, GFLAGS),
 635
 636         COMPOSITE(0, "hsadc_src", mux_pll_src_cpll_gpll_p, 0,
 637                         RK3288_CLKSEL_CON(22), 0, 1, MFLAGS, 8, 8, DFLAGS,
 638                         RK3288_CLKGATE_CON(2), 6, GFLAGS),
 639         MUX(0, "sclk_hsadc_out", mux_hsadcout_p, 0,
 640                         RK3288_CLKSEL_CON(22), 4, 1, MFLAGS),
 641         INVERTER(SCLK_HSADC, "sclk_hsadc", "sclk_hsadc_out",
 642                         RK3288_CLKSEL_CON(22), 7, IFLAGS),
 643
 644         GATE(0, "jtag", "ext_jtag", 0,
 645                         RK3288_CLKGATE_CON(4), 14, GFLAGS),
 646
 647         COMPOSITE_NODIV(SCLK_USBPHY480M_SRC, "usbphy480m_src", mux_usbphy480m_p, 0,
 648                         RK3288_CLKSEL_CON(13), 11, 2, MFLAGS,
 649                         RK3288_CLKGATE_CON(5), 14, GFLAGS),
 650         COMPOSITE_NODIV(SCLK_HSICPHY480M, "sclk_hsicphy480m", mux_hsicphy480m_p, 0,
 651                         RK3288_CLKSEL_CON(29), 0, 2, MFLAGS,
 652                         RK3288_CLKGATE_CON(3), 6, GFLAGS),
 653         GATE(0, "hsicphy12m_xin12m", "xin12m", 0,
 654                         RK3288_CLKGATE_CON(13), 9, GFLAGS),
 655         DIV(0, "hsicphy12m_usbphy", "sclk_hsicphy480m", 0,
 656                         RK3288_CLKSEL_CON(11), 8, 6, DFLAGS),
 657         MUX(SCLK_HSICPHY12M, "sclk_hsicphy12m", mux_hsicphy12m_p, 0,
 658                         RK3288_CLKSEL_CON(22), 4, 1, MFLAGS),
 659
 660         /*
 661          * Clock-Architecture Diagram 4
 662          */
 663
 664         /* aclk_cpu gates */
 665         GATE(0, "sclk_intmem0", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 5, GFLAGS),
 666         GATE(0, "sclk_intmem1", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 6, GFLAGS),
 667         GATE(0, "sclk_intmem2", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 7, GFLAGS),
 668         GATE(ACLK_DMAC1, "aclk_dmac1", "aclk_cpu", 0, RK3288_CLKGATE_CON(10), 12, GFLAGS),
 669         GATE(0, "aclk_strc_sys", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 13, GFLAGS),
 670         GATE(0, "aclk_intmem", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 4, GFLAGS),
 671         GATE(ACLK_CRYPTO, "aclk_crypto", "aclk_cpu", 0, RK3288_CLKGATE_CON(11), 6, GFLAGS),
 672         GATE(0, "aclk_ccp", "aclk_cpu", 0, RK3288_CLKGATE_CON(11), 8, GFLAGS),
 673
 674         /* hclk_cpu gates */
 675         GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_cpu", 0, RK3288_CLKGATE_CON(11), 7, GFLAGS),
 676         GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 8, GFLAGS),
 677         GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 9, GFLAGS),
 678         GATE(HCLK_SPDIF, "hclk_spdif", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 10, GFLAGS),
 679         GATE(HCLK_SPDIF8CH, "hclk_spdif_8ch", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 11, GFLAGS),
 680
 681         /* pclk_cpu gates */
 682         GATE(PCLK_PWM, "pclk_pwm", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 0, GFLAGS),
 683         GATE(PCLK_TIMER, "pclk_timer", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 1, GFLAGS),
 684         GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 2, GFLAGS),
 685         GATE(PCLK_I2C2, "pclk_i2c2", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 3, GFLAGS),
 686         GATE(PCLK_DDRUPCTL0, "pclk_ddrupctl0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 14, GFLAGS),
 687         GATE(PCLK_PUBL0, "pclk_publ0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 15, GFLAGS),
 688         GATE(PCLK_DDRUPCTL1, "pclk_ddrupctl1", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 0, GFLAGS),
 689         GATE(PCLK_PUBL1, "pclk_publ1", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 1, GFLAGS),
 690         GATE(PCLK_EFUSE1024, "pclk_efuse_1024", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 2, GFLAGS),
 691         GATE(PCLK_TZPC, "pclk_tzpc", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 3, GFLAGS),
 692         GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 9, GFLAGS),
 693         GATE(PCLK_EFUSE256, "pclk_efuse_256", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 10, GFLAGS),
 694         GATE(PCLK_RKPWM, "pclk_rkpwm", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 11, GFLAGS),
 695
 696         /* ddrctrl [DDR Controller PHY clock] gates */
 697         GATE(0, "nclk_ddrupctl0", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 4, GFLAGS),
 698         GATE(0, "nclk_ddrupctl1", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 5, GFLAGS),
 699
 700         /* ddrphy gates */
 701         GATE(0, "sclk_ddrphy0", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(4), 12, GFLAGS),
 702         GATE(0, "sclk_ddrphy1", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(4), 13, GFLAGS),
 703
 704         /* aclk_peri gates */
 705         GATE(0, "aclk_peri_axi_matrix", "aclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(6), 2, GFLAGS),
 706         GATE(ACLK_DMAC2, "aclk_dmac2", "aclk_peri", 0, RK3288_CLKGATE_CON(6), 3, GFLAGS),
 707         GATE(0, "aclk_peri_niu", "aclk_peri", 0, RK3288_CLKGATE_CON(7), 11, GFLAGS),
 708         GATE(ACLK_MMU, "aclk_mmu", "aclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(8), 12, GFLAGS),
 709         GATE(ACLK_GMAC, "aclk_gmac", "aclk_peri", 0, RK3288_CLKGATE_CON(8), 0, GFLAGS),
 710         GATE(HCLK_GPS, "hclk_gps", "aclk_peri", 0, RK3288_CLKGATE_CON(8), 2, GFLAGS),
 711
 712         /* hclk_peri gates */
 713         GATE(0, "hclk_peri_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(6), 0, GFLAGS),
 714         GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 4, GFLAGS),
 715         GATE(HCLK_USBHOST0, "hclk_host0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 6, GFLAGS),
 716         GATE(HCLK_USBHOST1, "hclk_host1", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 7, GFLAGS),
 717         GATE(HCLK_HSIC, "hclk_hsic", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 8, GFLAGS),
 718         GATE(0, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 9, GFLAGS),
 719         GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 10, GFLAGS),
 720         GATE(0, "hclk_emem", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 12, GFLAGS),
 721         GATE(0, "hclk_mem", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 13, GFLAGS),
 722         GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 14, GFLAGS),
 723         GATE(HCLK_NANDC1, "hclk_nandc1", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 15, GFLAGS),
 724         GATE(HCLK_TSP, "hclk_tsp", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 8, GFLAGS),
 725         GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 3, GFLAGS),
 726         GATE(HCLK_SDIO0, "hclk_sdio0", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 4, GFLAGS),
 727         GATE(HCLK_SDIO1, "hclk_sdio1", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 5, GFLAGS),
 728         GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 6, GFLAGS),
 729         GATE(HCLK_HSADC, "hclk_hsadc", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 7, GFLAGS),
 730         GATE(0, "pmu_hclk_otg0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 5, GFLAGS),
 731
 732         /* pclk_peri gates */
 733         GATE(0, "pclk_peri_matrix", "pclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(6), 1, GFLAGS),
 734         GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 4, GFLAGS),
 735         GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 5, GFLAGS),
 736         GATE(PCLK_SPI2, "pclk_spi2", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 6, GFLAGS),
 737         GATE(PCLK_PS2C, "pclk_ps2c", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 7, GFLAGS),
 738         GATE(PCLK_UART0, "pclk_uart0", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 8, GFLAGS),
 739         GATE(PCLK_UART1, "pclk_uart1", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 9, GFLAGS),
 740         GATE(PCLK_I2C4, "pclk_i2c4", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 15, GFLAGS),
 741         GATE(PCLK_UART3, "pclk_uart3", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 11, GFLAGS),
 742         GATE(PCLK_UART4, "pclk_uart4", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 12, GFLAGS),
 743         GATE(PCLK_I2C1, "pclk_i2c1", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 13, GFLAGS),
 744         GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 14, GFLAGS),
 745         GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 1, GFLAGS),
 746         GATE(PCLK_TSADC, "pclk_tsadc", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 2, GFLAGS),
 747         GATE(PCLK_SIM, "pclk_sim", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 3, GFLAGS),
 748         GATE(PCLK_I2C5, "pclk_i2c5", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 0, GFLAGS),
 749         GATE(PCLK_GMAC, "pclk_gmac", "pclk_peri", 0, RK3288_CLKGATE_CON(8), 1, GFLAGS),
 750
 751         GATE(SCLK_LCDC_PWM0, "sclk_lcdc_pwm0", "xin24m", 0, RK3288_CLKGATE_CON(13), 10, GFLAGS),
 752         GATE(SCLK_LCDC_PWM1, "sclk_lcdc_pwm1", "xin24m", 0, RK3288_CLKGATE_CON(13), 11, GFLAGS),
 753         GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK3288_CLKGATE_CON(5), 9, GFLAGS),
 754         GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu", "xin24m", 0, RK3288_CLKGATE_CON(5), 10, GFLAGS),
 755         GATE(SCLK_MIPIDSI_24M, "sclk_mipidsi_24m", "xin24m", 0, RK3288_CLKGATE_CON(5), 15, GFLAGS),
 756
 757         /* sclk_gpu gates */
 758         GATE(ACLK_GPU, "aclk_gpu", "sclk_gpu", 0, RK3288_CLKGATE_CON(18), 0, GFLAGS),
 759
 760         /* pclk_pd_alive gates */
 761         GATE(PCLK_GPIO8, "pclk_gpio8", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 8, GFLAGS),
 762         GATE(PCLK_GPIO7, "pclk_gpio7", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 7, GFLAGS),
 763         GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 1, GFLAGS),
 764         GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 2, GFLAGS),
 765         GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 3, GFLAGS),
 766         GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 4, GFLAGS),
 767         GATE(PCLK_GPIO5, "pclk_gpio5", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 5, GFLAGS),
 768         GATE(PCLK_GPIO6, "pclk_gpio6", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 6, GFLAGS),
 769         GATE(PCLK_GRF, "pclk_grf", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(14), 11, GFLAGS),
 770         GATE(0, "pclk_alive_niu", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 12, GFLAGS),
 771
 772         /* Watchdog pclk is controlled by RK3288_SGRF_SOC_CON0[1]. */
 773         SGRF_GATE(PCLK_WDT, "pclk_wdt", "pclk_pd_alive"),
 774
 775         /* pclk_pd_pmu gates */
 776         GATE(PCLK_PMU, "pclk_pmu", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 0, GFLAGS),
 777         GATE(0, "pclk_intmem1", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 1, GFLAGS),
 778         GATE(0, "pclk_pmu_niu", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 2, GFLAGS),
 779         GATE(PCLK_SGRF, "pclk_sgrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 3, GFLAGS),
 780         GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 4, GFLAGS),
 781
 782         /* hclk_vio gates */
 783         GATE(HCLK_RGA, "hclk_rga", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 1, GFLAGS),
 784         GATE(HCLK_VOP0, "hclk_vop0", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 6, GFLAGS),
 785         GATE(HCLK_VOP1, "hclk_vop1", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 8, GFLAGS),
 786         GATE(HCLK_VIO_AHB_ARBI, "hclk_vio_ahb_arbi", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 9, GFLAGS),
 787         GATE(HCLK_VIO_NIU, "hclk_vio_niu", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 10, GFLAGS),
 788         GATE(HCLK_VIP, "hclk_vip", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 15, GFLAGS),
 789         GATE(HCLK_IEP, "hclk_iep", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 3, GFLAGS),
 790         GATE(HCLK_ISP, "hclk_isp", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 1, GFLAGS),
 791         GATE(HCLK_VIO2_H2P, "hclk_vio2_h2p", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(16), 10, GFLAGS),
 792         GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 4, GFLAGS),
 793         GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 5, GFLAGS),
 794         GATE(PCLK_MIPI_CSI, "pclk_mipi_csi", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 6, GFLAGS),
 795         GATE(PCLK_LVDS_PHY, "pclk_lvds_phy", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 7, GFLAGS),
 796         GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(16), 8, GFLAGS),
 797         GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 9, GFLAGS),
 798         GATE(PCLK_VIO2_H2P, "pclk_vio2_h2p", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(16), 11, GFLAGS),
 799
 800         /* aclk_vio0 gates */
 801         GATE(ACLK_VOP0, "aclk_vop0", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 5, GFLAGS),
 802         GATE(ACLK_IEP, "aclk_iep", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 2, GFLAGS),
 803         GATE(ACLK_VIO0_NIU, "aclk_vio0_niu", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 11, GFLAGS),
 804         GATE(ACLK_VIP, "aclk_vip", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 14, GFLAGS),
 805
 806         /* aclk_vio1 gates */
 807         GATE(ACLK_VOP1, "aclk_vop1", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 7, GFLAGS),
 808         GATE(ACLK_ISP, "aclk_isp", "aclk_vio1", 0, RK3288_CLKGATE_CON(16), 2, GFLAGS),
 809         GATE(ACLK_VIO1_NIU, "aclk_vio1_niu", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 12, GFLAGS),
 810
 811         /* aclk_rga_pre gates */
 812         GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 0, GFLAGS),
 813         GATE(ACLK_RGA_NIU, "aclk_rga_niu", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 13, GFLAGS),
 814
 815         /*
 816          * Other ungrouped clocks.
 817          */
 818
 819         GATE(0, "pclk_vip_in", "ext_vip", 0, RK3288_CLKGATE_CON(16), 0, GFLAGS),
 820         INVERTER(0, "pclk_vip", "pclk_vip_in", RK3288_CLKSEL_CON(29), 4, IFLAGS),
 821         GATE(PCLK_ISP_IN, "pclk_isp_in", "ext_isp", 0, RK3288_CLKGATE_CON(16), 3, GFLAGS),
 822         INVERTER(0, "pclk_isp", "pclk_isp_in", RK3288_CLKSEL_CON(29), 3, IFLAGS),
 823 };
 824
 825 static struct rockchip_clk_branch rk3288w_hclkvio_branch[] __initdata = {
 826         DIV(0, "hclk_vio", "aclk_vio1", 0,
 827                         RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
 828 };
 829
 830 static struct rockchip_clk_branch rk3288_hclkvio_branch[] __initdata = {
 831         DIV(0, "hclk_vio", "aclk_vio0", 0,
 832                         RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
 833 };
 834
 835 static const char *const rk3288_critical_clocks[] __initconst = {
 836         "aclk_cpu",
 837         "aclk_peri",
 838         "aclk_peri_niu",
 839         "aclk_vio0_niu",
 840         "aclk_vio1_niu",
 841         "aclk_rga_niu",
 842         "hclk_peri",
 843         "hclk_vio_niu",
 844         "pclk_alive_niu",
 845         "pclk_pd_pmu",
 846         "pclk_pmu_niu",
 847         "pmu_hclk_otg0",
 848         /* pwm-regulators on some boards, so handoff-critical later */
 849         "pclk_rkpwm",
 850 };
 851
 852 static void __iomem *rk3288_cru_base;
 853
 854 /*
 855  * Some CRU registers will be reset in maskrom when the system
 856  * wakes up from fastboot.
 857  * So save them before suspend, restore them after resume.
 858  */
 859 static const int rk3288_saved_cru_reg_ids[] = {
 860         RK3288_MODE_CON,
 861         RK3288_CLKSEL_CON(0),
 862         RK3288_CLKSEL_CON(1),
 863         RK3288_CLKSEL_CON(10),
 864         RK3288_CLKSEL_CON(33),
 865         RK3288_CLKSEL_CON(37),
 866
 867         /* We turn aclk_dmac1 on for suspend; this will restore it */
 868         RK3288_CLKGATE_CON(10),
 869 };
 870
 871 static u32 rk3288_saved_cru_regs[ARRAY_SIZE(rk3288_saved_cru_reg_ids)];
 872
 873 static int rk3288_clk_suspend(void)
 874 {
 875         int i, reg_id;
 876
 877         for (i = 0; i < ARRAY_SIZE(rk3288_saved_cru_reg_ids); i++) {
 878                 reg_id = rk3288_saved_cru_reg_ids[i];
 879
 880                 rk3288_saved_cru_regs[i] =
 881                                 readl_relaxed(rk3288_cru_base + reg_id);
 882         }
 883
 884         /*
 885          * Going into deep sleep (specifically setting PMU_CLR_DMA in
 886          * RK3288_PMU_PWRMODE_CON1) appears to fail unless
 887          * "aclk_dmac1" is on.
 888          */
 889         writel_relaxed(1 << (12 + 16),
 890                        rk3288_cru_base + RK3288_CLKGATE_CON(10));
 891
 892         /*
 893          * Switch PLLs other than DPLL (for SDRAM) to slow mode to
 894          * avoid crashes on resume. The Mask ROM on the system will
 895          * put APLL, CPLL, and GPLL into slow mode at resume time
 896          * anyway (which is why we restore them), but we might not
 897          * even make it to the Mask ROM if this isn't done at suspend
 898          * time.
 899          *
 900          * NOTE: only APLL truly matters here, but we'll do them all.
 901          */
 902
 903         writel_relaxed(0xf3030000, rk3288_cru_base + RK3288_MODE_CON);
 904
 905         return 0;
 906 }
 907
 908 static void rk3288_clk_resume(void)
 909 {
 910         int i, reg_id;
 911
 912         for (i = ARRAY_SIZE(rk3288_saved_cru_reg_ids) - 1; i >= 0; i--) {
 913                 reg_id = rk3288_saved_cru_reg_ids[i];
 914
 915                 writel_relaxed(rk3288_saved_cru_regs[i] | 0xffff0000,
 916                                rk3288_cru_base + reg_id);
 917         }
 918 }
 919
 920 static void rk3288_clk_shutdown(void)
 921 {
 922         writel_relaxed(0xf3030000, rk3288_cru_base + RK3288_MODE_CON);
 923 }
 924
 925 static struct syscore_ops rk3288_clk_syscore_ops = {
 926         .suspend = rk3288_clk_suspend,
 927         .resume = rk3288_clk_resume,
 928 };
 929
 930 static void __init rk3288_common_init(struct device_node *np,
 931                                       enum rk3288_variant soc)
 932 {
 933         struct rockchip_clk_provider *ctx;
 934
 935         rk3288_cru_base = of_iomap(np, 0);
 936         if (!rk3288_cru_base) {
 937                 pr_err("%s: could not map cru region\n", __func__);
 938                 return;
 939         }
 940
 941         ctx = rockchip_clk_init(np, rk3288_cru_base, CLK_NR_CLKS);
 942         if (IS_ERR(ctx)) {
 943                 pr_err("%s: rockchip clk init failed\n", __func__);
 944                 iounmap(rk3288_cru_base);
 945                 return;
 946         }
 947
 948         rockchip_clk_register_plls(ctx, rk3288_pll_clks,
 949                                    ARRAY_SIZE(rk3288_pll_clks),
 950                                    RK3288_GRF_SOC_STATUS1);
 951         rockchip_clk_register_branches(ctx, rk3288_clk_branches,
 952                                   ARRAY_SIZE(rk3288_clk_branches));
 953
 954         if (soc == RK3288W_CRU)
 955                 rockchip_clk_register_branches(ctx, rk3288w_hclkvio_branch,
 956                                                ARRAY_SIZE(rk3288w_hclkvio_branch));
 957         else
 958                 rockchip_clk_register_branches(ctx, rk3288_hclkvio_branch,
 959                                                ARRAY_SIZE(rk3288_hclkvio_branch));
 960
 961         rockchip_clk_protect_critical(rk3288_critical_clocks,
 962                                       ARRAY_SIZE(rk3288_critical_clocks));
 963
 964         rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
 965                         mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
 966                         &rk3288_cpuclk_data, rk3288_cpuclk_rates,
 967                         ARRAY_SIZE(rk3288_cpuclk_rates));
 968
 969         rockchip_register_softrst(np, 12,
 970                                   rk3288_cru_base + RK3288_SOFTRST_CON(0),
 971                                   ROCKCHIP_SOFTRST_HIWORD_MASK);
 972
 973         rockchip_register_restart_notifier(ctx, RK3288_GLB_SRST_FST,
 974                                            rk3288_clk_shutdown);
 975         register_syscore_ops(&rk3288_clk_syscore_ops);
 976
 977         rockchip_clk_of_add_provider(np, ctx);
 978 }
 979
 980 static void __init rk3288_clk_init(struct device_node *np)
 981 {
 982         rk3288_common_init(np, RK3288_CRU);
 983 }
 984 CLK_OF_DECLARE(rk3288_cru, "rockchip,rk3288-cru", rk3288_clk_init);
 985
 986 static void __init rk3288w_clk_init(struct device_node *np)
 987 {
 988         rk3288_common_init(np, RK3288W_CRU);
 989 }
 990 CLK_OF_DECLARE(rk3288w_cru, "rockchip,rk3288w-cru", rk3288w_clk_init);