2 * Copyright 2014 Google, Inc
3 * Author: Alexandru M Stan <amstan@chromium.org>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/slab.h>
17 #include <linux/clk.h>
18 #include <linux/clk-provider.h>
20 #include <linux/kernel.h>
23 struct rockchip_mmc_clock {
30 #define to_mmc_clock(_hw) container_of(_hw, struct rockchip_mmc_clock, hw)
32 #define RK3288_MMC_CLKGEN_DIV 2
34 static unsigned long rockchip_mmc_recalc(struct clk_hw *hw,
35 unsigned long parent_rate)
37 return parent_rate / RK3288_MMC_CLKGEN_DIV;
40 #define ROCKCHIP_MMC_DELAY_SEL BIT(10)
41 #define ROCKCHIP_MMC_DEGREE_MASK 0x3
42 #define ROCKCHIP_MMC_DELAYNUM_OFFSET 2
43 #define ROCKCHIP_MMC_DELAYNUM_MASK (0xff << ROCKCHIP_MMC_DELAYNUM_OFFSET)
45 #define PSECS_PER_SEC 1000000000000LL
48 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
49 * simplify calculations. So 45degs could be anywhere between 33deg and 57.8deg.
51 #define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC 60
53 static int rockchip_mmc_get_phase(struct clk_hw *hw)
55 struct rockchip_mmc_clock *mmc_clock = to_mmc_clock(hw);
56 unsigned long rate = clk_get_rate(hw->clk);
61 /* See the comment for rockchip_mmc_set_phase below */
65 raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift);
67 degrees = (raw_value & ROCKCHIP_MMC_DEGREE_MASK) * 90;
69 if (raw_value & ROCKCHIP_MMC_DELAY_SEL) {
70 /* degrees/delaynum * 10000 */
71 unsigned long factor = (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10) *
72 36 * (rate / 1000000);
74 delay_num = (raw_value & ROCKCHIP_MMC_DELAYNUM_MASK);
75 delay_num >>= ROCKCHIP_MMC_DELAYNUM_OFFSET;
76 degrees += DIV_ROUND_CLOSEST(delay_num * factor, 10000);
82 static int rockchip_mmc_set_phase(struct clk_hw *hw, int degrees)
84 struct rockchip_mmc_clock *mmc_clock = to_mmc_clock(hw);
85 unsigned long rate = clk_get_rate(hw->clk);
86 u8 nineties, remainder;
92 * The below calculation is based on the output clock from
93 * MMC host to the card, which expects the phase clock inherits
94 * the clock rate from its parent, namely the output clock
95 * provider of MMC host. However, things may go wrong if
97 * (2) It is assigned to the wrong parent.
99 * This check help debug the case (1), which seems to be the
100 * most likely problem we often face and which makes it difficult
101 * for people to debug unstable mmc tuning results.
104 pr_err("%s: invalid clk rate\n", __func__);
108 nineties = degrees / 90;
109 remainder = (degrees % 90);
112 * Due to the inexact nature of the "fine" delay, we might
113 * actually go non-monotonic. We don't go _too_ monotonic
114 * though, so we should be OK. Here are options of how we may
117 * Ideally we end up with:
118 * 1.0, 2.0, ..., 69.0, 70.0, ..., 89.0, 90.0
120 * On one extreme (if delay is actually 44ps):
121 * .73, 1.5, ..., 50.6, 51.3, ..., 65.3, 90.0
122 * The other (if delay is actually 77ps):
123 * 1.3, 2.6, ..., 88.6. 89.8, ..., 114.0, 90
125 * It's possible we might make a delay that is up to 25
126 * degrees off from what we think we're making. That's OK
127 * though because we should be REALLY far from any bad range.
131 * Convert to delay; do a little extra work to make sure we
132 * don't overflow 32-bit / 64-bit numbers.
134 delay = 10000000; /* PSECS_PER_SEC / 10000 / 10 */
136 delay = DIV_ROUND_CLOSEST(delay,
138 (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10));
140 delay_num = (u8) min_t(u32, delay, 255);
142 raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0;
143 raw_value |= delay_num << ROCKCHIP_MMC_DELAYNUM_OFFSET;
144 raw_value |= nineties;
145 writel(HIWORD_UPDATE(raw_value, 0x07ff, mmc_clock->shift),
148 pr_debug("%s->set_phase(%d) delay_nums=%u reg[0x%p]=0x%03x actual_degrees=%d\n",
149 clk_hw_get_name(hw), degrees, delay_num,
150 mmc_clock->reg, raw_value>>(mmc_clock->shift),
151 rockchip_mmc_get_phase(hw)
157 static const struct clk_ops rockchip_mmc_clk_ops = {
158 .recalc_rate = rockchip_mmc_recalc,
159 .get_phase = rockchip_mmc_get_phase,
160 .set_phase = rockchip_mmc_set_phase,
163 struct clk *rockchip_clk_register_mmc(const char *name,
164 const char *const *parent_names, u8 num_parents,
165 void __iomem *reg, int shift)
167 struct clk_init_data init;
168 struct rockchip_mmc_clock *mmc_clock;
171 mmc_clock = kmalloc(sizeof(*mmc_clock), GFP_KERNEL);
173 return ERR_PTR(-ENOMEM);
177 init.num_parents = num_parents;
178 init.parent_names = parent_names;
179 init.ops = &rockchip_mmc_clk_ops;
181 mmc_clock->hw.init = &init;
182 mmc_clock->reg = reg;
183 mmc_clock->shift = shift;
185 clk = clk_register(NULL, &mmc_clock->hw);