1 // SPDX-License-Identifier: GPL-2.0
3 * RZ/G2L Clock Pulse Generator
5 * Copyright (C) 2021 Renesas Electronics Corp.
7 * Based on renesas-cpg-mssr.c
9 * Copyright (C) 2015 Glider bvba
10 * Copyright (C) 2013 Ideas On Board SPRL
11 * Copyright (C) 2015 Renesas Electronics Corp.
14 #include <linux/bitfield.h>
15 #include <linux/clk.h>
16 #include <linux/clk-provider.h>
17 #include <linux/clk/renesas.h>
18 #include <linux/delay.h>
19 #include <linux/device.h>
20 #include <linux/init.h>
21 #include <linux/iopoll.h>
22 #include <linux/mod_devicetable.h>
23 #include <linux/module.h>
25 #include <linux/platform_device.h>
26 #include <linux/pm_clock.h>
27 #include <linux/pm_domain.h>
28 #include <linux/reset-controller.h>
29 #include <linux/slab.h>
30 #include <linux/units.h>
32 #include <dt-bindings/clock/renesas-cpg-mssr.h>
34 #include "rzg2l-cpg.h"
37 #define WARN_DEBUG(x) WARN_ON(x)
39 #define WARN_DEBUG(x) do { } while (0)
42 #define GET_SHIFT(val) ((val >> 12) & 0xff)
43 #define GET_WIDTH(val) ((val >> 8) & 0xf)
45 #define KDIV(val) ((s16)FIELD_GET(GENMASK(31, 16), val))
46 #define MDIV(val) FIELD_GET(GENMASK(15, 6), val)
47 #define PDIV(val) FIELD_GET(GENMASK(5, 0), val)
48 #define SDIV(val) FIELD_GET(GENMASK(2, 0), val)
50 #define RZG3S_DIV_P GENMASK(28, 26)
51 #define RZG3S_DIV_M GENMASK(25, 22)
52 #define RZG3S_DIV_NI GENMASK(21, 13)
53 #define RZG3S_DIV_NF GENMASK(12, 1)
55 #define CLK_ON_R(reg) (reg)
56 #define CLK_MON_R(reg) (0x180 + (reg))
57 #define CLK_RST_R(reg) (reg)
58 #define CLK_MRST_R(reg) (0x180 + (reg))
60 #define GET_REG_OFFSET(val) ((val >> 20) & 0xfff)
61 #define GET_REG_SAMPLL_CLK1(val) ((val >> 22) & 0xfff)
62 #define GET_REG_SAMPLL_CLK2(val) ((val >> 12) & 0xfff)
64 #define CPG_WEN_BIT BIT(16)
66 #define MAX_VCLK_FREQ (148500000)
69 * struct clk_hw_data - clock hardware data
71 * @conf: clock configuration (register offset, shift, width)
72 * @sconf: clock status configuration (register offset, shift, width)
73 * @priv: CPG private data structure
79 struct rzg2l_cpg_priv *priv;
82 #define to_clk_hw_data(_hw) container_of(_hw, struct clk_hw_data, hw)
85 * struct sd_mux_hw_data - SD MUX clock hardware data
86 * @hw_data: clock hw data
87 * @mtable: clock mux table
89 struct sd_mux_hw_data {
90 struct clk_hw_data hw_data;
94 #define to_sd_mux_hw_data(_hw) container_of(_hw, struct sd_mux_hw_data, hw_data)
97 * struct div_hw_data - divider clock hardware data
98 * @hw_data: clock hw data
99 * @dtable: pointer to divider table
100 * @invalid_rate: invalid rate for divider
101 * @max_rate: maximum rate for divider
102 * @width: divider width
105 struct clk_hw_data hw_data;
106 const struct clk_div_table *dtable;
107 unsigned long invalid_rate;
108 unsigned long max_rate;
112 #define to_div_hw_data(_hw) container_of(_hw, struct div_hw_data, hw_data)
114 struct rzg2l_pll5_param {
123 struct rzg2l_pll5_mux_dsi_div_param {
130 * struct rzg2l_cpg_priv - Clock Pulse Generator Private Data
132 * @rcdev: Reset controller entity
134 * @base: CPG register block base address
135 * @rmw_lock: protects register accesses
136 * @clks: Array containing all Core and Module Clocks
137 * @num_core_clks: Number of Core Clocks in clks[]
138 * @num_mod_clks: Number of Module Clocks in clks[]
139 * @num_resets: Number of Module Resets in info->resets[]
140 * @last_dt_core_clk: ID of the last Core Clock exported to DT
141 * @info: Pointer to platform data
143 * @mux_dsi_div_params: pll5 mux and dsi div parameters
145 struct rzg2l_cpg_priv {
146 struct reset_controller_dev rcdev;
152 unsigned int num_core_clks;
153 unsigned int num_mod_clks;
154 unsigned int num_resets;
155 unsigned int last_dt_core_clk;
157 const struct rzg2l_cpg_info *info;
159 struct generic_pm_domain genpd;
161 struct rzg2l_pll5_mux_dsi_div_param mux_dsi_div_params;
164 static void rzg2l_cpg_del_clk_provider(void *data)
166 of_clk_del_provider(data);
169 /* Must be called in atomic context. */
170 static int rzg2l_cpg_wait_clk_update_done(void __iomem *base, u32 conf)
172 u32 bitmask = GENMASK(GET_WIDTH(conf) - 1, 0) << GET_SHIFT(conf);
173 u32 off = GET_REG_OFFSET(conf);
176 return readl_poll_timeout_atomic(base + off, val, !(val & bitmask), 10, 200);
179 int rzg2l_cpg_sd_clk_mux_notifier(struct notifier_block *nb, unsigned long event,
182 struct clk_notifier_data *cnd = data;
183 struct clk_hw *hw = __clk_get_hw(cnd->clk);
184 struct clk_hw_data *clk_hw_data = to_clk_hw_data(hw);
185 struct rzg2l_cpg_priv *priv = clk_hw_data->priv;
186 u32 off = GET_REG_OFFSET(clk_hw_data->conf);
187 u32 shift = GET_SHIFT(clk_hw_data->conf);
188 const u32 clk_src_266 = 3;
192 if (event != PRE_RATE_CHANGE || (cnd->new_rate / MEGA == 266))
195 spin_lock_irqsave(&priv->rmw_lock, flags);
198 * As per the HW manual, we should not directly switch from 533 MHz to
199 * 400 MHz and vice versa. To change the setting from 2’b01 (533 MHz)
200 * to 2’b10 (400 MHz) or vice versa, Switch to 2’b11 (266 MHz) first,
201 * and then switch to the target setting (2’b01 (533 MHz) or 2’b10
203 * Setting a value of '0' to the SEL_SDHI0_SET or SEL_SDHI1_SET clock
204 * switching register is prohibited.
205 * The clock mux has 3 input clocks(533 MHz, 400 MHz, and 266 MHz), and
206 * the index to value mapping is done by adding 1 to the index.
209 writel((CPG_WEN_BIT | clk_src_266) << shift, priv->base + off);
211 /* Wait for the update done. */
212 ret = rzg2l_cpg_wait_clk_update_done(priv->base, clk_hw_data->sconf);
214 spin_unlock_irqrestore(&priv->rmw_lock, flags);
217 dev_err(priv->dev, "failed to switch to safe clk source\n");
219 return notifier_from_errno(ret);
222 int rzg3s_cpg_div_clk_notifier(struct notifier_block *nb, unsigned long event,
225 struct clk_notifier_data *cnd = data;
226 struct clk_hw *hw = __clk_get_hw(cnd->clk);
227 struct clk_hw_data *clk_hw_data = to_clk_hw_data(hw);
228 struct div_hw_data *div_hw_data = to_div_hw_data(clk_hw_data);
229 struct rzg2l_cpg_priv *priv = clk_hw_data->priv;
230 u32 off = GET_REG_OFFSET(clk_hw_data->conf);
231 u32 shift = GET_SHIFT(clk_hw_data->conf);
236 if (event != PRE_RATE_CHANGE || !div_hw_data->invalid_rate ||
237 div_hw_data->invalid_rate % cnd->new_rate)
240 spin_lock_irqsave(&priv->rmw_lock, flags);
242 val = readl(priv->base + off);
244 val &= GENMASK(GET_WIDTH(clk_hw_data->conf) - 1, 0);
247 * There are different constraints for the user of this notifiers as follows:
248 * 1/ SD div cannot be 1 (val == 0) if parent rate is 800MHz
249 * 2/ OCTA / SPI div cannot be 1 (val == 0) if parent rate is 400MHz
250 * As SD can have only one parent having 800MHz and OCTA div can have
251 * only one parent having 400MHz we took into account the parent rate
252 * at the beginning of function (by checking invalid_rate % new_rate).
253 * Now it is time to check the hardware divider and update it accordingly.
256 writel((CPG_WEN_BIT | 1) << shift, priv->base + off);
257 /* Wait for the update done. */
258 ret = rzg2l_cpg_wait_clk_update_done(priv->base, clk_hw_data->sconf);
261 spin_unlock_irqrestore(&priv->rmw_lock, flags);
264 dev_err(priv->dev, "Failed to downgrade the div\n");
266 return notifier_from_errno(ret);
269 static int rzg2l_register_notifier(struct clk_hw *hw, const struct cpg_core_clk *core,
270 struct rzg2l_cpg_priv *priv)
272 struct notifier_block *nb;
277 nb = devm_kzalloc(priv->dev, sizeof(*nb), GFP_KERNEL);
281 nb->notifier_call = core->notifier;
283 return clk_notifier_register(hw->clk, nb);
286 static unsigned long rzg3s_div_clk_recalc_rate(struct clk_hw *hw,
287 unsigned long parent_rate)
289 struct clk_hw_data *clk_hw_data = to_clk_hw_data(hw);
290 struct div_hw_data *div_hw_data = to_div_hw_data(clk_hw_data);
291 struct rzg2l_cpg_priv *priv = clk_hw_data->priv;
294 val = readl(priv->base + GET_REG_OFFSET(clk_hw_data->conf));
295 val >>= GET_SHIFT(clk_hw_data->conf);
296 val &= GENMASK(GET_WIDTH(clk_hw_data->conf) - 1, 0);
298 return divider_recalc_rate(hw, parent_rate, val, div_hw_data->dtable,
299 CLK_DIVIDER_ROUND_CLOSEST, div_hw_data->width);
302 static int rzg3s_div_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
304 struct clk_hw_data *clk_hw_data = to_clk_hw_data(hw);
305 struct div_hw_data *div_hw_data = to_div_hw_data(clk_hw_data);
307 if (div_hw_data->max_rate && req->rate > div_hw_data->max_rate)
308 req->rate = div_hw_data->max_rate;
310 return divider_determine_rate(hw, req, div_hw_data->dtable, div_hw_data->width,
311 CLK_DIVIDER_ROUND_CLOSEST);
314 static int rzg3s_div_clk_set_rate(struct clk_hw *hw, unsigned long rate,
315 unsigned long parent_rate)
317 struct clk_hw_data *clk_hw_data = to_clk_hw_data(hw);
318 struct div_hw_data *div_hw_data = to_div_hw_data(clk_hw_data);
319 struct rzg2l_cpg_priv *priv = clk_hw_data->priv;
320 u32 off = GET_REG_OFFSET(clk_hw_data->conf);
321 u32 shift = GET_SHIFT(clk_hw_data->conf);
326 val = divider_get_val(rate, parent_rate, div_hw_data->dtable, div_hw_data->width,
327 CLK_DIVIDER_ROUND_CLOSEST);
329 spin_lock_irqsave(&priv->rmw_lock, flags);
330 writel((CPG_WEN_BIT | val) << shift, priv->base + off);
331 /* Wait for the update done. */
332 ret = rzg2l_cpg_wait_clk_update_done(priv->base, clk_hw_data->sconf);
333 spin_unlock_irqrestore(&priv->rmw_lock, flags);
338 static const struct clk_ops rzg3s_div_clk_ops = {
339 .recalc_rate = rzg3s_div_clk_recalc_rate,
340 .determine_rate = rzg3s_div_clk_determine_rate,
341 .set_rate = rzg3s_div_clk_set_rate,
344 static struct clk * __init
345 rzg3s_cpg_div_clk_register(const struct cpg_core_clk *core, struct clk **clks,
346 void __iomem *base, struct rzg2l_cpg_priv *priv)
348 struct div_hw_data *div_hw_data;
349 struct clk_init_data init = {};
350 const struct clk_div_table *clkt;
351 struct clk_hw *clk_hw;
352 const struct clk *parent;
353 const char *parent_name;
357 parent = clks[core->parent & 0xffff];
359 return ERR_CAST(parent);
361 parent_name = __clk_get_name(parent);
363 div_hw_data = devm_kzalloc(priv->dev, sizeof(*div_hw_data), GFP_KERNEL);
365 return ERR_PTR(-ENOMEM);
367 init.name = core->name;
368 init.flags = core->flag;
369 init.ops = &rzg3s_div_clk_ops;
370 init.parent_names = &parent_name;
371 init.num_parents = 1;
373 /* Get the maximum divider to retrieve div width. */
374 for (clkt = core->dtable; clkt->div; clkt++) {
379 div_hw_data->hw_data.priv = priv;
380 div_hw_data->hw_data.conf = core->conf;
381 div_hw_data->hw_data.sconf = core->sconf;
382 div_hw_data->dtable = core->dtable;
383 div_hw_data->invalid_rate = core->invalid_rate;
384 div_hw_data->max_rate = core->max_rate;
385 div_hw_data->width = fls(max) - 1;
387 clk_hw = &div_hw_data->hw_data.hw;
388 clk_hw->init = &init;
390 ret = devm_clk_hw_register(priv->dev, clk_hw);
394 ret = rzg2l_register_notifier(clk_hw, core, priv);
396 dev_err(priv->dev, "Failed to register notifier for %s\n",
404 static struct clk * __init
405 rzg2l_cpg_div_clk_register(const struct cpg_core_clk *core,
408 struct rzg2l_cpg_priv *priv)
410 struct device *dev = priv->dev;
411 const struct clk *parent;
412 const char *parent_name;
413 struct clk_hw *clk_hw;
415 parent = clks[core->parent & 0xffff];
417 return ERR_CAST(parent);
419 parent_name = __clk_get_name(parent);
422 clk_hw = clk_hw_register_divider_table(dev, core->name,
424 base + GET_REG_OFFSET(core->conf),
425 GET_SHIFT(core->conf),
426 GET_WIDTH(core->conf),
431 clk_hw = clk_hw_register_divider(dev, core->name,
433 base + GET_REG_OFFSET(core->conf),
434 GET_SHIFT(core->conf),
435 GET_WIDTH(core->conf),
436 core->flag, &priv->rmw_lock);
439 return ERR_CAST(clk_hw);
444 static struct clk * __init
445 rzg2l_cpg_mux_clk_register(const struct cpg_core_clk *core,
447 struct rzg2l_cpg_priv *priv)
449 const struct clk_hw *clk_hw;
451 clk_hw = devm_clk_hw_register_mux(priv->dev, core->name,
452 core->parent_names, core->num_parents,
454 base + GET_REG_OFFSET(core->conf),
455 GET_SHIFT(core->conf),
456 GET_WIDTH(core->conf),
457 core->mux_flags, &priv->rmw_lock);
459 return ERR_CAST(clk_hw);
464 static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index)
466 struct clk_hw_data *clk_hw_data = to_clk_hw_data(hw);
467 struct sd_mux_hw_data *sd_mux_hw_data = to_sd_mux_hw_data(clk_hw_data);
468 struct rzg2l_cpg_priv *priv = clk_hw_data->priv;
469 u32 off = GET_REG_OFFSET(clk_hw_data->conf);
470 u32 shift = GET_SHIFT(clk_hw_data->conf);
475 val = clk_mux_index_to_val(sd_mux_hw_data->mtable, CLK_MUX_ROUND_CLOSEST, index);
477 spin_lock_irqsave(&priv->rmw_lock, flags);
479 writel((CPG_WEN_BIT | val) << shift, priv->base + off);
481 /* Wait for the update done. */
482 ret = rzg2l_cpg_wait_clk_update_done(priv->base, clk_hw_data->sconf);
484 spin_unlock_irqrestore(&priv->rmw_lock, flags);
487 dev_err(priv->dev, "Failed to switch parent\n");
492 static u8 rzg2l_cpg_sd_clk_mux_get_parent(struct clk_hw *hw)
494 struct clk_hw_data *clk_hw_data = to_clk_hw_data(hw);
495 struct sd_mux_hw_data *sd_mux_hw_data = to_sd_mux_hw_data(clk_hw_data);
496 struct rzg2l_cpg_priv *priv = clk_hw_data->priv;
499 val = readl(priv->base + GET_REG_OFFSET(clk_hw_data->conf));
500 val >>= GET_SHIFT(clk_hw_data->conf);
501 val &= GENMASK(GET_WIDTH(clk_hw_data->conf) - 1, 0);
503 return clk_mux_val_to_index(hw, sd_mux_hw_data->mtable, CLK_MUX_ROUND_CLOSEST, val);
506 static const struct clk_ops rzg2l_cpg_sd_clk_mux_ops = {
507 .determine_rate = __clk_mux_determine_rate_closest,
508 .set_parent = rzg2l_cpg_sd_clk_mux_set_parent,
509 .get_parent = rzg2l_cpg_sd_clk_mux_get_parent,
512 static struct clk * __init
513 rzg2l_cpg_sd_mux_clk_register(const struct cpg_core_clk *core,
515 struct rzg2l_cpg_priv *priv)
517 struct sd_mux_hw_data *sd_mux_hw_data;
518 struct clk_init_data init;
519 struct clk_hw *clk_hw;
522 sd_mux_hw_data = devm_kzalloc(priv->dev, sizeof(*sd_mux_hw_data), GFP_KERNEL);
524 return ERR_PTR(-ENOMEM);
526 sd_mux_hw_data->hw_data.priv = priv;
527 sd_mux_hw_data->hw_data.conf = core->conf;
528 sd_mux_hw_data->hw_data.sconf = core->sconf;
529 sd_mux_hw_data->mtable = core->mtable;
531 init.name = core->name;
532 init.ops = &rzg2l_cpg_sd_clk_mux_ops;
533 init.flags = core->flag;
534 init.num_parents = core->num_parents;
535 init.parent_names = core->parent_names;
537 clk_hw = &sd_mux_hw_data->hw_data.hw;
538 clk_hw->init = &init;
540 ret = devm_clk_hw_register(priv->dev, clk_hw);
544 ret = rzg2l_register_notifier(clk_hw, core, priv);
546 dev_err(priv->dev, "Failed to register notifier for %s\n",
555 rzg2l_cpg_get_foutpostdiv_rate(struct rzg2l_pll5_param *params,
558 unsigned long foutpostdiv_rate;
560 params->pl5_intin = rate / MEGA;
561 params->pl5_fracin = div_u64(((u64)rate % MEGA) << 24, MEGA);
562 params->pl5_refdiv = 2;
563 params->pl5_postdiv1 = 1;
564 params->pl5_postdiv2 = 1;
565 params->pl5_spread = 0x16;
568 EXTAL_FREQ_IN_MEGA_HZ * MEGA / params->pl5_refdiv *
569 ((((params->pl5_intin << 24) + params->pl5_fracin)) >> 24) /
570 (params->pl5_postdiv1 * params->pl5_postdiv2);
572 return foutpostdiv_rate;
575 struct dsi_div_hw_data {
579 struct rzg2l_cpg_priv *priv;
582 #define to_dsi_div_hw_data(_hw) container_of(_hw, struct dsi_div_hw_data, hw)
584 static unsigned long rzg2l_cpg_dsi_div_recalc_rate(struct clk_hw *hw,
585 unsigned long parent_rate)
587 struct dsi_div_hw_data *dsi_div = to_dsi_div_hw_data(hw);
588 unsigned long rate = dsi_div->rate;
596 static unsigned long rzg2l_cpg_get_vclk_parent_rate(struct clk_hw *hw,
599 struct dsi_div_hw_data *dsi_div = to_dsi_div_hw_data(hw);
600 struct rzg2l_cpg_priv *priv = dsi_div->priv;
601 struct rzg2l_pll5_param params;
602 unsigned long parent_rate;
604 parent_rate = rzg2l_cpg_get_foutpostdiv_rate(¶ms, rate);
606 if (priv->mux_dsi_div_params.clksrc)
612 static int rzg2l_cpg_dsi_div_determine_rate(struct clk_hw *hw,
613 struct clk_rate_request *req)
615 if (req->rate > MAX_VCLK_FREQ)
616 req->rate = MAX_VCLK_FREQ;
618 req->best_parent_rate = rzg2l_cpg_get_vclk_parent_rate(hw, req->rate);
623 static int rzg2l_cpg_dsi_div_set_rate(struct clk_hw *hw,
625 unsigned long parent_rate)
627 struct dsi_div_hw_data *dsi_div = to_dsi_div_hw_data(hw);
628 struct rzg2l_cpg_priv *priv = dsi_div->priv;
631 * MUX -->DIV_DSI_{A,B} -->M3 -->VCLK
633 * Based on the dot clock, the DSI divider clock sets the divider value,
634 * calculates the pll parameters for generating FOUTPOSTDIV and the clk
635 * source for the MUX and propagates that info to the parents.
638 if (!rate || rate > MAX_VCLK_FREQ)
641 dsi_div->rate = rate;
642 writel(CPG_PL5_SDIV_DIV_DSI_A_WEN | CPG_PL5_SDIV_DIV_DSI_B_WEN |
643 (priv->mux_dsi_div_params.dsi_div_a << 0) |
644 (priv->mux_dsi_div_params.dsi_div_b << 8),
645 priv->base + CPG_PL5_SDIV);
650 static const struct clk_ops rzg2l_cpg_dsi_div_ops = {
651 .recalc_rate = rzg2l_cpg_dsi_div_recalc_rate,
652 .determine_rate = rzg2l_cpg_dsi_div_determine_rate,
653 .set_rate = rzg2l_cpg_dsi_div_set_rate,
656 static struct clk * __init
657 rzg2l_cpg_dsi_div_clk_register(const struct cpg_core_clk *core,
659 struct rzg2l_cpg_priv *priv)
661 struct dsi_div_hw_data *clk_hw_data;
662 const struct clk *parent;
663 const char *parent_name;
664 struct clk_init_data init;
665 struct clk_hw *clk_hw;
668 parent = clks[core->parent & 0xffff];
670 return ERR_CAST(parent);
672 clk_hw_data = devm_kzalloc(priv->dev, sizeof(*clk_hw_data), GFP_KERNEL);
674 return ERR_PTR(-ENOMEM);
676 clk_hw_data->priv = priv;
678 parent_name = __clk_get_name(parent);
679 init.name = core->name;
680 init.ops = &rzg2l_cpg_dsi_div_ops;
681 init.flags = CLK_SET_RATE_PARENT;
682 init.parent_names = &parent_name;
683 init.num_parents = 1;
685 clk_hw = &clk_hw_data->hw;
686 clk_hw->init = &init;
688 ret = devm_clk_hw_register(priv->dev, clk_hw);
695 struct pll5_mux_hw_data {
699 struct rzg2l_cpg_priv *priv;
702 #define to_pll5_mux_hw_data(_hw) container_of(_hw, struct pll5_mux_hw_data, hw)
704 static int rzg2l_cpg_pll5_4_clk_mux_determine_rate(struct clk_hw *hw,
705 struct clk_rate_request *req)
707 struct clk_hw *parent;
708 struct pll5_mux_hw_data *hwdata = to_pll5_mux_hw_data(hw);
709 struct rzg2l_cpg_priv *priv = hwdata->priv;
711 parent = clk_hw_get_parent_by_index(hw, priv->mux_dsi_div_params.clksrc);
712 req->best_parent_hw = parent;
713 req->best_parent_rate = req->rate;
718 static int rzg2l_cpg_pll5_4_clk_mux_set_parent(struct clk_hw *hw, u8 index)
720 struct pll5_mux_hw_data *hwdata = to_pll5_mux_hw_data(hw);
721 struct rzg2l_cpg_priv *priv = hwdata->priv;
725 * | | -->MUX -->DIV_DSIA_B -->M3 -->VCLK
728 * Based on the dot clock, the DSI divider clock calculates the parent
729 * rate and clk source for the MUX. It propagates that info to
730 * pll5_4_clk_mux which sets the clock source for DSI divider clock.
733 writel(CPG_OTHERFUNC1_REG_RES0_ON_WEN | index,
734 priv->base + CPG_OTHERFUNC1_REG);
739 static u8 rzg2l_cpg_pll5_4_clk_mux_get_parent(struct clk_hw *hw)
741 struct pll5_mux_hw_data *hwdata = to_pll5_mux_hw_data(hw);
742 struct rzg2l_cpg_priv *priv = hwdata->priv;
744 return readl(priv->base + GET_REG_OFFSET(hwdata->conf));
747 static const struct clk_ops rzg2l_cpg_pll5_4_clk_mux_ops = {
748 .determine_rate = rzg2l_cpg_pll5_4_clk_mux_determine_rate,
749 .set_parent = rzg2l_cpg_pll5_4_clk_mux_set_parent,
750 .get_parent = rzg2l_cpg_pll5_4_clk_mux_get_parent,
753 static struct clk * __init
754 rzg2l_cpg_pll5_4_mux_clk_register(const struct cpg_core_clk *core,
755 struct rzg2l_cpg_priv *priv)
757 struct pll5_mux_hw_data *clk_hw_data;
758 struct clk_init_data init;
759 struct clk_hw *clk_hw;
762 clk_hw_data = devm_kzalloc(priv->dev, sizeof(*clk_hw_data), GFP_KERNEL);
764 return ERR_PTR(-ENOMEM);
766 clk_hw_data->priv = priv;
767 clk_hw_data->conf = core->conf;
769 init.name = core->name;
770 init.ops = &rzg2l_cpg_pll5_4_clk_mux_ops;
771 init.flags = CLK_SET_RATE_PARENT;
772 init.num_parents = core->num_parents;
773 init.parent_names = core->parent_names;
775 clk_hw = &clk_hw_data->hw;
776 clk_hw->init = &init;
778 ret = devm_clk_hw_register(priv->dev, clk_hw);
788 unsigned long foutpostdiv_rate;
789 struct rzg2l_cpg_priv *priv;
792 #define to_sipll5(_hw) container_of(_hw, struct sipll5, hw)
794 static unsigned long rzg2l_cpg_get_vclk_rate(struct clk_hw *hw,
797 struct sipll5 *sipll5 = to_sipll5(hw);
798 struct rzg2l_cpg_priv *priv = sipll5->priv;
801 vclk = rate / ((1 << priv->mux_dsi_div_params.dsi_div_a) *
802 (priv->mux_dsi_div_params.dsi_div_b + 1));
804 if (priv->mux_dsi_div_params.clksrc)
810 static unsigned long rzg2l_cpg_sipll5_recalc_rate(struct clk_hw *hw,
811 unsigned long parent_rate)
813 struct sipll5 *sipll5 = to_sipll5(hw);
814 unsigned long pll5_rate = sipll5->foutpostdiv_rate;
817 pll5_rate = parent_rate;
822 static long rzg2l_cpg_sipll5_round_rate(struct clk_hw *hw,
824 unsigned long *parent_rate)
829 static int rzg2l_cpg_sipll5_set_rate(struct clk_hw *hw,
831 unsigned long parent_rate)
833 struct sipll5 *sipll5 = to_sipll5(hw);
834 struct rzg2l_cpg_priv *priv = sipll5->priv;
835 struct rzg2l_pll5_param params;
836 unsigned long vclk_rate;
841 * OSC --> PLL5 --> FOUTPOSTDIV-->|
842 * | | -->MUX -->DIV_DSIA_B -->M3 -->VCLK
845 * Based on the dot clock, the DSI divider clock calculates the parent
846 * rate and the pll5 parameters for generating FOUTPOSTDIV. It propagates
847 * that info to sipll5 which sets parameters for generating FOUTPOSTDIV.
849 * OSC --> PLL5 --> FOUTPOSTDIV
855 vclk_rate = rzg2l_cpg_get_vclk_rate(hw, rate);
856 sipll5->foutpostdiv_rate =
857 rzg2l_cpg_get_foutpostdiv_rate(¶ms, vclk_rate);
859 /* Put PLL5 into standby mode */
860 writel(CPG_SIPLL5_STBY_RESETB_WEN, priv->base + CPG_SIPLL5_STBY);
861 ret = readl_poll_timeout(priv->base + CPG_SIPLL5_MON, val,
862 !(val & CPG_SIPLL5_MON_PLL5_LOCK), 100, 250000);
864 dev_err(priv->dev, "failed to release pll5 lock");
868 /* Output clock setting 1 */
869 writel((params.pl5_postdiv1 << 0) | (params.pl5_postdiv2 << 4) |
870 (params.pl5_refdiv << 8), priv->base + CPG_SIPLL5_CLK1);
872 /* Output clock setting, SSCG modulation value setting 3 */
873 writel((params.pl5_fracin << 8), priv->base + CPG_SIPLL5_CLK3);
875 /* Output clock setting 4 */
876 writel(CPG_SIPLL5_CLK4_RESV_LSB | (params.pl5_intin << 16),
877 priv->base + CPG_SIPLL5_CLK4);
879 /* Output clock setting 5 */
880 writel(params.pl5_spread, priv->base + CPG_SIPLL5_CLK5);
882 /* PLL normal mode setting */
883 writel(CPG_SIPLL5_STBY_DOWNSPREAD_WEN | CPG_SIPLL5_STBY_SSCG_EN_WEN |
884 CPG_SIPLL5_STBY_RESETB_WEN | CPG_SIPLL5_STBY_RESETB,
885 priv->base + CPG_SIPLL5_STBY);
887 /* PLL normal mode transition, output clock stability check */
888 ret = readl_poll_timeout(priv->base + CPG_SIPLL5_MON, val,
889 (val & CPG_SIPLL5_MON_PLL5_LOCK), 100, 250000);
891 dev_err(priv->dev, "failed to lock pll5");
898 static const struct clk_ops rzg2l_cpg_sipll5_ops = {
899 .recalc_rate = rzg2l_cpg_sipll5_recalc_rate,
900 .round_rate = rzg2l_cpg_sipll5_round_rate,
901 .set_rate = rzg2l_cpg_sipll5_set_rate,
904 static struct clk * __init
905 rzg2l_cpg_sipll5_register(const struct cpg_core_clk *core,
907 struct rzg2l_cpg_priv *priv)
909 const struct clk *parent;
910 struct clk_init_data init;
911 const char *parent_name;
912 struct sipll5 *sipll5;
913 struct clk_hw *clk_hw;
916 parent = clks[core->parent & 0xffff];
918 return ERR_CAST(parent);
920 sipll5 = devm_kzalloc(priv->dev, sizeof(*sipll5), GFP_KERNEL);
922 return ERR_PTR(-ENOMEM);
924 init.name = core->name;
925 parent_name = __clk_get_name(parent);
926 init.ops = &rzg2l_cpg_sipll5_ops;
928 init.parent_names = &parent_name;
929 init.num_parents = 1;
931 sipll5->hw.init = &init;
932 sipll5->conf = core->conf;
935 writel(CPG_SIPLL5_STBY_SSCG_EN_WEN | CPG_SIPLL5_STBY_RESETB_WEN |
936 CPG_SIPLL5_STBY_RESETB, priv->base + CPG_SIPLL5_STBY);
938 clk_hw = &sipll5->hw;
939 clk_hw->init = &init;
941 ret = devm_clk_hw_register(priv->dev, clk_hw);
945 priv->mux_dsi_div_params.clksrc = 1; /* Use clk src 1 for DSI */
946 priv->mux_dsi_div_params.dsi_div_a = 1; /* Divided by 2 */
947 priv->mux_dsi_div_params.dsi_div_b = 2; /* Divided by 3 */
957 struct rzg2l_cpg_priv *priv;
960 #define to_pll(_hw) container_of(_hw, struct pll_clk, hw)
962 static unsigned long rzg2l_cpg_pll_clk_recalc_rate(struct clk_hw *hw,
963 unsigned long parent_rate)
965 struct pll_clk *pll_clk = to_pll(hw);
966 struct rzg2l_cpg_priv *priv = pll_clk->priv;
967 unsigned int val1, val2;
970 if (pll_clk->type != CLK_TYPE_SAM_PLL)
973 val1 = readl(priv->base + GET_REG_SAMPLL_CLK1(pll_clk->conf));
974 val2 = readl(priv->base + GET_REG_SAMPLL_CLK2(pll_clk->conf));
976 rate = mul_u64_u32_shr(parent_rate, (MDIV(val1) << 16) + KDIV(val1),
979 return DIV_ROUND_CLOSEST_ULL(rate, PDIV(val1));
982 static const struct clk_ops rzg2l_cpg_pll_ops = {
983 .recalc_rate = rzg2l_cpg_pll_clk_recalc_rate,
986 static unsigned long rzg3s_cpg_pll_clk_recalc_rate(struct clk_hw *hw,
987 unsigned long parent_rate)
989 struct pll_clk *pll_clk = to_pll(hw);
990 struct rzg2l_cpg_priv *priv = pll_clk->priv;
991 u32 nir, nfr, mr, pr, val;
994 if (pll_clk->type != CLK_TYPE_G3S_PLL)
997 val = readl(priv->base + GET_REG_SAMPLL_CLK1(pll_clk->conf));
999 pr = 1 << FIELD_GET(RZG3S_DIV_P, val);
1000 /* Hardware interprets values higher than 8 as p = 16. */
1004 mr = FIELD_GET(RZG3S_DIV_M, val) + 1;
1005 nir = FIELD_GET(RZG3S_DIV_NI, val) + 1;
1006 nfr = FIELD_GET(RZG3S_DIV_NF, val);
1008 rate = mul_u64_u32_shr(parent_rate, 4096 * nir + nfr, 12);
1010 return DIV_ROUND_CLOSEST_ULL(rate, (mr * pr));
1013 static const struct clk_ops rzg3s_cpg_pll_ops = {
1014 .recalc_rate = rzg3s_cpg_pll_clk_recalc_rate,
1017 static struct clk * __init
1018 rzg2l_cpg_pll_clk_register(const struct cpg_core_clk *core,
1021 struct rzg2l_cpg_priv *priv,
1022 const struct clk_ops *ops)
1024 struct device *dev = priv->dev;
1025 const struct clk *parent;
1026 struct clk_init_data init;
1027 const char *parent_name;
1028 struct pll_clk *pll_clk;
1030 parent = clks[core->parent & 0xffff];
1032 return ERR_CAST(parent);
1034 pll_clk = devm_kzalloc(dev, sizeof(*pll_clk), GFP_KERNEL);
1036 return ERR_PTR(-ENOMEM);
1038 parent_name = __clk_get_name(parent);
1039 init.name = core->name;
1042 init.parent_names = &parent_name;
1043 init.num_parents = 1;
1045 pll_clk->hw.init = &init;
1046 pll_clk->conf = core->conf;
1047 pll_clk->base = base;
1048 pll_clk->priv = priv;
1049 pll_clk->type = core->type;
1051 return clk_register(NULL, &pll_clk->hw);
1055 *rzg2l_cpg_clk_src_twocell_get(struct of_phandle_args *clkspec,
1058 unsigned int clkidx = clkspec->args[1];
1059 struct rzg2l_cpg_priv *priv = data;
1060 struct device *dev = priv->dev;
1064 switch (clkspec->args[0]) {
1067 if (clkidx > priv->last_dt_core_clk) {
1068 dev_err(dev, "Invalid %s clock index %u\n", type, clkidx);
1069 return ERR_PTR(-EINVAL);
1071 clk = priv->clks[clkidx];
1076 if (clkidx >= priv->num_mod_clks) {
1077 dev_err(dev, "Invalid %s clock index %u\n", type,
1079 return ERR_PTR(-EINVAL);
1081 clk = priv->clks[priv->num_core_clks + clkidx];
1085 dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]);
1086 return ERR_PTR(-EINVAL);
1090 dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx,
1093 dev_dbg(dev, "clock (%u, %u) is %pC at %lu Hz\n",
1094 clkspec->args[0], clkspec->args[1], clk,
1100 rzg2l_cpg_register_core_clk(const struct cpg_core_clk *core,
1101 const struct rzg2l_cpg_info *info,
1102 struct rzg2l_cpg_priv *priv)
1104 struct clk *clk = ERR_PTR(-EOPNOTSUPP), *parent;
1105 struct device *dev = priv->dev;
1106 unsigned int id = core->id, div = core->div;
1107 const char *parent_name;
1109 WARN_DEBUG(id >= priv->num_core_clks);
1110 WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
1113 /* Skip NULLified clock */
1117 switch (core->type) {
1119 clk = of_clk_get_by_name(priv->dev->of_node, core->name);
1122 WARN_DEBUG(core->parent >= priv->num_core_clks);
1123 parent = priv->clks[core->parent];
1124 if (IS_ERR(parent)) {
1129 parent_name = __clk_get_name(parent);
1130 clk = clk_register_fixed_factor(NULL, core->name,
1131 parent_name, CLK_SET_RATE_PARENT,
1134 case CLK_TYPE_SAM_PLL:
1135 clk = rzg2l_cpg_pll_clk_register(core, priv->clks, priv->base, priv,
1136 &rzg2l_cpg_pll_ops);
1138 case CLK_TYPE_G3S_PLL:
1139 clk = rzg2l_cpg_pll_clk_register(core, priv->clks, priv->base, priv,
1140 &rzg3s_cpg_pll_ops);
1142 case CLK_TYPE_SIPLL5:
1143 clk = rzg2l_cpg_sipll5_register(core, priv->clks, priv);
1146 clk = rzg2l_cpg_div_clk_register(core, priv->clks,
1149 case CLK_TYPE_G3S_DIV:
1150 clk = rzg3s_cpg_div_clk_register(core, priv->clks, priv->base, priv);
1153 clk = rzg2l_cpg_mux_clk_register(core, priv->base, priv);
1155 case CLK_TYPE_SD_MUX:
1156 clk = rzg2l_cpg_sd_mux_clk_register(core, priv->base, priv);
1158 case CLK_TYPE_PLL5_4_MUX:
1159 clk = rzg2l_cpg_pll5_4_mux_clk_register(core, priv);
1161 case CLK_TYPE_DSI_DIV:
1162 clk = rzg2l_cpg_dsi_div_clk_register(core, priv->clks, priv);
1168 if (IS_ERR_OR_NULL(clk))
1171 dev_dbg(dev, "Core clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
1172 priv->clks[id] = clk;
1176 dev_err(dev, "Failed to register %s clock %s: %ld\n", "core",
1177 core->name, PTR_ERR(clk));
1181 * struct mstp_clock - MSTP gating clock
1183 * @hw: handle between common and hardware-specific interfaces
1184 * @off: register offset
1186 * @enabled: soft state of the clock, if it is coupled with another clock
1187 * @priv: CPG/MSTP private data
1188 * @sibling: pointer to the other coupled clock
1195 struct rzg2l_cpg_priv *priv;
1196 struct mstp_clock *sibling;
1199 #define to_mod_clock(_hw) container_of(_hw, struct mstp_clock, hw)
1201 static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable)
1203 struct mstp_clock *clock = to_mod_clock(hw);
1204 struct rzg2l_cpg_priv *priv = clock->priv;
1205 unsigned int reg = clock->off;
1206 struct device *dev = priv->dev;
1207 u32 bitmask = BIT(clock->bit);
1212 dev_dbg(dev, "%pC does not support ON/OFF\n", hw->clk);
1216 dev_dbg(dev, "CLK_ON 0x%x/%pC %s\n", CLK_ON_R(reg), hw->clk,
1217 enable ? "ON" : "OFF");
1219 value = bitmask << 16;
1223 writel(value, priv->base + CLK_ON_R(reg));
1228 if (!priv->info->has_clk_mon_regs)
1231 error = readl_poll_timeout_atomic(priv->base + CLK_MON_R(reg), value,
1232 value & bitmask, 0, 10);
1234 dev_err(dev, "Failed to enable CLK_ON %p\n",
1235 priv->base + CLK_ON_R(reg));
1240 static int rzg2l_mod_clock_enable(struct clk_hw *hw)
1242 struct mstp_clock *clock = to_mod_clock(hw);
1244 if (clock->sibling) {
1245 struct rzg2l_cpg_priv *priv = clock->priv;
1246 unsigned long flags;
1249 spin_lock_irqsave(&priv->rmw_lock, flags);
1250 enabled = clock->sibling->enabled;
1251 clock->enabled = true;
1252 spin_unlock_irqrestore(&priv->rmw_lock, flags);
1257 return rzg2l_mod_clock_endisable(hw, true);
1260 static void rzg2l_mod_clock_disable(struct clk_hw *hw)
1262 struct mstp_clock *clock = to_mod_clock(hw);
1264 if (clock->sibling) {
1265 struct rzg2l_cpg_priv *priv = clock->priv;
1266 unsigned long flags;
1269 spin_lock_irqsave(&priv->rmw_lock, flags);
1270 enabled = clock->sibling->enabled;
1271 clock->enabled = false;
1272 spin_unlock_irqrestore(&priv->rmw_lock, flags);
1277 rzg2l_mod_clock_endisable(hw, false);
1280 static int rzg2l_mod_clock_is_enabled(struct clk_hw *hw)
1282 struct mstp_clock *clock = to_mod_clock(hw);
1283 struct rzg2l_cpg_priv *priv = clock->priv;
1284 u32 bitmask = BIT(clock->bit);
1288 dev_dbg(priv->dev, "%pC does not support ON/OFF\n", hw->clk);
1293 return clock->enabled;
1295 if (priv->info->has_clk_mon_regs)
1296 value = readl(priv->base + CLK_MON_R(clock->off));
1298 value = readl(priv->base + clock->off);
1300 return value & bitmask;
1303 static const struct clk_ops rzg2l_mod_clock_ops = {
1304 .enable = rzg2l_mod_clock_enable,
1305 .disable = rzg2l_mod_clock_disable,
1306 .is_enabled = rzg2l_mod_clock_is_enabled,
1309 static struct mstp_clock
1310 *rzg2l_mod_clock_get_sibling(struct mstp_clock *clock,
1311 struct rzg2l_cpg_priv *priv)
1316 for (i = 0; i < priv->num_mod_clks; i++) {
1317 struct mstp_clock *clk;
1319 if (priv->clks[priv->num_core_clks + i] == ERR_PTR(-ENOENT))
1322 hw = __clk_get_hw(priv->clks[priv->num_core_clks + i]);
1323 clk = to_mod_clock(hw);
1324 if (clock->off == clk->off && clock->bit == clk->bit)
1332 rzg2l_cpg_register_mod_clk(const struct rzg2l_mod_clk *mod,
1333 const struct rzg2l_cpg_info *info,
1334 struct rzg2l_cpg_priv *priv)
1336 struct mstp_clock *clock = NULL;
1337 struct device *dev = priv->dev;
1338 unsigned int id = mod->id;
1339 struct clk_init_data init;
1340 struct clk *parent, *clk;
1341 const char *parent_name;
1344 WARN_DEBUG(id < priv->num_core_clks);
1345 WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks);
1346 WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks);
1347 WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
1350 /* Skip NULLified clock */
1354 parent = priv->clks[mod->parent];
1355 if (IS_ERR(parent)) {
1360 clock = devm_kzalloc(dev, sizeof(*clock), GFP_KERNEL);
1362 clk = ERR_PTR(-ENOMEM);
1366 init.name = mod->name;
1367 init.ops = &rzg2l_mod_clock_ops;
1368 init.flags = CLK_SET_RATE_PARENT;
1369 for (i = 0; i < info->num_crit_mod_clks; i++)
1370 if (id == info->crit_mod_clks[i]) {
1371 dev_dbg(dev, "CPG %s setting CLK_IS_CRITICAL\n",
1373 init.flags |= CLK_IS_CRITICAL;
1377 parent_name = __clk_get_name(parent);
1378 init.parent_names = &parent_name;
1379 init.num_parents = 1;
1381 clock->off = mod->off;
1382 clock->bit = mod->bit;
1384 clock->hw.init = &init;
1386 clk = clk_register(NULL, &clock->hw);
1390 dev_dbg(dev, "Module clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
1391 priv->clks[id] = clk;
1393 if (mod->is_coupled) {
1394 struct mstp_clock *sibling;
1396 clock->enabled = rzg2l_mod_clock_is_enabled(&clock->hw);
1397 sibling = rzg2l_mod_clock_get_sibling(clock, priv);
1399 clock->sibling = sibling;
1400 sibling->sibling = clock;
1407 dev_err(dev, "Failed to register %s clock %s: %ld\n", "module",
1408 mod->name, PTR_ERR(clk));
1411 #define rcdev_to_priv(x) container_of(x, struct rzg2l_cpg_priv, rcdev)
1413 static int rzg2l_cpg_assert(struct reset_controller_dev *rcdev,
1416 struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
1417 const struct rzg2l_cpg_info *info = priv->info;
1418 unsigned int reg = info->resets[id].off;
1419 u32 mask = BIT(info->resets[id].bit);
1420 s8 monbit = info->resets[id].monbit;
1421 u32 value = mask << 16;
1423 dev_dbg(rcdev->dev, "assert id:%ld offset:0x%x\n", id, CLK_RST_R(reg));
1425 writel(value, priv->base + CLK_RST_R(reg));
1427 if (info->has_clk_mon_regs) {
1428 reg = CLK_MRST_R(reg);
1429 } else if (monbit >= 0) {
1433 /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */
1438 return readl_poll_timeout_atomic(priv->base + reg, value,
1439 value & mask, 10, 200);
1442 static int rzg2l_cpg_deassert(struct reset_controller_dev *rcdev,
1445 struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
1446 const struct rzg2l_cpg_info *info = priv->info;
1447 unsigned int reg = info->resets[id].off;
1448 u32 mask = BIT(info->resets[id].bit);
1449 s8 monbit = info->resets[id].monbit;
1450 u32 value = (mask << 16) | mask;
1452 dev_dbg(rcdev->dev, "deassert id:%ld offset:0x%x\n", id,
1455 writel(value, priv->base + CLK_RST_R(reg));
1457 if (info->has_clk_mon_regs) {
1458 reg = CLK_MRST_R(reg);
1459 } else if (monbit >= 0) {
1463 /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */
1468 return readl_poll_timeout_atomic(priv->base + reg, value,
1469 !(value & mask), 10, 200);
1472 static int rzg2l_cpg_reset(struct reset_controller_dev *rcdev,
1477 ret = rzg2l_cpg_assert(rcdev, id);
1481 return rzg2l_cpg_deassert(rcdev, id);
1484 static int rzg2l_cpg_status(struct reset_controller_dev *rcdev,
1487 struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
1488 const struct rzg2l_cpg_info *info = priv->info;
1489 s8 monbit = info->resets[id].monbit;
1493 if (info->has_clk_mon_regs) {
1494 reg = CLK_MRST_R(info->resets[id].off);
1495 bitmask = BIT(info->resets[id].bit);
1496 } else if (monbit >= 0) {
1498 bitmask = BIT(monbit);
1503 return !!(readl(priv->base + reg) & bitmask);
1506 static const struct reset_control_ops rzg2l_cpg_reset_ops = {
1507 .reset = rzg2l_cpg_reset,
1508 .assert = rzg2l_cpg_assert,
1509 .deassert = rzg2l_cpg_deassert,
1510 .status = rzg2l_cpg_status,
1513 static int rzg2l_cpg_reset_xlate(struct reset_controller_dev *rcdev,
1514 const struct of_phandle_args *reset_spec)
1516 struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
1517 const struct rzg2l_cpg_info *info = priv->info;
1518 unsigned int id = reset_spec->args[0];
1520 if (id >= rcdev->nr_resets || !info->resets[id].off) {
1521 dev_err(rcdev->dev, "Invalid reset index %u\n", id);
1528 static int rzg2l_cpg_reset_controller_register(struct rzg2l_cpg_priv *priv)
1530 priv->rcdev.ops = &rzg2l_cpg_reset_ops;
1531 priv->rcdev.of_node = priv->dev->of_node;
1532 priv->rcdev.dev = priv->dev;
1533 priv->rcdev.of_reset_n_cells = 1;
1534 priv->rcdev.of_xlate = rzg2l_cpg_reset_xlate;
1535 priv->rcdev.nr_resets = priv->num_resets;
1537 return devm_reset_controller_register(priv->dev, &priv->rcdev);
1540 static bool rzg2l_cpg_is_pm_clk(struct rzg2l_cpg_priv *priv,
1541 const struct of_phandle_args *clkspec)
1543 const struct rzg2l_cpg_info *info = priv->info;
1547 if (clkspec->args_count != 2)
1550 if (clkspec->args[0] != CPG_MOD)
1553 id = clkspec->args[1] + info->num_total_core_clks;
1554 for (i = 0; i < info->num_no_pm_mod_clks; i++) {
1555 if (info->no_pm_mod_clks[i] == id)
1562 static int rzg2l_cpg_attach_dev(struct generic_pm_domain *domain, struct device *dev)
1564 struct rzg2l_cpg_priv *priv = container_of(domain, struct rzg2l_cpg_priv, genpd);
1565 struct device_node *np = dev->of_node;
1566 struct of_phandle_args clkspec;
1572 while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
1574 if (rzg2l_cpg_is_pm_clk(priv, &clkspec)) {
1577 error = pm_clk_create(dev);
1579 of_node_put(clkspec.np);
1583 clk = of_clk_get_from_provider(&clkspec);
1584 of_node_put(clkspec.np);
1586 error = PTR_ERR(clk);
1590 error = pm_clk_add_clk(dev, clk);
1592 dev_err(dev, "pm_clk_add_clk failed %d\n",
1597 of_node_put(clkspec.np);
1608 pm_clk_destroy(dev);
1613 static void rzg2l_cpg_detach_dev(struct generic_pm_domain *unused, struct device *dev)
1615 if (!pm_clk_no_clocks(dev))
1616 pm_clk_destroy(dev);
1619 static void rzg2l_cpg_genpd_remove(void *data)
1621 pm_genpd_remove(data);
1624 static int __init rzg2l_cpg_add_clk_domain(struct rzg2l_cpg_priv *priv)
1626 struct device *dev = priv->dev;
1627 struct device_node *np = dev->of_node;
1628 struct generic_pm_domain *genpd = &priv->genpd;
1631 genpd->name = np->name;
1632 genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |
1633 GENPD_FLAG_ACTIVE_WAKEUP;
1634 genpd->attach_dev = rzg2l_cpg_attach_dev;
1635 genpd->detach_dev = rzg2l_cpg_detach_dev;
1636 ret = pm_genpd_init(genpd, &pm_domain_always_on_gov, false);
1640 ret = devm_add_action_or_reset(dev, rzg2l_cpg_genpd_remove, genpd);
1644 return of_genpd_add_provider_simple(np, genpd);
1647 static int __init rzg2l_cpg_probe(struct platform_device *pdev)
1649 struct device *dev = &pdev->dev;
1650 struct device_node *np = dev->of_node;
1651 const struct rzg2l_cpg_info *info;
1652 struct rzg2l_cpg_priv *priv;
1653 unsigned int nclks, i;
1657 info = of_device_get_match_data(dev);
1659 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1665 spin_lock_init(&priv->rmw_lock);
1667 priv->base = devm_platform_ioremap_resource(pdev, 0);
1668 if (IS_ERR(priv->base))
1669 return PTR_ERR(priv->base);
1671 nclks = info->num_total_core_clks + info->num_hw_mod_clks;
1672 clks = devm_kmalloc_array(dev, nclks, sizeof(*clks), GFP_KERNEL);
1676 dev_set_drvdata(dev, priv);
1678 priv->num_core_clks = info->num_total_core_clks;
1679 priv->num_mod_clks = info->num_hw_mod_clks;
1680 priv->num_resets = info->num_resets;
1681 priv->last_dt_core_clk = info->last_dt_core_clk;
1683 for (i = 0; i < nclks; i++)
1684 clks[i] = ERR_PTR(-ENOENT);
1686 for (i = 0; i < info->num_core_clks; i++)
1687 rzg2l_cpg_register_core_clk(&info->core_clks[i], info, priv);
1689 for (i = 0; i < info->num_mod_clks; i++)
1690 rzg2l_cpg_register_mod_clk(&info->mod_clks[i], info, priv);
1692 error = of_clk_add_provider(np, rzg2l_cpg_clk_src_twocell_get, priv);
1696 error = devm_add_action_or_reset(dev, rzg2l_cpg_del_clk_provider, np);
1700 error = rzg2l_cpg_add_clk_domain(priv);
1704 error = rzg2l_cpg_reset_controller_register(priv);
1711 static const struct of_device_id rzg2l_cpg_match[] = {
1712 #ifdef CONFIG_CLK_R9A07G043
1714 .compatible = "renesas,r9a07g043-cpg",
1715 .data = &r9a07g043_cpg_info,
1718 #ifdef CONFIG_CLK_R9A07G044
1720 .compatible = "renesas,r9a07g044-cpg",
1721 .data = &r9a07g044_cpg_info,
1724 #ifdef CONFIG_CLK_R9A07G054
1726 .compatible = "renesas,r9a07g054-cpg",
1727 .data = &r9a07g054_cpg_info,
1730 #ifdef CONFIG_CLK_R9A08G045
1732 .compatible = "renesas,r9a08g045-cpg",
1733 .data = &r9a08g045_cpg_info,
1736 #ifdef CONFIG_CLK_R9A09G011
1738 .compatible = "renesas,r9a09g011-cpg",
1739 .data = &r9a09g011_cpg_info,
1745 static struct platform_driver rzg2l_cpg_driver = {
1747 .name = "rzg2l-cpg",
1748 .of_match_table = rzg2l_cpg_match,
1752 static int __init rzg2l_cpg_init(void)
1754 return platform_driver_probe(&rzg2l_cpg_driver, rzg2l_cpg_probe);
1757 subsys_initcall(rzg2l_cpg_init);
1759 MODULE_DESCRIPTION("Renesas RZ/G2L CPG Driver");