1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas Clock Pulse Generator / Module Standby and Software Reset
5 * Copyright (C) 2015 Glider bvba
7 * Based on clk-mstp.c, clk-rcar-gen2.c, and clk-rcar-gen3.c
9 * Copyright (C) 2013 Ideas On Board SPRL
10 * Copyright (C) 2015 Renesas Electronics Corp.
13 #include <linux/clk.h>
14 #include <linux/clk-provider.h>
15 #include <linux/clk/renesas.h>
16 #include <linux/delay.h>
17 #include <linux/device.h>
18 #include <linux/init.h>
20 #include <linux/mod_devicetable.h>
21 #include <linux/module.h>
22 #include <linux/of_address.h>
23 #include <linux/of_device.h>
24 #include <linux/platform_device.h>
25 #include <linux/pm_clock.h>
26 #include <linux/pm_domain.h>
27 #include <linux/psci.h>
28 #include <linux/reset-controller.h>
29 #include <linux/slab.h>
31 #include <dt-bindings/clock/renesas-cpg-mssr.h>
33 #include "renesas-cpg-mssr.h"
37 #define WARN_DEBUG(x) WARN_ON(x)
39 #define WARN_DEBUG(x) do { } while (0)
44 * Module Standby and Software Reset register offets.
46 * If the registers exist, these are valid for SH-Mobile, R-Mobile,
47 * R-Car Gen2, R-Car Gen3, and RZ/G1.
48 * These are NOT valid for R-Car Gen1 and RZ/A1!
52 * Module Stop Status Register offsets
55 static const u16 mstpsr[] = {
56 0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4,
57 0x9A0, 0x9A4, 0x9A8, 0x9AC,
60 static const u16 mstpsr_for_v3u[] = {
61 0x2E00, 0x2E04, 0x2E08, 0x2E0C, 0x2E10, 0x2E14, 0x2E18, 0x2E1C,
62 0x2E20, 0x2E24, 0x2E28, 0x2E2C, 0x2E30, 0x2E34, 0x2E38,
66 * System Module Stop Control Register offsets
69 static const u16 smstpcr[] = {
70 0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C,
71 0x990, 0x994, 0x998, 0x99C,
74 static const u16 mstpcr_for_v3u[] = {
75 0x2D00, 0x2D04, 0x2D08, 0x2D0C, 0x2D10, 0x2D14, 0x2D18, 0x2D1C,
76 0x2D20, 0x2D24, 0x2D28, 0x2D2C, 0x2D30, 0x2D34, 0x2D38,
80 * Standby Control Register offsets (RZ/A)
81 * Base address is FRQCR register
84 static const u16 stbcr[] = {
85 0xFFFF/*dummy*/, 0x010, 0x014, 0x410, 0x414, 0x418, 0x41C, 0x420,
90 * Software Reset Register offsets
93 static const u16 srcr[] = {
94 0x0A0, 0x0A8, 0x0B0, 0x0B8, 0x0BC, 0x0C4, 0x1C8, 0x1CC,
95 0x920, 0x924, 0x928, 0x92C,
98 static const u16 srcr_for_v3u[] = {
99 0x2C00, 0x2C04, 0x2C08, 0x2C0C, 0x2C10, 0x2C14, 0x2C18, 0x2C1C,
100 0x2C20, 0x2C24, 0x2C28, 0x2C2C, 0x2C30, 0x2C34, 0x2C38,
103 /* Realtime Module Stop Control Register offsets */
104 #define RMSTPCR(i) (smstpcr[i] - 0x20)
106 /* Modem Module Stop Control Register offsets (r8a73a4) */
107 #define MMSTPCR(i) (smstpcr[i] + 0x20)
109 /* Software Reset Clearing Register offsets */
111 static const u16 srstclr[] = {
112 0x940, 0x944, 0x948, 0x94C, 0x950, 0x954, 0x958, 0x95C,
113 0x960, 0x964, 0x968, 0x96C,
116 static const u16 srstclr_for_v3u[] = {
117 0x2C80, 0x2C84, 0x2C88, 0x2C8C, 0x2C90, 0x2C94, 0x2C98, 0x2C9C,
118 0x2CA0, 0x2CA4, 0x2CA8, 0x2CAC, 0x2CB0, 0x2CB4, 0x2CB8,
122 * Clock Pulse Generator / Module Standby and Software Reset Private Data
124 * @rcdev: Optional reset controller entity
125 * @dev: CPG/MSSR device
126 * @base: CPG/MSSR register block base address
127 * @reg_layout: CPG/MSSR register layout
128 * @rmw_lock: protects RMW register accesses
129 * @np: Device node in DT for this CPG/MSSR module
130 * @num_core_clks: Number of Core Clocks in clks[]
131 * @num_mod_clks: Number of Module Clocks in clks[]
132 * @last_dt_core_clk: ID of the last Core Clock exported to DT
133 * @notifiers: Notifier chain to save/restore clock state for system resume
134 * @status_regs: Pointer to status registers array
135 * @control_regs: Pointer to control registers array
136 * @reset_regs: Pointer to reset registers array
137 * @reset_clear_regs: Pointer to reset clearing registers array
138 * @smstpcr_saved[].mask: Mask of SMSTPCR[] bits under our control
139 * @smstpcr_saved[].val: Saved values of SMSTPCR[]
140 * @clks: Array containing all Core and Module Clocks
142 struct cpg_mssr_priv {
143 #ifdef CONFIG_RESET_CONTROLLER
144 struct reset_controller_dev rcdev;
148 enum clk_reg_layout reg_layout;
150 struct device_node *np;
152 unsigned int num_core_clks;
153 unsigned int num_mod_clks;
154 unsigned int last_dt_core_clk;
156 struct raw_notifier_head notifiers;
157 const u16 *status_regs;
158 const u16 *control_regs;
159 const u16 *reset_regs;
160 const u16 *reset_clear_regs;
164 } smstpcr_saved[ARRAY_SIZE(mstpsr_for_v3u)];
169 static struct cpg_mssr_priv *cpg_mssr_priv;
172 * struct mstp_clock - MSTP gating clock
173 * @hw: handle between common and hardware-specific interfaces
174 * @index: MSTP clock number
175 * @priv: CPG/MSSR private data
180 struct cpg_mssr_priv *priv;
183 #define to_mstp_clock(_hw) container_of(_hw, struct mstp_clock, hw)
185 static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
187 struct mstp_clock *clock = to_mstp_clock(hw);
188 struct cpg_mssr_priv *priv = clock->priv;
189 unsigned int reg = clock->index / 32;
190 unsigned int bit = clock->index % 32;
191 struct device *dev = priv->dev;
192 u32 bitmask = BIT(bit);
197 dev_dbg(dev, "MSTP %u%02u/%pC %s\n", reg, bit, hw->clk,
198 enable ? "ON" : "OFF");
199 spin_lock_irqsave(&priv->rmw_lock, flags);
201 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
202 value = readb(priv->base + priv->control_regs[reg]);
207 writeb(value, priv->base + priv->control_regs[reg]);
209 /* dummy read to ensure write has completed */
210 readb(priv->base + priv->control_regs[reg]);
211 barrier_data(priv->base + priv->control_regs[reg]);
213 value = readl(priv->base + priv->control_regs[reg]);
218 writel(value, priv->base + priv->control_regs[reg]);
221 spin_unlock_irqrestore(&priv->rmw_lock, flags);
223 if (!enable || priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
226 for (i = 1000; i > 0; --i) {
227 if (!(readl(priv->base + priv->status_regs[reg]) & bitmask))
233 dev_err(dev, "Failed to enable SMSTP %p[%d]\n",
234 priv->base + priv->control_regs[reg], bit);
241 static int cpg_mstp_clock_enable(struct clk_hw *hw)
243 return cpg_mstp_clock_endisable(hw, true);
246 static void cpg_mstp_clock_disable(struct clk_hw *hw)
248 cpg_mstp_clock_endisable(hw, false);
251 static int cpg_mstp_clock_is_enabled(struct clk_hw *hw)
253 struct mstp_clock *clock = to_mstp_clock(hw);
254 struct cpg_mssr_priv *priv = clock->priv;
257 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
258 value = readb(priv->base + priv->control_regs[clock->index / 32]);
260 value = readl(priv->base + priv->status_regs[clock->index / 32]);
262 return !(value & BIT(clock->index % 32));
265 static const struct clk_ops cpg_mstp_clock_ops = {
266 .enable = cpg_mstp_clock_enable,
267 .disable = cpg_mstp_clock_disable,
268 .is_enabled = cpg_mstp_clock_is_enabled,
272 struct clk *cpg_mssr_clk_src_twocell_get(struct of_phandle_args *clkspec,
275 unsigned int clkidx = clkspec->args[1];
276 struct cpg_mssr_priv *priv = data;
277 struct device *dev = priv->dev;
283 switch (clkspec->args[0]) {
286 if (clkidx > priv->last_dt_core_clk) {
287 dev_err(dev, "Invalid %s clock index %u\n", type,
289 return ERR_PTR(-EINVAL);
291 clk = priv->clks[clkidx];
296 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
297 idx = MOD_CLK_PACK_10(clkidx);
298 range_check = 7 - (clkidx % 10);
300 idx = MOD_CLK_PACK(clkidx);
301 range_check = 31 - (clkidx % 100);
303 if (range_check < 0 || idx >= priv->num_mod_clks) {
304 dev_err(dev, "Invalid %s clock index %u\n", type,
306 return ERR_PTR(-EINVAL);
308 clk = priv->clks[priv->num_core_clks + idx];
312 dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]);
313 return ERR_PTR(-EINVAL);
317 dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx,
320 dev_dbg(dev, "clock (%u, %u) is %pC at %lu Hz\n",
321 clkspec->args[0], clkspec->args[1], clk,
326 static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core,
327 const struct cpg_mssr_info *info,
328 struct cpg_mssr_priv *priv)
330 struct clk *clk = ERR_PTR(-ENOTSUPP), *parent;
331 struct device *dev = priv->dev;
332 unsigned int id = core->id, div = core->div;
333 const char *parent_name;
335 WARN_DEBUG(id >= priv->num_core_clks);
336 WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
339 /* Skip NULLified clock */
343 switch (core->type) {
345 clk = of_clk_get_by_name(priv->np, core->name);
349 case CLK_TYPE_DIV6P1:
350 case CLK_TYPE_DIV6_RO:
351 WARN_DEBUG(core->parent >= priv->num_core_clks);
352 parent = priv->clks[core->parent];
353 if (IS_ERR(parent)) {
358 parent_name = __clk_get_name(parent);
360 if (core->type == CLK_TYPE_DIV6_RO)
361 /* Multiply with the DIV6 register value */
362 div *= (readl(priv->base + core->offset) & 0x3f) + 1;
364 if (core->type == CLK_TYPE_DIV6P1) {
365 clk = cpg_div6_register(core->name, 1, &parent_name,
366 priv->base + core->offset,
369 clk = clk_register_fixed_factor(NULL, core->name,
376 clk = clk_register_fixed_rate(NULL, core->name, NULL, 0,
381 if (info->cpg_clk_register)
382 clk = info->cpg_clk_register(dev, core, info,
383 priv->clks, priv->base,
386 dev_err(dev, "%s has unsupported core clock type %u\n",
387 core->name, core->type);
391 if (IS_ERR_OR_NULL(clk))
394 dev_dbg(dev, "Core clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
395 priv->clks[id] = clk;
399 dev_err(dev, "Failed to register %s clock %s: %ld\n", "core",
400 core->name, PTR_ERR(clk));
403 static void __init cpg_mssr_register_mod_clk(const struct mssr_mod_clk *mod,
404 const struct cpg_mssr_info *info,
405 struct cpg_mssr_priv *priv)
407 struct mstp_clock *clock = NULL;
408 struct device *dev = priv->dev;
409 unsigned int id = mod->id;
410 struct clk_init_data init;
411 struct clk *parent, *clk;
412 const char *parent_name;
415 WARN_DEBUG(id < priv->num_core_clks);
416 WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks);
417 WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks);
418 WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
421 /* Skip NULLified clock */
425 parent = priv->clks[mod->parent];
426 if (IS_ERR(parent)) {
431 clock = kzalloc(sizeof(*clock), GFP_KERNEL);
433 clk = ERR_PTR(-ENOMEM);
437 init.name = mod->name;
438 init.ops = &cpg_mstp_clock_ops;
439 init.flags = CLK_SET_RATE_PARENT;
440 parent_name = __clk_get_name(parent);
441 init.parent_names = &parent_name;
442 init.num_parents = 1;
444 clock->index = id - priv->num_core_clks;
446 clock->hw.init = &init;
448 for (i = 0; i < info->num_crit_mod_clks; i++)
449 if (id == info->crit_mod_clks[i] &&
450 cpg_mstp_clock_is_enabled(&clock->hw)) {
451 dev_dbg(dev, "MSTP %s setting CLK_IS_CRITICAL\n",
453 init.flags |= CLK_IS_CRITICAL;
457 clk = clk_register(NULL, &clock->hw);
461 dev_dbg(dev, "Module clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
462 priv->clks[id] = clk;
463 priv->smstpcr_saved[clock->index / 32].mask |= BIT(clock->index % 32);
467 dev_err(dev, "Failed to register %s clock %s: %ld\n", "module",
468 mod->name, PTR_ERR(clk));
472 struct cpg_mssr_clk_domain {
473 struct generic_pm_domain genpd;
474 unsigned int num_core_pm_clks;
475 unsigned int core_pm_clks[];
478 static struct cpg_mssr_clk_domain *cpg_mssr_clk_domain;
480 static bool cpg_mssr_is_pm_clk(const struct of_phandle_args *clkspec,
481 struct cpg_mssr_clk_domain *pd)
485 if (clkspec->np != pd->genpd.dev.of_node || clkspec->args_count != 2)
488 switch (clkspec->args[0]) {
490 for (i = 0; i < pd->num_core_pm_clks; i++)
491 if (clkspec->args[1] == pd->core_pm_clks[i])
503 int cpg_mssr_attach_dev(struct generic_pm_domain *unused, struct device *dev)
505 struct cpg_mssr_clk_domain *pd = cpg_mssr_clk_domain;
506 struct device_node *np = dev->of_node;
507 struct of_phandle_args clkspec;
513 dev_dbg(dev, "CPG/MSSR clock domain not yet available\n");
514 return -EPROBE_DEFER;
517 while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
519 if (cpg_mssr_is_pm_clk(&clkspec, pd))
522 of_node_put(clkspec.np);
529 clk = of_clk_get_from_provider(&clkspec);
530 of_node_put(clkspec.np);
535 error = pm_clk_create(dev);
539 error = pm_clk_add_clk(dev, clk);
552 void cpg_mssr_detach_dev(struct generic_pm_domain *unused, struct device *dev)
554 if (!pm_clk_no_clocks(dev))
558 static int __init cpg_mssr_add_clk_domain(struct device *dev,
559 const unsigned int *core_pm_clks,
560 unsigned int num_core_pm_clks)
562 struct device_node *np = dev->of_node;
563 struct generic_pm_domain *genpd;
564 struct cpg_mssr_clk_domain *pd;
565 size_t pm_size = num_core_pm_clks * sizeof(core_pm_clks[0]);
567 pd = devm_kzalloc(dev, sizeof(*pd) + pm_size, GFP_KERNEL);
571 pd->num_core_pm_clks = num_core_pm_clks;
572 memcpy(pd->core_pm_clks, core_pm_clks, pm_size);
575 genpd->name = np->name;
576 genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |
577 GENPD_FLAG_ACTIVE_WAKEUP;
578 genpd->attach_dev = cpg_mssr_attach_dev;
579 genpd->detach_dev = cpg_mssr_detach_dev;
580 pm_genpd_init(genpd, &pm_domain_always_on_gov, false);
581 cpg_mssr_clk_domain = pd;
583 of_genpd_add_provider_simple(np, genpd);
587 #ifdef CONFIG_RESET_CONTROLLER
589 #define rcdev_to_priv(x) container_of(x, struct cpg_mssr_priv, rcdev)
591 static int cpg_mssr_reset(struct reset_controller_dev *rcdev,
594 struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
595 unsigned int reg = id / 32;
596 unsigned int bit = id % 32;
597 u32 bitmask = BIT(bit);
599 dev_dbg(priv->dev, "reset %u%02u\n", reg, bit);
602 writel(bitmask, priv->base + priv->reset_regs[reg]);
604 /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */
607 /* Release module from reset state */
608 writel(bitmask, priv->base + priv->reset_clear_regs[reg]);
613 static int cpg_mssr_assert(struct reset_controller_dev *rcdev, unsigned long id)
615 struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
616 unsigned int reg = id / 32;
617 unsigned int bit = id % 32;
618 u32 bitmask = BIT(bit);
620 dev_dbg(priv->dev, "assert %u%02u\n", reg, bit);
622 writel(bitmask, priv->base + priv->reset_regs[reg]);
626 static int cpg_mssr_deassert(struct reset_controller_dev *rcdev,
629 struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
630 unsigned int reg = id / 32;
631 unsigned int bit = id % 32;
632 u32 bitmask = BIT(bit);
634 dev_dbg(priv->dev, "deassert %u%02u\n", reg, bit);
636 writel(bitmask, priv->base + priv->reset_clear_regs[reg]);
640 static int cpg_mssr_status(struct reset_controller_dev *rcdev,
643 struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
644 unsigned int reg = id / 32;
645 unsigned int bit = id % 32;
646 u32 bitmask = BIT(bit);
648 return !!(readl(priv->base + priv->reset_regs[reg]) & bitmask);
651 static const struct reset_control_ops cpg_mssr_reset_ops = {
652 .reset = cpg_mssr_reset,
653 .assert = cpg_mssr_assert,
654 .deassert = cpg_mssr_deassert,
655 .status = cpg_mssr_status,
658 static int cpg_mssr_reset_xlate(struct reset_controller_dev *rcdev,
659 const struct of_phandle_args *reset_spec)
661 struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
662 unsigned int unpacked = reset_spec->args[0];
663 unsigned int idx = MOD_CLK_PACK(unpacked);
665 if (unpacked % 100 > 31 || idx >= rcdev->nr_resets) {
666 dev_err(priv->dev, "Invalid reset index %u\n", unpacked);
673 static int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv)
675 priv->rcdev.ops = &cpg_mssr_reset_ops;
676 priv->rcdev.of_node = priv->dev->of_node;
677 priv->rcdev.of_reset_n_cells = 1;
678 priv->rcdev.of_xlate = cpg_mssr_reset_xlate;
679 priv->rcdev.nr_resets = priv->num_mod_clks;
680 return devm_reset_controller_register(priv->dev, &priv->rcdev);
683 #else /* !CONFIG_RESET_CONTROLLER */
684 static inline int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv)
688 #endif /* !CONFIG_RESET_CONTROLLER */
691 static const struct of_device_id cpg_mssr_match[] = {
692 #ifdef CONFIG_CLK_R7S9210
694 .compatible = "renesas,r7s9210-cpg-mssr",
695 .data = &r7s9210_cpg_mssr_info,
698 #ifdef CONFIG_CLK_R8A7742
700 .compatible = "renesas,r8a7742-cpg-mssr",
701 .data = &r8a7742_cpg_mssr_info,
704 #ifdef CONFIG_CLK_R8A7743
706 .compatible = "renesas,r8a7743-cpg-mssr",
707 .data = &r8a7743_cpg_mssr_info,
709 /* RZ/G1N is (almost) identical to RZ/G1M w.r.t. clocks. */
711 .compatible = "renesas,r8a7744-cpg-mssr",
712 .data = &r8a7743_cpg_mssr_info,
715 #ifdef CONFIG_CLK_R8A7745
717 .compatible = "renesas,r8a7745-cpg-mssr",
718 .data = &r8a7745_cpg_mssr_info,
721 #ifdef CONFIG_CLK_R8A77470
723 .compatible = "renesas,r8a77470-cpg-mssr",
724 .data = &r8a77470_cpg_mssr_info,
727 #ifdef CONFIG_CLK_R8A774A1
729 .compatible = "renesas,r8a774a1-cpg-mssr",
730 .data = &r8a774a1_cpg_mssr_info,
733 #ifdef CONFIG_CLK_R8A774B1
735 .compatible = "renesas,r8a774b1-cpg-mssr",
736 .data = &r8a774b1_cpg_mssr_info,
739 #ifdef CONFIG_CLK_R8A774C0
741 .compatible = "renesas,r8a774c0-cpg-mssr",
742 .data = &r8a774c0_cpg_mssr_info,
745 #ifdef CONFIG_CLK_R8A774E1
747 .compatible = "renesas,r8a774e1-cpg-mssr",
748 .data = &r8a774e1_cpg_mssr_info,
751 #ifdef CONFIG_CLK_R8A7790
753 .compatible = "renesas,r8a7790-cpg-mssr",
754 .data = &r8a7790_cpg_mssr_info,
757 #ifdef CONFIG_CLK_R8A7791
759 .compatible = "renesas,r8a7791-cpg-mssr",
760 .data = &r8a7791_cpg_mssr_info,
762 /* R-Car M2-N is (almost) identical to R-Car M2-W w.r.t. clocks. */
764 .compatible = "renesas,r8a7793-cpg-mssr",
765 .data = &r8a7791_cpg_mssr_info,
768 #ifdef CONFIG_CLK_R8A7792
770 .compatible = "renesas,r8a7792-cpg-mssr",
771 .data = &r8a7792_cpg_mssr_info,
774 #ifdef CONFIG_CLK_R8A7794
776 .compatible = "renesas,r8a7794-cpg-mssr",
777 .data = &r8a7794_cpg_mssr_info,
780 #ifdef CONFIG_CLK_R8A7795
782 .compatible = "renesas,r8a7795-cpg-mssr",
783 .data = &r8a7795_cpg_mssr_info,
786 #ifdef CONFIG_CLK_R8A77960
788 .compatible = "renesas,r8a7796-cpg-mssr",
789 .data = &r8a7796_cpg_mssr_info,
792 #ifdef CONFIG_CLK_R8A77961
794 .compatible = "renesas,r8a77961-cpg-mssr",
795 .data = &r8a7796_cpg_mssr_info,
798 #ifdef CONFIG_CLK_R8A77965
800 .compatible = "renesas,r8a77965-cpg-mssr",
801 .data = &r8a77965_cpg_mssr_info,
804 #ifdef CONFIG_CLK_R8A77970
806 .compatible = "renesas,r8a77970-cpg-mssr",
807 .data = &r8a77970_cpg_mssr_info,
810 #ifdef CONFIG_CLK_R8A77980
812 .compatible = "renesas,r8a77980-cpg-mssr",
813 .data = &r8a77980_cpg_mssr_info,
816 #ifdef CONFIG_CLK_R8A77990
818 .compatible = "renesas,r8a77990-cpg-mssr",
819 .data = &r8a77990_cpg_mssr_info,
822 #ifdef CONFIG_CLK_R8A77995
824 .compatible = "renesas,r8a77995-cpg-mssr",
825 .data = &r8a77995_cpg_mssr_info,
828 #ifdef CONFIG_CLK_R8A779A0
830 .compatible = "renesas,r8a779a0-cpg-mssr",
831 .data = &r8a779a0_cpg_mssr_info,
837 static void cpg_mssr_del_clk_provider(void *data)
839 of_clk_del_provider(data);
842 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM_PSCI_FW)
843 static int cpg_mssr_suspend_noirq(struct device *dev)
845 struct cpg_mssr_priv *priv = dev_get_drvdata(dev);
848 /* This is the best we can do to check for the presence of PSCI */
849 if (!psci_ops.cpu_suspend)
852 /* Save module registers with bits under our control */
853 for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) {
854 if (priv->smstpcr_saved[reg].mask)
855 priv->smstpcr_saved[reg].val =
856 priv->reg_layout == CLK_REG_LAYOUT_RZ_A ?
857 readb(priv->base + priv->control_regs[reg]) :
858 readl(priv->base + priv->control_regs[reg]);
861 /* Save core clocks */
862 raw_notifier_call_chain(&priv->notifiers, PM_EVENT_SUSPEND, NULL);
867 static int cpg_mssr_resume_noirq(struct device *dev)
869 struct cpg_mssr_priv *priv = dev_get_drvdata(dev);
871 u32 mask, oldval, newval;
873 /* This is the best we can do to check for the presence of PSCI */
874 if (!psci_ops.cpu_suspend)
877 /* Restore core clocks */
878 raw_notifier_call_chain(&priv->notifiers, PM_EVENT_RESUME, NULL);
880 /* Restore module clocks */
881 for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) {
882 mask = priv->smstpcr_saved[reg].mask;
886 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
887 oldval = readb(priv->base + priv->control_regs[reg]);
889 oldval = readl(priv->base + priv->control_regs[reg]);
890 newval = oldval & ~mask;
891 newval |= priv->smstpcr_saved[reg].val & mask;
892 if (newval == oldval)
895 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
896 writeb(newval, priv->base + priv->control_regs[reg]);
897 /* dummy read to ensure write has completed */
898 readb(priv->base + priv->control_regs[reg]);
899 barrier_data(priv->base + priv->control_regs[reg]);
902 writel(newval, priv->base + priv->control_regs[reg]);
904 /* Wait until enabled clocks are really enabled */
905 mask &= ~priv->smstpcr_saved[reg].val;
909 for (i = 1000; i > 0; --i) {
910 oldval = readl(priv->base + priv->status_regs[reg]);
911 if (!(oldval & mask))
917 dev_warn(dev, "Failed to enable %s%u[0x%x]\n",
918 priv->reg_layout == CLK_REG_LAYOUT_RZ_A ?
919 "STB" : "SMSTP", reg, oldval & mask);
925 static const struct dev_pm_ops cpg_mssr_pm = {
926 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(cpg_mssr_suspend_noirq,
927 cpg_mssr_resume_noirq)
929 #define DEV_PM_OPS &cpg_mssr_pm
931 #define DEV_PM_OPS NULL
932 #endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */
934 static int __init cpg_mssr_common_init(struct device *dev,
935 struct device_node *np,
936 const struct cpg_mssr_info *info)
938 struct cpg_mssr_priv *priv;
939 unsigned int nclks, i;
943 error = info->init(dev);
948 nclks = info->num_total_core_clks + info->num_hw_mod_clks;
949 priv = kzalloc(struct_size(priv, clks, nclks), GFP_KERNEL);
955 spin_lock_init(&priv->rmw_lock);
957 priv->base = of_iomap(np, 0);
963 cpg_mssr_priv = priv;
964 priv->num_core_clks = info->num_total_core_clks;
965 priv->num_mod_clks = info->num_hw_mod_clks;
966 priv->last_dt_core_clk = info->last_dt_core_clk;
967 RAW_INIT_NOTIFIER_HEAD(&priv->notifiers);
968 priv->reg_layout = info->reg_layout;
969 if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3) {
970 priv->status_regs = mstpsr;
971 priv->control_regs = smstpcr;
972 priv->reset_regs = srcr;
973 priv->reset_clear_regs = srstclr;
974 } else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
975 priv->control_regs = stbcr;
976 } else if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_V3U) {
977 priv->status_regs = mstpsr_for_v3u;
978 priv->control_regs = mstpcr_for_v3u;
979 priv->reset_regs = srcr_for_v3u;
980 priv->reset_clear_regs = srstclr_for_v3u;
986 for (i = 0; i < nclks; i++)
987 priv->clks[i] = ERR_PTR(-ENOENT);
989 error = of_clk_add_provider(np, cpg_mssr_clk_src_twocell_get, priv);
1003 void __init cpg_mssr_early_init(struct device_node *np,
1004 const struct cpg_mssr_info *info)
1009 error = cpg_mssr_common_init(NULL, np, info);
1013 for (i = 0; i < info->num_early_core_clks; i++)
1014 cpg_mssr_register_core_clk(&info->early_core_clks[i], info,
1017 for (i = 0; i < info->num_early_mod_clks; i++)
1018 cpg_mssr_register_mod_clk(&info->early_mod_clks[i], info,
1023 static int __init cpg_mssr_probe(struct platform_device *pdev)
1025 struct device *dev = &pdev->dev;
1026 struct device_node *np = dev->of_node;
1027 const struct cpg_mssr_info *info;
1028 struct cpg_mssr_priv *priv;
1032 info = of_device_get_match_data(dev);
1034 if (!cpg_mssr_priv) {
1035 error = cpg_mssr_common_init(dev, dev->of_node, info);
1040 priv = cpg_mssr_priv;
1042 dev_set_drvdata(dev, priv);
1044 for (i = 0; i < info->num_core_clks; i++)
1045 cpg_mssr_register_core_clk(&info->core_clks[i], info, priv);
1047 for (i = 0; i < info->num_mod_clks; i++)
1048 cpg_mssr_register_mod_clk(&info->mod_clks[i], info, priv);
1050 error = devm_add_action_or_reset(dev,
1051 cpg_mssr_del_clk_provider,
1056 error = cpg_mssr_add_clk_domain(dev, info->core_pm_clks,
1057 info->num_core_pm_clks);
1061 /* Reset Controller not supported for Standby Control SoCs */
1062 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
1065 error = cpg_mssr_reset_controller_register(priv);
1072 static struct platform_driver cpg_mssr_driver = {
1074 .name = "renesas-cpg-mssr",
1075 .of_match_table = cpg_mssr_match,
1080 static int __init cpg_mssr_init(void)
1082 return platform_driver_probe(&cpg_mssr_driver, cpg_mssr_probe);
1085 subsys_initcall(cpg_mssr_init);
1087 void __init cpg_core_nullify_range(struct cpg_core_clk *core_clks,
1088 unsigned int num_core_clks,
1089 unsigned int first_clk,
1090 unsigned int last_clk)
1094 for (i = 0; i < num_core_clks; i++)
1095 if (core_clks[i].id >= first_clk &&
1096 core_clks[i].id <= last_clk)
1097 core_clks[i].name = NULL;
1100 void __init mssr_mod_nullify(struct mssr_mod_clk *mod_clks,
1101 unsigned int num_mod_clks,
1102 const unsigned int *clks, unsigned int n)
1106 for (i = 0, j = 0; i < num_mod_clks && j < n; i++)
1107 if (mod_clks[i].id == clks[j]) {
1108 mod_clks[i].name = NULL;
1113 void __init mssr_mod_reparent(struct mssr_mod_clk *mod_clks,
1114 unsigned int num_mod_clks,
1115 const struct mssr_mod_reparent *clks,
1120 for (i = 0, j = 0; i < num_mod_clks && j < n; i++)
1121 if (mod_clks[i].id == clks[j].clk) {
1122 mod_clks[i].parent = clks[j].parent;
1127 MODULE_DESCRIPTION("Renesas CPG/MSSR Driver");
1128 MODULE_LICENSE("GPL v2");