drivers/clk/renesas/renesas-cpg-mssr.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Renesas Clock Pulse Generator / Module Standby and Software Reset
   4  *
   5  * Copyright (C) 2015 Glider bvba
   6  *
   7  * Based on clk-mstp.c, clk-rcar-gen2.c, and clk-rcar-gen3.c
   8  *
   9  * Copyright (C) 2013 Ideas On Board SPRL
  10  * Copyright (C) 2015 Renesas Electronics Corp.
  11  */
  12
  13 #include <linux/clk.h>
  14 #include <linux/clk-provider.h>
  15 #include <linux/clk/renesas.h>
  16 #include <linux/delay.h>
  17 #include <linux/device.h>
  18 #include <linux/init.h>
  19 #include <linux/io.h>
  20 #include <linux/iopoll.h>
  21 #include <linux/mod_devicetable.h>
  22 #include <linux/module.h>
  23 #include <linux/of_address.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/pm_clock.h>
  26 #include <linux/pm_domain.h>
  27 #include <linux/psci.h>
  28 #include <linux/reset-controller.h>
  29 #include <linux/slab.h>
  30
  31 #include <dt-bindings/clock/renesas-cpg-mssr.h>
  32
  33 #include "renesas-cpg-mssr.h"
  34 #include "clk-div6.h"
  35
  36 #ifdef DEBUG
  37 #define WARN_DEBUG(x)   WARN_ON(x)
  38 #else
  39 #define WARN_DEBUG(x)   do { } while (0)
  40 #endif
  41
  42
  43 /*
  44  * Module Standby and Software Reset register offets.
  45  *
  46  * If the registers exist, these are valid for SH-Mobile, R-Mobile,
  47  * R-Car Gen2, R-Car Gen3, and RZ/G1.
  48  * These are NOT valid for R-Car Gen1 and RZ/A1!
  49  */
  50
  51 /*
  52  * Module Stop Status Register offsets
  53  */
  54
  55 static const u16 mstpsr[] = {
  56         0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4,
  57         0x9A0, 0x9A4, 0x9A8, 0x9AC,
  58 };
  59
  60 static const u16 mstpsr_for_gen4[] = {
  61         0x2E00, 0x2E04, 0x2E08, 0x2E0C, 0x2E10, 0x2E14, 0x2E18, 0x2E1C,
  62         0x2E20, 0x2E24, 0x2E28, 0x2E2C, 0x2E30, 0x2E34, 0x2E38, 0x2E3C,
  63         0x2E40, 0x2E44, 0x2E48, 0x2E4C, 0x2E50, 0x2E54, 0x2E58, 0x2E5C,
  64         0x2E60, 0x2E64, 0x2E68, 0x2E6C, 0x2E70, 0x2E74,
  65 };
  66
  67 /*
  68  * System Module Stop Control Register offsets
  69  */
  70
  71 static const u16 smstpcr[] = {
  72         0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C,
  73         0x990, 0x994, 0x998, 0x99C,
  74 };
  75
  76 static const u16 mstpcr_for_gen4[] = {
  77         0x2D00, 0x2D04, 0x2D08, 0x2D0C, 0x2D10, 0x2D14, 0x2D18, 0x2D1C,
  78         0x2D20, 0x2D24, 0x2D28, 0x2D2C, 0x2D30, 0x2D34, 0x2D38, 0x2D3C,
  79         0x2D40, 0x2D44, 0x2D48, 0x2D4C, 0x2D50, 0x2D54, 0x2D58, 0x2D5C,
  80         0x2D60, 0x2D64, 0x2D68, 0x2D6C, 0x2D70, 0x2D74,
  81 };
  82
  83 /*
  84  * Standby Control Register offsets (RZ/A)
  85  * Base address is FRQCR register
  86  */
  87
  88 static const u16 stbcr[] = {
  89         0xFFFF/*dummy*/, 0x010, 0x014, 0x410, 0x414, 0x418, 0x41C, 0x420,
  90         0x424, 0x428, 0x42C,
  91 };
  92
  93 /*
  94  * Software Reset Register offsets
  95  */
  96
  97 static const u16 srcr[] = {
  98         0x0A0, 0x0A8, 0x0B0, 0x0B8, 0x0BC, 0x0C4, 0x1C8, 0x1CC,
  99         0x920, 0x924, 0x928, 0x92C,
 100 };
 101
 102 static const u16 srcr_for_gen4[] = {
 103         0x2C00, 0x2C04, 0x2C08, 0x2C0C, 0x2C10, 0x2C14, 0x2C18, 0x2C1C,
 104         0x2C20, 0x2C24, 0x2C28, 0x2C2C, 0x2C30, 0x2C34, 0x2C38, 0x2C3C,
 105         0x2C40, 0x2C44, 0x2C48, 0x2C4C, 0x2C50, 0x2C54, 0x2C58, 0x2C5C,
 106         0x2C60, 0x2C64, 0x2C68, 0x2C6C, 0x2C70, 0x2C74,
 107 };
 108
 109 /*
 110  * Software Reset Clearing Register offsets
 111  */
 112
 113 static const u16 srstclr[] = {
 114         0x940, 0x944, 0x948, 0x94C, 0x950, 0x954, 0x958, 0x95C,
 115         0x960, 0x964, 0x968, 0x96C,
 116 };
 117
 118 static const u16 srstclr_for_gen4[] = {
 119         0x2C80, 0x2C84, 0x2C88, 0x2C8C, 0x2C90, 0x2C94, 0x2C98, 0x2C9C,
 120         0x2CA0, 0x2CA4, 0x2CA8, 0x2CAC, 0x2CB0, 0x2CB4, 0x2CB8, 0x2CBC,
 121         0x2CC0, 0x2CC4, 0x2CC8, 0x2CCC, 0x2CD0, 0x2CD4, 0x2CD8, 0x2CDC,
 122         0x2CE0, 0x2CE4, 0x2CE8, 0x2CEC, 0x2CF0, 0x2CF4,
 123 };
 124
 125 /**
 126  * struct cpg_mssr_priv - Clock Pulse Generator / Module Standby
 127  *                        and Software Reset Private Data
 128  *
 129  * @rcdev: Optional reset controller entity
 130  * @dev: CPG/MSSR device
 131  * @base: CPG/MSSR register block base address
 132  * @reg_layout: CPG/MSSR register layout
 133  * @rmw_lock: protects RMW register accesses
 134  * @np: Device node in DT for this CPG/MSSR module
 135  * @num_core_clks: Number of Core Clocks in clks[]
 136  * @num_mod_clks: Number of Module Clocks in clks[]
 137  * @last_dt_core_clk: ID of the last Core Clock exported to DT
 138  * @notifiers: Notifier chain to save/restore clock state for system resume
 139  * @status_regs: Pointer to status registers array
 140  * @control_regs: Pointer to control registers array
 141  * @reset_regs: Pointer to reset registers array
 142  * @reset_clear_regs:  Pointer to reset clearing registers array
 143  * @smstpcr_saved: [].mask: Mask of SMSTPCR[] bits under our control
 144  *                 [].val: Saved values of SMSTPCR[]
 145  * @clks: Array containing all Core and Module Clocks
 146  */
 147 struct cpg_mssr_priv {
 148 #ifdef CONFIG_RESET_CONTROLLER
 149         struct reset_controller_dev rcdev;
 150 #endif
 151         struct device *dev;
 152         void __iomem *base;
 153         enum clk_reg_layout reg_layout;
 154         spinlock_t rmw_lock;
 155         struct device_node *np;
 156
 157         unsigned int num_core_clks;
 158         unsigned int num_mod_clks;
 159         unsigned int last_dt_core_clk;
 160
 161         struct raw_notifier_head notifiers;
 162         const u16 *status_regs;
 163         const u16 *control_regs;
 164         const u16 *reset_regs;
 165         const u16 *reset_clear_regs;
 166         struct {
 167                 u32 mask;
 168                 u32 val;
 169         } smstpcr_saved[ARRAY_SIZE(mstpsr_for_gen4)];
 170
 171         struct clk *clks[];
 172 };
 173
 174 static struct cpg_mssr_priv *cpg_mssr_priv;
 175
 176 /**
 177  * struct mstp_clock - MSTP gating clock
 178  * @hw: handle between common and hardware-specific interfaces
 179  * @index: MSTP clock number
 180  * @priv: CPG/MSSR private data
 181  */
 182 struct mstp_clock {
 183         struct clk_hw hw;
 184         u32 index;
 185         struct cpg_mssr_priv *priv;
 186 };
 187
 188 #define to_mstp_clock(_hw) container_of(_hw, struct mstp_clock, hw)
 189
 190 static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
 191 {
 192         struct mstp_clock *clock = to_mstp_clock(hw);
 193         struct cpg_mssr_priv *priv = clock->priv;
 194         unsigned int reg = clock->index / 32;
 195         unsigned int bit = clock->index % 32;
 196         struct device *dev = priv->dev;
 197         u32 bitmask = BIT(bit);
 198         unsigned long flags;
 199         u32 value;
 200         int error;
 201
 202         dev_dbg(dev, "MSTP %u%02u/%pC %s\n", reg, bit, hw->clk,
 203                 enable ? "ON" : "OFF");
 204         spin_lock_irqsave(&priv->rmw_lock, flags);
 205
 206         if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
 207                 value = readb(priv->base + priv->control_regs[reg]);
 208                 if (enable)
 209                         value &= ~bitmask;
 210                 else
 211                         value |= bitmask;
 212                 writeb(value, priv->base + priv->control_regs[reg]);
 213
 214                 /* dummy read to ensure write has completed */
 215                 readb(priv->base + priv->control_regs[reg]);
 216                 barrier_data(priv->base + priv->control_regs[reg]);
 217         } else {
 218                 value = readl(priv->base + priv->control_regs[reg]);
 219                 if (enable)
 220                         value &= ~bitmask;
 221                 else
 222                         value |= bitmask;
 223                 writel(value, priv->base + priv->control_regs[reg]);
 224         }
 225
 226         spin_unlock_irqrestore(&priv->rmw_lock, flags);
 227
 228         if (!enable || priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
 229                 return 0;
 230
 231         error = readl_poll_timeout_atomic(priv->base + priv->status_regs[reg],
 232                                           value, !(value & bitmask), 0, 10);
 233         if (error)
 234                 dev_err(dev, "Failed to enable SMSTP %p[%d]\n",
 235                         priv->base + priv->control_regs[reg], bit);
 236
 237         return error;
 238 }
 239
 240 static int cpg_mstp_clock_enable(struct clk_hw *hw)
 241 {
 242         return cpg_mstp_clock_endisable(hw, true);
 243 }
 244
 245 static void cpg_mstp_clock_disable(struct clk_hw *hw)
 246 {
 247         cpg_mstp_clock_endisable(hw, false);
 248 }
 249
 250 static int cpg_mstp_clock_is_enabled(struct clk_hw *hw)
 251 {
 252         struct mstp_clock *clock = to_mstp_clock(hw);
 253         struct cpg_mssr_priv *priv = clock->priv;
 254         u32 value;
 255
 256         if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
 257                 value = readb(priv->base + priv->control_regs[clock->index / 32]);
 258         else
 259                 value = readl(priv->base + priv->status_regs[clock->index / 32]);
 260
 261         return !(value & BIT(clock->index % 32));
 262 }
 263
 264 static const struct clk_ops cpg_mstp_clock_ops = {
 265         .enable = cpg_mstp_clock_enable,
 266         .disable = cpg_mstp_clock_disable,
 267         .is_enabled = cpg_mstp_clock_is_enabled,
 268 };
 269
 270 static
 271 struct clk *cpg_mssr_clk_src_twocell_get(struct of_phandle_args *clkspec,
 272                                          void *data)
 273 {
 274         unsigned int clkidx = clkspec->args[1];
 275         struct cpg_mssr_priv *priv = data;
 276         struct device *dev = priv->dev;
 277         unsigned int idx;
 278         const char *type;
 279         struct clk *clk;
 280         int range_check;
 281
 282         switch (clkspec->args[0]) {
 283         case CPG_CORE:
 284                 type = "core";
 285                 if (clkidx > priv->last_dt_core_clk) {
 286                         dev_err(dev, "Invalid %s clock index %u\n", type,
 287                                clkidx);
 288                         return ERR_PTR(-EINVAL);
 289                 }
 290                 clk = priv->clks[clkidx];
 291                 break;
 292
 293         case CPG_MOD:
 294                 type = "module";
 295                 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
 296                         idx = MOD_CLK_PACK_10(clkidx);
 297                         range_check = 7 - (clkidx % 10);
 298                 } else {
 299                         idx = MOD_CLK_PACK(clkidx);
 300                         range_check = 31 - (clkidx % 100);
 301                 }
 302                 if (range_check < 0 || idx >= priv->num_mod_clks) {
 303                         dev_err(dev, "Invalid %s clock index %u\n", type,
 304                                 clkidx);
 305                         return ERR_PTR(-EINVAL);
 306                 }
 307                 clk = priv->clks[priv->num_core_clks + idx];
 308                 break;
 309
 310         default:
 311                 dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]);
 312                 return ERR_PTR(-EINVAL);
 313         }
 314
 315         if (IS_ERR(clk))
 316                 dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx,
 317                        PTR_ERR(clk));
 318         else
 319                 dev_dbg(dev, "clock (%u, %u) is %pC at %lu Hz\n",
 320                         clkspec->args[0], clkspec->args[1], clk,
 321                         clk_get_rate(clk));
 322         return clk;
 323 }
 324
 325 static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core,
 326                                               const struct cpg_mssr_info *info,
 327                                               struct cpg_mssr_priv *priv)
 328 {
 329         struct clk *clk = ERR_PTR(-ENOTSUPP), *parent;
 330         struct device *dev = priv->dev;
 331         unsigned int id = core->id, div = core->div;
 332         const char *parent_name;
 333
 334         WARN_DEBUG(id >= priv->num_core_clks);
 335         WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
 336
 337         if (!core->name) {
 338                 /* Skip NULLified clock */
 339                 return;
 340         }
 341
 342         switch (core->type) {
 343         case CLK_TYPE_IN:
 344                 clk = of_clk_get_by_name(priv->np, core->name);
 345                 break;
 346
 347         case CLK_TYPE_FF:
 348         case CLK_TYPE_DIV6P1:
 349         case CLK_TYPE_DIV6_RO:
 350                 WARN_DEBUG(core->parent >= priv->num_core_clks);
 351                 parent = priv->clks[core->parent];
 352                 if (IS_ERR(parent)) {
 353                         clk = parent;
 354                         goto fail;
 355                 }
 356
 357                 parent_name = __clk_get_name(parent);
 358
 359                 if (core->type == CLK_TYPE_DIV6_RO)
 360                         /* Multiply with the DIV6 register value */
 361                         div *= (readl(priv->base + core->offset) & 0x3f) + 1;
 362
 363                 if (core->type == CLK_TYPE_DIV6P1) {
 364                         clk = cpg_div6_register(core->name, 1, &parent_name,
 365                                                 priv->base + core->offset,
 366                                                 &priv->notifiers);
 367                 } else {
 368                         clk = clk_register_fixed_factor(NULL, core->name,
 369                                                         parent_name, 0,
 370                                                         core->mult, div);
 371                 }
 372                 break;
 373
 374         case CLK_TYPE_FR:
 375                 clk = clk_register_fixed_rate(NULL, core->name, NULL, 0,
 376                                               core->mult);
 377                 break;
 378
 379         default:
 380                 if (info->cpg_clk_register)
 381                         clk = info->cpg_clk_register(dev, core, info,
 382                                                      priv->clks, priv->base,
 383                                                      &priv->notifiers);
 384                 else
 385                         dev_err(dev, "%s has unsupported core clock type %u\n",
 386                                 core->name, core->type);
 387                 break;
 388         }
 389
 390         if (IS_ERR_OR_NULL(clk))
 391                 goto fail;
 392
 393         dev_dbg(dev, "Core clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
 394         priv->clks[id] = clk;
 395         return;
 396
 397 fail:
 398         dev_err(dev, "Failed to register %s clock %s: %ld\n", "core",
 399                 core->name, PTR_ERR(clk));
 400 }
 401
 402 static void __init cpg_mssr_register_mod_clk(const struct mssr_mod_clk *mod,
 403                                              const struct cpg_mssr_info *info,
 404                                              struct cpg_mssr_priv *priv)
 405 {
 406         struct mstp_clock *clock = NULL;
 407         struct device *dev = priv->dev;
 408         unsigned int id = mod->id;
 409         struct clk_init_data init = {};
 410         struct clk *parent, *clk;
 411         const char *parent_name;
 412         unsigned int i;
 413
 414         WARN_DEBUG(id < priv->num_core_clks);
 415         WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks);
 416         WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks);
 417         WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
 418
 419         if (!mod->name) {
 420                 /* Skip NULLified clock */
 421                 return;
 422         }
 423
 424         parent = priv->clks[mod->parent];
 425         if (IS_ERR(parent)) {
 426                 clk = parent;
 427                 goto fail;
 428         }
 429
 430         clock = kzalloc(sizeof(*clock), GFP_KERNEL);
 431         if (!clock) {
 432                 clk = ERR_PTR(-ENOMEM);
 433                 goto fail;
 434         }
 435
 436         init.name = mod->name;
 437         init.ops = &cpg_mstp_clock_ops;
 438         init.flags = CLK_SET_RATE_PARENT;
 439         parent_name = __clk_get_name(parent);
 440         init.parent_names = &parent_name;
 441         init.num_parents = 1;
 442
 443         clock->index = id - priv->num_core_clks;
 444         clock->priv = priv;
 445         clock->hw.init = &init;
 446
 447         for (i = 0; i < info->num_crit_mod_clks; i++)
 448                 if (id == info->crit_mod_clks[i] &&
 449                     cpg_mstp_clock_is_enabled(&clock->hw)) {
 450                         dev_dbg(dev, "MSTP %s setting CLK_IS_CRITICAL\n",
 451                                 mod->name);
 452                         init.flags |= CLK_IS_CRITICAL;
 453                         break;
 454                 }
 455
 456         clk = clk_register(NULL, &clock->hw);
 457         if (IS_ERR(clk))
 458                 goto fail;
 459
 460         dev_dbg(dev, "Module clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
 461         priv->clks[id] = clk;
 462         priv->smstpcr_saved[clock->index / 32].mask |= BIT(clock->index % 32);
 463         return;
 464
 465 fail:
 466         dev_err(dev, "Failed to register %s clock %s: %ld\n", "module",
 467                 mod->name, PTR_ERR(clk));
 468         kfree(clock);
 469 }
 470
 471 struct cpg_mssr_clk_domain {
 472         struct generic_pm_domain genpd;
 473         unsigned int num_core_pm_clks;
 474         unsigned int core_pm_clks[];
 475 };
 476
 477 static struct cpg_mssr_clk_domain *cpg_mssr_clk_domain;
 478
 479 static bool cpg_mssr_is_pm_clk(const struct of_phandle_args *clkspec,
 480                                struct cpg_mssr_clk_domain *pd)
 481 {
 482         unsigned int i;
 483
 484         if (clkspec->np != pd->genpd.dev.of_node || clkspec->args_count != 2)
 485                 return false;
 486
 487         switch (clkspec->args[0]) {
 488         case CPG_CORE:
 489                 for (i = 0; i < pd->num_core_pm_clks; i++)
 490                         if (clkspec->args[1] == pd->core_pm_clks[i])
 491                                 return true;
 492                 return false;
 493
 494         case CPG_MOD:
 495                 return true;
 496
 497         default:
 498                 return false;
 499         }
 500 }
 501
 502 int cpg_mssr_attach_dev(struct generic_pm_domain *unused, struct device *dev)
 503 {
 504         struct cpg_mssr_clk_domain *pd = cpg_mssr_clk_domain;
 505         struct device_node *np = dev->of_node;
 506         struct of_phandle_args clkspec;
 507         struct clk *clk;
 508         int i = 0;
 509         int error;
 510
 511         if (!pd) {
 512                 dev_dbg(dev, "CPG/MSSR clock domain not yet available\n");
 513                 return -EPROBE_DEFER;
 514         }
 515
 516         while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
 517                                            &clkspec)) {
 518                 if (cpg_mssr_is_pm_clk(&clkspec, pd))
 519                         goto found;
 520
 521                 of_node_put(clkspec.np);
 522                 i++;
 523         }
 524
 525         return 0;
 526
 527 found:
 528         clk = of_clk_get_from_provider(&clkspec);
 529         of_node_put(clkspec.np);
 530
 531         if (IS_ERR(clk))
 532                 return PTR_ERR(clk);
 533
 534         error = pm_clk_create(dev);
 535         if (error)
 536                 goto fail_put;
 537
 538         error = pm_clk_add_clk(dev, clk);
 539         if (error)
 540                 goto fail_destroy;
 541
 542         return 0;
 543
 544 fail_destroy:
 545         pm_clk_destroy(dev);
 546 fail_put:
 547         clk_put(clk);
 548         return error;
 549 }
 550
 551 void cpg_mssr_detach_dev(struct generic_pm_domain *unused, struct device *dev)
 552 {
 553         if (!pm_clk_no_clocks(dev))
 554                 pm_clk_destroy(dev);
 555 }
 556
 557 static void cpg_mssr_genpd_remove(void *data)
 558 {
 559         pm_genpd_remove(data);
 560 }
 561
 562 static int __init cpg_mssr_add_clk_domain(struct device *dev,
 563                                           const unsigned int *core_pm_clks,
 564                                           unsigned int num_core_pm_clks)
 565 {
 566         struct device_node *np = dev->of_node;
 567         struct generic_pm_domain *genpd;
 568         struct cpg_mssr_clk_domain *pd;
 569         size_t pm_size = num_core_pm_clks * sizeof(core_pm_clks[0]);
 570         int ret;
 571
 572         pd = devm_kzalloc(dev, sizeof(*pd) + pm_size, GFP_KERNEL);
 573         if (!pd)
 574                 return -ENOMEM;
 575
 576         pd->num_core_pm_clks = num_core_pm_clks;
 577         memcpy(pd->core_pm_clks, core_pm_clks, pm_size);
 578
 579         genpd = &pd->genpd;
 580         genpd->name = np->name;
 581         genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |
 582                        GENPD_FLAG_ACTIVE_WAKEUP;
 583         genpd->attach_dev = cpg_mssr_attach_dev;
 584         genpd->detach_dev = cpg_mssr_detach_dev;
 585         ret = pm_genpd_init(genpd, &pm_domain_always_on_gov, false);
 586         if (ret)
 587                 return ret;
 588
 589         ret = devm_add_action_or_reset(dev, cpg_mssr_genpd_remove, genpd);
 590         if (ret)
 591                 return ret;
 592
 593         cpg_mssr_clk_domain = pd;
 594
 595         return of_genpd_add_provider_simple(np, genpd);
 596 }
 597
 598 #ifdef CONFIG_RESET_CONTROLLER
 599
 600 #define rcdev_to_priv(x)        container_of(x, struct cpg_mssr_priv, rcdev)
 601
 602 static int cpg_mssr_reset(struct reset_controller_dev *rcdev,
 603                           unsigned long id)
 604 {
 605         struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
 606         unsigned int reg = id / 32;
 607         unsigned int bit = id % 32;
 608         u32 bitmask = BIT(bit);
 609
 610         dev_dbg(priv->dev, "reset %u%02u\n", reg, bit);
 611
 612         /* Reset module */
 613         writel(bitmask, priv->base + priv->reset_regs[reg]);
 614
 615         /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */
 616         udelay(35);
 617
 618         /* Release module from reset state */
 619         writel(bitmask, priv->base + priv->reset_clear_regs[reg]);
 620
 621         return 0;
 622 }
 623
 624 static int cpg_mssr_assert(struct reset_controller_dev *rcdev, unsigned long id)
 625 {
 626         struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
 627         unsigned int reg = id / 32;
 628         unsigned int bit = id % 32;
 629         u32 bitmask = BIT(bit);
 630
 631         dev_dbg(priv->dev, "assert %u%02u\n", reg, bit);
 632
 633         writel(bitmask, priv->base + priv->reset_regs[reg]);
 634         return 0;
 635 }
 636
 637 static int cpg_mssr_deassert(struct reset_controller_dev *rcdev,
 638                              unsigned long id)
 639 {
 640         struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
 641         unsigned int reg = id / 32;
 642         unsigned int bit = id % 32;
 643         u32 bitmask = BIT(bit);
 644
 645         dev_dbg(priv->dev, "deassert %u%02u\n", reg, bit);
 646
 647         writel(bitmask, priv->base + priv->reset_clear_regs[reg]);
 648         return 0;
 649 }
 650
 651 static int cpg_mssr_status(struct reset_controller_dev *rcdev,
 652                            unsigned long id)
 653 {
 654         struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
 655         unsigned int reg = id / 32;
 656         unsigned int bit = id % 32;
 657         u32 bitmask = BIT(bit);
 658
 659         return !!(readl(priv->base + priv->reset_regs[reg]) & bitmask);
 660 }
 661
 662 static const struct reset_control_ops cpg_mssr_reset_ops = {
 663         .reset = cpg_mssr_reset,
 664         .assert = cpg_mssr_assert,
 665         .deassert = cpg_mssr_deassert,
 666         .status = cpg_mssr_status,
 667 };
 668
 669 static int cpg_mssr_reset_xlate(struct reset_controller_dev *rcdev,
 670                                 const struct of_phandle_args *reset_spec)
 671 {
 672         struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
 673         unsigned int unpacked = reset_spec->args[0];
 674         unsigned int idx = MOD_CLK_PACK(unpacked);
 675
 676         if (unpacked % 100 > 31 || idx >= rcdev->nr_resets) {
 677                 dev_err(priv->dev, "Invalid reset index %u\n", unpacked);
 678                 return -EINVAL;
 679         }
 680
 681         return idx;
 682 }
 683
 684 static int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv)
 685 {
 686         priv->rcdev.ops = &cpg_mssr_reset_ops;
 687         priv->rcdev.of_node = priv->dev->of_node;
 688         priv->rcdev.of_reset_n_cells = 1;
 689         priv->rcdev.of_xlate = cpg_mssr_reset_xlate;
 690         priv->rcdev.nr_resets = priv->num_mod_clks;
 691         return devm_reset_controller_register(priv->dev, &priv->rcdev);
 692 }
 693
 694 #else /* !CONFIG_RESET_CONTROLLER */
 695 static inline int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv)
 696 {
 697         return 0;
 698 }
 699 #endif /* !CONFIG_RESET_CONTROLLER */
 700
 701
 702 static const struct of_device_id cpg_mssr_match[] = {
 703 #ifdef CONFIG_CLK_R7S9210
 704         {
 705                 .compatible = "renesas,r7s9210-cpg-mssr",
 706                 .data = &r7s9210_cpg_mssr_info,
 707         },
 708 #endif
 709 #ifdef CONFIG_CLK_R8A7742
 710         {
 711                 .compatible = "renesas,r8a7742-cpg-mssr",
 712                 .data = &r8a7742_cpg_mssr_info,
 713         },
 714 #endif
 715 #ifdef CONFIG_CLK_R8A7743
 716         {
 717                 .compatible = "renesas,r8a7743-cpg-mssr",
 718                 .data = &r8a7743_cpg_mssr_info,
 719         },
 720         /* RZ/G1N is (almost) identical to RZ/G1M w.r.t. clocks. */
 721         {
 722                 .compatible = "renesas,r8a7744-cpg-mssr",
 723                 .data = &r8a7743_cpg_mssr_info,
 724         },
 725 #endif
 726 #ifdef CONFIG_CLK_R8A7745
 727         {
 728                 .compatible = "renesas,r8a7745-cpg-mssr",
 729                 .data = &r8a7745_cpg_mssr_info,
 730         },
 731 #endif
 732 #ifdef CONFIG_CLK_R8A77470
 733         {
 734                 .compatible = "renesas,r8a77470-cpg-mssr",
 735                 .data = &r8a77470_cpg_mssr_info,
 736         },
 737 #endif
 738 #ifdef CONFIG_CLK_R8A774A1
 739         {
 740                 .compatible = "renesas,r8a774a1-cpg-mssr",
 741                 .data = &r8a774a1_cpg_mssr_info,
 742         },
 743 #endif
 744 #ifdef CONFIG_CLK_R8A774B1
 745         {
 746                 .compatible = "renesas,r8a774b1-cpg-mssr",
 747                 .data = &r8a774b1_cpg_mssr_info,
 748         },
 749 #endif
 750 #ifdef CONFIG_CLK_R8A774C0
 751         {
 752                 .compatible = "renesas,r8a774c0-cpg-mssr",
 753                 .data = &r8a774c0_cpg_mssr_info,
 754         },
 755 #endif
 756 #ifdef CONFIG_CLK_R8A774E1
 757         {
 758                 .compatible = "renesas,r8a774e1-cpg-mssr",
 759                 .data = &r8a774e1_cpg_mssr_info,
 760         },
 761 #endif
 762 #ifdef CONFIG_CLK_R8A7790
 763         {
 764                 .compatible = "renesas,r8a7790-cpg-mssr",
 765                 .data = &r8a7790_cpg_mssr_info,
 766         },
 767 #endif
 768 #ifdef CONFIG_CLK_R8A7791
 769         {
 770                 .compatible = "renesas,r8a7791-cpg-mssr",
 771                 .data = &r8a7791_cpg_mssr_info,
 772         },
 773         /* R-Car M2-N is (almost) identical to R-Car M2-W w.r.t. clocks. */
 774         {
 775                 .compatible = "renesas,r8a7793-cpg-mssr",
 776                 .data = &r8a7791_cpg_mssr_info,
 777         },
 778 #endif
 779 #ifdef CONFIG_CLK_R8A7792
 780         {
 781                 .compatible = "renesas,r8a7792-cpg-mssr",
 782                 .data = &r8a7792_cpg_mssr_info,
 783         },
 784 #endif
 785 #ifdef CONFIG_CLK_R8A7794
 786         {
 787                 .compatible = "renesas,r8a7794-cpg-mssr",
 788                 .data = &r8a7794_cpg_mssr_info,
 789         },
 790 #endif
 791 #ifdef CONFIG_CLK_R8A7795
 792         {
 793                 .compatible = "renesas,r8a7795-cpg-mssr",
 794                 .data = &r8a7795_cpg_mssr_info,
 795         },
 796 #endif
 797 #ifdef CONFIG_CLK_R8A77960
 798         {
 799                 .compatible = "renesas,r8a7796-cpg-mssr",
 800                 .data = &r8a7796_cpg_mssr_info,
 801         },
 802 #endif
 803 #ifdef CONFIG_CLK_R8A77961
 804         {
 805                 .compatible = "renesas,r8a77961-cpg-mssr",
 806                 .data = &r8a7796_cpg_mssr_info,
 807         },
 808 #endif
 809 #ifdef CONFIG_CLK_R8A77965
 810         {
 811                 .compatible = "renesas,r8a77965-cpg-mssr",
 812                 .data = &r8a77965_cpg_mssr_info,
 813         },
 814 #endif
 815 #ifdef CONFIG_CLK_R8A77970
 816         {
 817                 .compatible = "renesas,r8a77970-cpg-mssr",
 818                 .data = &r8a77970_cpg_mssr_info,
 819         },
 820 #endif
 821 #ifdef CONFIG_CLK_R8A77980
 822         {
 823                 .compatible = "renesas,r8a77980-cpg-mssr",
 824                 .data = &r8a77980_cpg_mssr_info,
 825         },
 826 #endif
 827 #ifdef CONFIG_CLK_R8A77990
 828         {
 829                 .compatible = "renesas,r8a77990-cpg-mssr",
 830                 .data = &r8a77990_cpg_mssr_info,
 831         },
 832 #endif
 833 #ifdef CONFIG_CLK_R8A77995
 834         {
 835                 .compatible = "renesas,r8a77995-cpg-mssr",
 836                 .data = &r8a77995_cpg_mssr_info,
 837         },
 838 #endif
 839 #ifdef CONFIG_CLK_R8A779A0
 840         {
 841                 .compatible = "renesas,r8a779a0-cpg-mssr",
 842                 .data = &r8a779a0_cpg_mssr_info,
 843         },
 844 #endif
 845 #ifdef CONFIG_CLK_R8A779F0
 846         {
 847                 .compatible = "renesas,r8a779f0-cpg-mssr",
 848                 .data = &r8a779f0_cpg_mssr_info,
 849         },
 850 #endif
 851 #ifdef CONFIG_CLK_R8A779G0
 852         {
 853                 .compatible = "renesas,r8a779g0-cpg-mssr",
 854                 .data = &r8a779g0_cpg_mssr_info,
 855         },
 856 #endif
 857         { /* sentinel */ }
 858 };
 859
 860 static void cpg_mssr_del_clk_provider(void *data)
 861 {
 862         of_clk_del_provider(data);
 863 }
 864
 865 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM_PSCI_FW)
 866 static int cpg_mssr_suspend_noirq(struct device *dev)
 867 {
 868         struct cpg_mssr_priv *priv = dev_get_drvdata(dev);
 869         unsigned int reg;
 870
 871         /* This is the best we can do to check for the presence of PSCI */
 872         if (!psci_ops.cpu_suspend)
 873                 return 0;
 874
 875         /* Save module registers with bits under our control */
 876         for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) {
 877                 if (priv->smstpcr_saved[reg].mask)
 878                         priv->smstpcr_saved[reg].val =
 879                                 priv->reg_layout == CLK_REG_LAYOUT_RZ_A ?
 880                                 readb(priv->base + priv->control_regs[reg]) :
 881                                 readl(priv->base + priv->control_regs[reg]);
 882         }
 883
 884         /* Save core clocks */
 885         raw_notifier_call_chain(&priv->notifiers, PM_EVENT_SUSPEND, NULL);
 886
 887         return 0;
 888 }
 889
 890 static int cpg_mssr_resume_noirq(struct device *dev)
 891 {
 892         struct cpg_mssr_priv *priv = dev_get_drvdata(dev);
 893         unsigned int reg;
 894         u32 mask, oldval, newval;
 895         int error;
 896
 897         /* This is the best we can do to check for the presence of PSCI */
 898         if (!psci_ops.cpu_suspend)
 899                 return 0;
 900
 901         /* Restore core clocks */
 902         raw_notifier_call_chain(&priv->notifiers, PM_EVENT_RESUME, NULL);
 903
 904         /* Restore module clocks */
 905         for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) {
 906                 mask = priv->smstpcr_saved[reg].mask;
 907                 if (!mask)
 908                         continue;
 909
 910                 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
 911                         oldval = readb(priv->base + priv->control_regs[reg]);
 912                 else
 913                         oldval = readl(priv->base + priv->control_regs[reg]);
 914                 newval = oldval & ~mask;
 915                 newval |= priv->smstpcr_saved[reg].val & mask;
 916                 if (newval == oldval)
 917                         continue;
 918
 919                 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
 920                         writeb(newval, priv->base + priv->control_regs[reg]);
 921                         /* dummy read to ensure write has completed */
 922                         readb(priv->base + priv->control_regs[reg]);
 923                         barrier_data(priv->base + priv->control_regs[reg]);
 924                         continue;
 925                 } else
 926                         writel(newval, priv->base + priv->control_regs[reg]);
 927
 928                 /* Wait until enabled clocks are really enabled */
 929                 mask &= ~priv->smstpcr_saved[reg].val;
 930                 if (!mask)
 931                         continue;
 932
 933                 error = readl_poll_timeout_atomic(priv->base + priv->status_regs[reg],
 934                                                 oldval, !(oldval & mask), 0, 10);
 935                 if (error)
 936                         dev_warn(dev, "Failed to enable SMSTP%u[0x%x]\n", reg,
 937                                  oldval & mask);
 938         }
 939
 940         return 0;
 941 }
 942
 943 static const struct dev_pm_ops cpg_mssr_pm = {
 944         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(cpg_mssr_suspend_noirq,
 945                                       cpg_mssr_resume_noirq)
 946 };
 947 #define DEV_PM_OPS      &cpg_mssr_pm
 948 #else
 949 #define DEV_PM_OPS      NULL
 950 #endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */
 951
 952 static int __init cpg_mssr_common_init(struct device *dev,
 953                                        struct device_node *np,
 954                                        const struct cpg_mssr_info *info)
 955 {
 956         struct cpg_mssr_priv *priv;
 957         unsigned int nclks, i;
 958         int error;
 959
 960         if (info->init) {
 961                 error = info->init(dev);
 962                 if (error)
 963                         return error;
 964         }
 965
 966         nclks = info->num_total_core_clks + info->num_hw_mod_clks;
 967         priv = kzalloc(struct_size(priv, clks, nclks), GFP_KERNEL);
 968         if (!priv)
 969                 return -ENOMEM;
 970
 971         priv->np = np;
 972         priv->dev = dev;
 973         spin_lock_init(&priv->rmw_lock);
 974
 975         priv->base = of_iomap(np, 0);
 976         if (!priv->base) {
 977                 error = -ENOMEM;
 978                 goto out_err;
 979         }
 980
 981         priv->num_core_clks = info->num_total_core_clks;
 982         priv->num_mod_clks = info->num_hw_mod_clks;
 983         priv->last_dt_core_clk = info->last_dt_core_clk;
 984         RAW_INIT_NOTIFIER_HEAD(&priv->notifiers);
 985         priv->reg_layout = info->reg_layout;
 986         if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3) {
 987                 priv->status_regs = mstpsr;
 988                 priv->control_regs = smstpcr;
 989                 priv->reset_regs = srcr;
 990                 priv->reset_clear_regs = srstclr;
 991         } else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
 992                 priv->control_regs = stbcr;
 993         } else if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_GEN4) {
 994                 priv->status_regs = mstpsr_for_gen4;
 995                 priv->control_regs = mstpcr_for_gen4;
 996                 priv->reset_regs = srcr_for_gen4;
 997                 priv->reset_clear_regs = srstclr_for_gen4;
 998         } else {
 999                 error = -EINVAL;
1000                 goto out_err;
1001         }
1002
1003         for (i = 0; i < nclks; i++)
1004                 priv->clks[i] = ERR_PTR(-ENOENT);
1005
1006         error = of_clk_add_provider(np, cpg_mssr_clk_src_twocell_get, priv);
1007         if (error)
1008                 goto out_err;
1009
1010         cpg_mssr_priv = priv;
1011
1012         return 0;
1013
1014 out_err:
1015         if (priv->base)
1016                 iounmap(priv->base);
1017         kfree(priv);
1018
1019         return error;
1020 }
1021
1022 void __init cpg_mssr_early_init(struct device_node *np,
1023                                 const struct cpg_mssr_info *info)
1024 {
1025         int error;
1026         int i;
1027
1028         error = cpg_mssr_common_init(NULL, np, info);
1029         if (error)
1030                 return;
1031
1032         for (i = 0; i < info->num_early_core_clks; i++)
1033                 cpg_mssr_register_core_clk(&info->early_core_clks[i], info,
1034                                            cpg_mssr_priv);
1035
1036         for (i = 0; i < info->num_early_mod_clks; i++)
1037                 cpg_mssr_register_mod_clk(&info->early_mod_clks[i], info,
1038                                           cpg_mssr_priv);
1039
1040 }
1041
1042 static int __init cpg_mssr_probe(struct platform_device *pdev)
1043 {
1044         struct device *dev = &pdev->dev;
1045         struct device_node *np = dev->of_node;
1046         const struct cpg_mssr_info *info;
1047         struct cpg_mssr_priv *priv;
1048         unsigned int i;
1049         int error;
1050
1051         info = of_device_get_match_data(dev);
1052
1053         if (!cpg_mssr_priv) {
1054                 error = cpg_mssr_common_init(dev, dev->of_node, info);
1055                 if (error)
1056                         return error;
1057         }
1058
1059         priv = cpg_mssr_priv;
1060         priv->dev = dev;
1061         dev_set_drvdata(dev, priv);
1062
1063         for (i = 0; i < info->num_core_clks; i++)
1064                 cpg_mssr_register_core_clk(&info->core_clks[i], info, priv);
1065
1066         for (i = 0; i < info->num_mod_clks; i++)
1067                 cpg_mssr_register_mod_clk(&info->mod_clks[i], info, priv);
1068
1069         error = devm_add_action_or_reset(dev,
1070                                          cpg_mssr_del_clk_provider,
1071                                          np);
1072         if (error)
1073                 return error;
1074
1075         error = cpg_mssr_add_clk_domain(dev, info->core_pm_clks,
1076                                         info->num_core_pm_clks);
1077         if (error)
1078                 return error;
1079
1080         /* Reset Controller not supported for Standby Control SoCs */
1081         if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
1082                 return 0;
1083
1084         error = cpg_mssr_reset_controller_register(priv);
1085         if (error)
1086                 return error;
1087
1088         return 0;
1089 }
1090
1091 static struct platform_driver cpg_mssr_driver = {
1092         .driver         = {
1093                 .name   = "renesas-cpg-mssr",
1094                 .of_match_table = cpg_mssr_match,
1095                 .pm = DEV_PM_OPS,
1096         },
1097 };
1098
1099 static int __init cpg_mssr_init(void)
1100 {
1101         return platform_driver_probe(&cpg_mssr_driver, cpg_mssr_probe);
1102 }
1103
1104 subsys_initcall(cpg_mssr_init);
1105
1106 void __init mssr_mod_nullify(struct mssr_mod_clk *mod_clks,
1107                              unsigned int num_mod_clks,
1108                              const unsigned int *clks, unsigned int n)
1109 {
1110         unsigned int i, j;
1111
1112         for (i = 0, j = 0; i < num_mod_clks && j < n; i++)
1113                 if (mod_clks[i].id == clks[j]) {
1114                         mod_clks[i].name = NULL;
1115                         j++;
1116                 }
1117 }
1118
1119 MODULE_DESCRIPTION("Renesas CPG/MSSR Driver");