drivers/clk/renesas/renesas-cpg-mssr.c

   1 /*
   2  * Renesas Clock Pulse Generator / Module Standby and Software Reset
   3  *
   4  * Copyright (C) 2015 Glider bvba
   5  *
   6  * Based on clk-mstp.c, clk-rcar-gen2.c, and clk-rcar-gen3.c
   7  *
   8  * Copyright (C) 2013 Ideas On Board SPRL
   9  * Copyright (C) 2015 Renesas Electronics Corp.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; version 2 of the License.
  14  */
  15
  16 #include <linux/clk.h>
  17 #include <linux/clk-provider.h>
  18 #include <linux/clk/renesas.h>
  19 #include <linux/device.h>
  20 #include <linux/init.h>
  21 #include <linux/mod_devicetable.h>
  22 #include <linux/module.h>
  23 #include <linux/of_address.h>
  24 #include <linux/of_device.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/pm_clock.h>
  27 #include <linux/pm_domain.h>
  28 #include <linux/slab.h>
  29
  30 #include <dt-bindings/clock/renesas-cpg-mssr.h>
  31
  32 #include "renesas-cpg-mssr.h"
  33 #include "clk-div6.h"
  34
  35 #ifdef DEBUG
  36 #define WARN_DEBUG(x)   WARN_ON(x)
  37 #else
  38 #define WARN_DEBUG(x)   do { } while (0)
  39 #endif
  40
  41
  42 /*
  43  * Module Standby and Software Reset register offets.
  44  *
  45  * If the registers exist, these are valid for SH-Mobile, R-Mobile,
  46  * R-Car Gen 2, and R-Car Gen 3.
  47  * These are NOT valid for R-Car Gen1 and RZ/A1!
  48  */
  49
  50 /*
  51  * Module Stop Status Register offsets
  52  */
  53
  54 static const u16 mstpsr[] = {
  55         0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4,
  56         0x9A0, 0x9A4, 0x9A8, 0x9AC,
  57 };
  58
  59 #define MSTPSR(i)       mstpsr[i]
  60
  61
  62 /*
  63  * System Module Stop Control Register offsets
  64  */
  65
  66 static const u16 smstpcr[] = {
  67         0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C,
  68         0x990, 0x994, 0x998, 0x99C,
  69 };
  70
  71 #define SMSTPCR(i)      smstpcr[i]
  72
  73
  74 /*
  75  * Software Reset Register offsets
  76  */
  77
  78 static const u16 srcr[] = {
  79         0x0A0, 0x0A8, 0x0B0, 0x0B8, 0x0BC, 0x0C4, 0x1C8, 0x1CC,
  80         0x920, 0x924, 0x928, 0x92C,
  81 };
  82
  83 #define SRCR(i)         srcr[i]
  84
  85
  86 /* Realtime Module Stop Control Register offsets */
  87 #define RMSTPCR(i)      (smstpcr[i] - 0x20)
  88
  89 /* Modem Module Stop Control Register offsets (r8a73a4) */
  90 #define MMSTPCR(i)      (smstpcr[i] + 0x20)
  91
  92 /* Software Reset Clearing Register offsets */
  93 #define SRSTCLR(i)      (0x940 + (i) * 4)
  94
  95
  96 /**
  97  * Clock Pulse Generator / Module Standby and Software Reset Private Data
  98  *
  99  * @dev: CPG/MSSR device
 100  * @base: CPG/MSSR register block base address
 101  * @mstp_lock: protects writes to SMSTPCR
 102  * @clks: Array containing all Core and Module Clocks
 103  * @num_core_clks: Number of Core Clocks in clks[]
 104  * @num_mod_clks: Number of Module Clocks in clks[]
 105  * @last_dt_core_clk: ID of the last Core Clock exported to DT
 106  */
 107 struct cpg_mssr_priv {
 108         struct device *dev;
 109         void __iomem *base;
 110         spinlock_t mstp_lock;
 111
 112         struct clk **clks;
 113         unsigned int num_core_clks;
 114         unsigned int num_mod_clks;
 115         unsigned int last_dt_core_clk;
 116 };
 117
 118
 119 /**
 120  * struct mstp_clock - MSTP gating clock
 121  * @hw: handle between common and hardware-specific interfaces
 122  * @index: MSTP clock number
 123  * @priv: CPG/MSSR private data
 124  */
 125 struct mstp_clock {
 126         struct clk_hw hw;
 127         u32 index;
 128         struct cpg_mssr_priv *priv;
 129 };
 130
 131 #define to_mstp_clock(_hw) container_of(_hw, struct mstp_clock, hw)
 132
 133 static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
 134 {
 135         struct mstp_clock *clock = to_mstp_clock(hw);
 136         struct cpg_mssr_priv *priv = clock->priv;
 137         unsigned int reg = clock->index / 32;
 138         unsigned int bit = clock->index % 32;
 139         struct device *dev = priv->dev;
 140         u32 bitmask = BIT(bit);
 141         unsigned long flags;
 142         unsigned int i;
 143         u32 value;
 144
 145         dev_dbg(dev, "MSTP %u%02u/%pC %s\n", reg, bit, hw->clk,
 146                 enable ? "ON" : "OFF");
 147         spin_lock_irqsave(&priv->mstp_lock, flags);
 148
 149         value = clk_readl(priv->base + SMSTPCR(reg));
 150         if (enable)
 151                 value &= ~bitmask;
 152         else
 153                 value |= bitmask;
 154         clk_writel(value, priv->base + SMSTPCR(reg));
 155
 156         spin_unlock_irqrestore(&priv->mstp_lock, flags);
 157
 158         if (!enable)
 159                 return 0;
 160
 161         for (i = 1000; i > 0; --i) {
 162                 if (!(clk_readl(priv->base + MSTPSR(reg)) &
 163                       bitmask))
 164                         break;
 165                 cpu_relax();
 166         }
 167
 168         if (!i) {
 169                 dev_err(dev, "Failed to enable SMSTP %p[%d]\n",
 170                         priv->base + SMSTPCR(reg), bit);
 171                 return -ETIMEDOUT;
 172         }
 173
 174         return 0;
 175 }
 176
 177 static int cpg_mstp_clock_enable(struct clk_hw *hw)
 178 {
 179         return cpg_mstp_clock_endisable(hw, true);
 180 }
 181
 182 static void cpg_mstp_clock_disable(struct clk_hw *hw)
 183 {
 184         cpg_mstp_clock_endisable(hw, false);
 185 }
 186
 187 static int cpg_mstp_clock_is_enabled(struct clk_hw *hw)
 188 {
 189         struct mstp_clock *clock = to_mstp_clock(hw);
 190         struct cpg_mssr_priv *priv = clock->priv;
 191         u32 value;
 192
 193         value = clk_readl(priv->base + MSTPSR(clock->index / 32));
 194
 195         return !(value & BIT(clock->index % 32));
 196 }
 197
 198 static const struct clk_ops cpg_mstp_clock_ops = {
 199         .enable = cpg_mstp_clock_enable,
 200         .disable = cpg_mstp_clock_disable,
 201         .is_enabled = cpg_mstp_clock_is_enabled,
 202 };
 203
 204 static
 205 struct clk *cpg_mssr_clk_src_twocell_get(struct of_phandle_args *clkspec,
 206                                          void *data)
 207 {
 208         unsigned int clkidx = clkspec->args[1];
 209         struct cpg_mssr_priv *priv = data;
 210         struct device *dev = priv->dev;
 211         unsigned int idx;
 212         const char *type;
 213         struct clk *clk;
 214
 215         switch (clkspec->args[0]) {
 216         case CPG_CORE:
 217                 type = "core";
 218                 if (clkidx > priv->last_dt_core_clk) {
 219                         dev_err(dev, "Invalid %s clock index %u\n", type,
 220                                clkidx);
 221                         return ERR_PTR(-EINVAL);
 222                 }
 223                 clk = priv->clks[clkidx];
 224                 break;
 225
 226         case CPG_MOD:
 227                 type = "module";
 228                 idx = MOD_CLK_PACK(clkidx);
 229                 if (clkidx % 100 > 31 || idx >= priv->num_mod_clks) {
 230                         dev_err(dev, "Invalid %s clock index %u\n", type,
 231                                 clkidx);
 232                         return ERR_PTR(-EINVAL);
 233                 }
 234                 clk = priv->clks[priv->num_core_clks + idx];
 235                 break;
 236
 237         default:
 238                 dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]);
 239                 return ERR_PTR(-EINVAL);
 240         }
 241
 242         if (IS_ERR(clk))
 243                 dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx,
 244                        PTR_ERR(clk));
 245         else
 246                 dev_dbg(dev, "clock (%u, %u) is %pC at %lu Hz\n",
 247                         clkspec->args[0], clkspec->args[1], clk,
 248                         clk_get_rate(clk));
 249         return clk;
 250 }
 251
 252 static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core,
 253                                               const struct cpg_mssr_info *info,
 254                                               struct cpg_mssr_priv *priv)
 255 {
 256         struct clk *clk = NULL, *parent;
 257         struct device *dev = priv->dev;
 258         unsigned int id = core->id, div = core->div;
 259         const char *parent_name;
 260
 261         WARN_DEBUG(id >= priv->num_core_clks);
 262         WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
 263
 264         switch (core->type) {
 265         case CLK_TYPE_IN:
 266                 clk = of_clk_get_by_name(priv->dev->of_node, core->name);
 267                 break;
 268
 269         case CLK_TYPE_FF:
 270         case CLK_TYPE_DIV6P1:
 271         case CLK_TYPE_DIV6_RO:
 272                 WARN_DEBUG(core->parent >= priv->num_core_clks);
 273                 parent = priv->clks[core->parent];
 274                 if (IS_ERR(parent)) {
 275                         clk = parent;
 276                         goto fail;
 277                 }
 278
 279                 parent_name = __clk_get_name(parent);
 280
 281                 if (core->type == CLK_TYPE_DIV6_RO)
 282                         /* Multiply with the DIV6 register value */
 283                         div *= (readl(priv->base + core->offset) & 0x3f) + 1;
 284
 285                 if (core->type == CLK_TYPE_DIV6P1) {
 286                         clk = cpg_div6_register(core->name, 1, &parent_name,
 287                                                 priv->base + core->offset);
 288                 } else {
 289                         clk = clk_register_fixed_factor(NULL, core->name,
 290                                                         parent_name, 0,
 291                                                         core->mult, div);
 292                 }
 293                 break;
 294
 295         default:
 296                 if (info->cpg_clk_register)
 297                         clk = info->cpg_clk_register(dev, core, info,
 298                                                      priv->clks, priv->base);
 299                 else
 300                         dev_err(dev, "%s has unsupported core clock type %u\n",
 301                                 core->name, core->type);
 302                 break;
 303         }
 304
 305         if (IS_ERR_OR_NULL(clk))
 306                 goto fail;
 307
 308         dev_dbg(dev, "Core clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
 309         priv->clks[id] = clk;
 310         return;
 311
 312 fail:
 313         dev_err(dev, "Failed to register %s clock %s: %ld\n", "core,",
 314                 core->name, PTR_ERR(clk));
 315 }
 316
 317 static void __init cpg_mssr_register_mod_clk(const struct mssr_mod_clk *mod,
 318                                              const struct cpg_mssr_info *info,
 319                                              struct cpg_mssr_priv *priv)
 320 {
 321         struct mstp_clock *clock = NULL;
 322         struct device *dev = priv->dev;
 323         unsigned int id = mod->id;
 324         struct clk_init_data init;
 325         struct clk *parent, *clk;
 326         const char *parent_name;
 327         unsigned int i;
 328
 329         WARN_DEBUG(id < priv->num_core_clks);
 330         WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks);
 331         WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks);
 332         WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
 333
 334         parent = priv->clks[mod->parent];
 335         if (IS_ERR(parent)) {
 336                 clk = parent;
 337                 goto fail;
 338         }
 339
 340         clock = kzalloc(sizeof(*clock), GFP_KERNEL);
 341         if (!clock) {
 342                 clk = ERR_PTR(-ENOMEM);
 343                 goto fail;
 344         }
 345
 346         init.name = mod->name;
 347         init.ops = &cpg_mstp_clock_ops;
 348         init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT;
 349         for (i = 0; i < info->num_crit_mod_clks; i++)
 350                 if (id == info->crit_mod_clks[i]) {
 351 #ifdef CLK_ENABLE_HAND_OFF
 352                         dev_dbg(dev, "MSTP %s setting CLK_ENABLE_HAND_OFF\n",
 353                                 mod->name);
 354                         init.flags |= CLK_ENABLE_HAND_OFF;
 355                         break;
 356 #else
 357                         dev_dbg(dev, "Ignoring MSTP %s to prevent disabling\n",
 358                                 mod->name);
 359                         kfree(clock);
 360                         return;
 361 #endif
 362                 }
 363
 364         parent_name = __clk_get_name(parent);
 365         init.parent_names = &parent_name;
 366         init.num_parents = 1;
 367
 368         clock->index = id - priv->num_core_clks;
 369         clock->priv = priv;
 370         clock->hw.init = &init;
 371
 372         clk = clk_register(NULL, &clock->hw);
 373         if (IS_ERR(clk))
 374                 goto fail;
 375
 376         dev_dbg(dev, "Module clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
 377         priv->clks[id] = clk;
 378         return;
 379
 380 fail:
 381         dev_err(dev, "Failed to register %s clock %s: %ld\n", "module,",
 382                 mod->name, PTR_ERR(clk));
 383         kfree(clock);
 384 }
 385
 386 struct cpg_mssr_clk_domain {
 387         struct generic_pm_domain genpd;
 388         struct device_node *np;
 389         unsigned int num_core_pm_clks;
 390         unsigned int core_pm_clks[0];
 391 };
 392
 393 static struct cpg_mssr_clk_domain *cpg_mssr_clk_domain;
 394
 395 static bool cpg_mssr_is_pm_clk(const struct of_phandle_args *clkspec,
 396                                struct cpg_mssr_clk_domain *pd)
 397 {
 398         unsigned int i;
 399
 400         if (clkspec->np != pd->np || clkspec->args_count != 2)
 401                 return false;
 402
 403         switch (clkspec->args[0]) {
 404         case CPG_CORE:
 405                 for (i = 0; i < pd->num_core_pm_clks; i++)
 406                         if (clkspec->args[1] == pd->core_pm_clks[i])
 407                                 return true;
 408                 return false;
 409
 410         case CPG_MOD:
 411                 return true;
 412
 413         default:
 414                 return false;
 415         }
 416 }
 417
 418 int cpg_mssr_attach_dev(struct generic_pm_domain *unused, struct device *dev)
 419 {
 420         struct cpg_mssr_clk_domain *pd = cpg_mssr_clk_domain;
 421         struct device_node *np = dev->of_node;
 422         struct of_phandle_args clkspec;
 423         struct clk *clk;
 424         int i = 0;
 425         int error;
 426
 427         if (!pd) {
 428                 dev_dbg(dev, "CPG/MSSR clock domain not yet available\n");
 429                 return -EPROBE_DEFER;
 430         }
 431
 432         while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
 433                                            &clkspec)) {
 434                 if (cpg_mssr_is_pm_clk(&clkspec, pd))
 435                         goto found;
 436
 437                 of_node_put(clkspec.np);
 438                 i++;
 439         }
 440
 441         return 0;
 442
 443 found:
 444         clk = of_clk_get_from_provider(&clkspec);
 445         of_node_put(clkspec.np);
 446
 447         if (IS_ERR(clk))
 448                 return PTR_ERR(clk);
 449
 450         error = pm_clk_create(dev);
 451         if (error) {
 452                 dev_err(dev, "pm_clk_create failed %d\n", error);
 453                 goto fail_put;
 454         }
 455
 456         error = pm_clk_add_clk(dev, clk);
 457         if (error) {
 458                 dev_err(dev, "pm_clk_add_clk %pC failed %d\n", clk, error);
 459                 goto fail_destroy;
 460         }
 461
 462         return 0;
 463
 464 fail_destroy:
 465         pm_clk_destroy(dev);
 466 fail_put:
 467         clk_put(clk);
 468         return error;
 469 }
 470
 471 void cpg_mssr_detach_dev(struct generic_pm_domain *unused, struct device *dev)
 472 {
 473         if (!list_empty(&dev->power.subsys_data->clock_list))
 474                 pm_clk_destroy(dev);
 475 }
 476
 477 static int __init cpg_mssr_add_clk_domain(struct device *dev,
 478                                           const unsigned int *core_pm_clks,
 479                                           unsigned int num_core_pm_clks)
 480 {
 481         struct device_node *np = dev->of_node;
 482         struct generic_pm_domain *genpd;
 483         struct cpg_mssr_clk_domain *pd;
 484         size_t pm_size = num_core_pm_clks * sizeof(core_pm_clks[0]);
 485
 486         pd = devm_kzalloc(dev, sizeof(*pd) + pm_size, GFP_KERNEL);
 487         if (!pd)
 488                 return -ENOMEM;
 489
 490         pd->np = np;
 491         pd->num_core_pm_clks = num_core_pm_clks;
 492         memcpy(pd->core_pm_clks, core_pm_clks, pm_size);
 493
 494         genpd = &pd->genpd;
 495         genpd->name = np->name;
 496         genpd->flags = GENPD_FLAG_PM_CLK;
 497         genpd->attach_dev = cpg_mssr_attach_dev;
 498         genpd->detach_dev = cpg_mssr_detach_dev;
 499         pm_genpd_init(genpd, &pm_domain_always_on_gov, false);
 500         cpg_mssr_clk_domain = pd;
 501
 502         of_genpd_add_provider_simple(np, genpd);
 503         return 0;
 504 }
 505
 506 static const struct of_device_id cpg_mssr_match[] = {
 507 #ifdef CONFIG_ARCH_R8A7795
 508         {
 509                 .compatible = "renesas,r8a7795-cpg-mssr",
 510                 .data = &r8a7795_cpg_mssr_info,
 511         },
 512 #endif
 513 #ifdef CONFIG_ARCH_R8A7796
 514         {
 515                 .compatible = "renesas,r8a7796-cpg-mssr",
 516                 .data = &r8a7796_cpg_mssr_info,
 517         },
 518 #endif
 519         { /* sentinel */ }
 520 };
 521
 522 static void cpg_mssr_del_clk_provider(void *data)
 523 {
 524         of_clk_del_provider(data);
 525 }
 526
 527 static int __init cpg_mssr_probe(struct platform_device *pdev)
 528 {
 529         struct device *dev = &pdev->dev;
 530         struct device_node *np = dev->of_node;
 531         const struct cpg_mssr_info *info;
 532         struct cpg_mssr_priv *priv;
 533         unsigned int nclks, i;
 534         struct resource *res;
 535         struct clk **clks;
 536         int error;
 537
 538         info = of_match_node(cpg_mssr_match, np)->data;
 539         if (info->init) {
 540                 error = info->init(dev);
 541                 if (error)
 542                         return error;
 543         }
 544
 545         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 546         if (!priv)
 547                 return -ENOMEM;
 548
 549         priv->dev = dev;
 550         spin_lock_init(&priv->mstp_lock);
 551
 552         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 553         priv->base = devm_ioremap_resource(dev, res);
 554         if (IS_ERR(priv->base))
 555                 return PTR_ERR(priv->base);
 556
 557         nclks = info->num_total_core_clks + info->num_hw_mod_clks;
 558         clks = devm_kmalloc_array(dev, nclks, sizeof(*clks), GFP_KERNEL);
 559         if (!clks)
 560                 return -ENOMEM;
 561
 562         priv->clks = clks;
 563         priv->num_core_clks = info->num_total_core_clks;
 564         priv->num_mod_clks = info->num_hw_mod_clks;
 565         priv->last_dt_core_clk = info->last_dt_core_clk;
 566
 567         for (i = 0; i < nclks; i++)
 568                 clks[i] = ERR_PTR(-ENOENT);
 569
 570         for (i = 0; i < info->num_core_clks; i++)
 571                 cpg_mssr_register_core_clk(&info->core_clks[i], info, priv);
 572
 573         for (i = 0; i < info->num_mod_clks; i++)
 574                 cpg_mssr_register_mod_clk(&info->mod_clks[i], info, priv);
 575
 576         error = of_clk_add_provider(np, cpg_mssr_clk_src_twocell_get, priv);
 577         if (error)
 578                 return error;
 579
 580         error = devm_add_action_or_reset(dev,
 581                                          cpg_mssr_del_clk_provider,
 582                                          np);
 583         if (error)
 584                 return error;
 585
 586         error = cpg_mssr_add_clk_domain(dev, info->core_pm_clks,
 587                                         info->num_core_pm_clks);
 588         if (error)
 589                 return error;
 590
 591         return 0;
 592 }
 593
 594 static struct platform_driver cpg_mssr_driver = {
 595         .driver         = {
 596                 .name   = "renesas-cpg-mssr",
 597                 .of_match_table = cpg_mssr_match,
 598         },
 599 };
 600
 601 static int __init cpg_mssr_init(void)
 602 {
 603         return platform_driver_probe(&cpg_mssr_driver, cpg_mssr_probe);
 604 }
 605
 606 subsys_initcall(cpg_mssr_init);
 607
 608 MODULE_DESCRIPTION("Renesas CPG/MSSR Driver");
 609 MODULE_LICENSE("GPL v2");