2 * R-Car Gen3 Clock Pulse Generator
4 * Copyright (C) 2015-2016 Glider bvba
6 * Based on clk-rcar-gen3.c
8 * Copyright (C) 2015 Renesas Electronics Corp.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
15 #include <linux/bug.h>
16 #include <linux/clk.h>
17 #include <linux/clk-provider.h>
18 #include <linux/device.h>
19 #include <linux/err.h>
20 #include <linux/init.h>
22 #include <linux/slab.h>
24 #include "renesas-cpg-mssr.h"
25 #include "rcar-gen3-cpg.h"
27 #define CPG_PLL0CR 0x00d8
28 #define CPG_PLL2CR 0x002c
29 #define CPG_PLL4CR 0x01f4
35 #define CPG_SD_STP_HCK BIT(9)
36 #define CPG_SD_STP_CK BIT(8)
38 #define CPG_SD_STP_MASK (CPG_SD_STP_HCK | CPG_SD_STP_CK)
39 #define CPG_SD_FC_MASK (0x7 << 2 | 0x3 << 0)
41 #define CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) \
43 .val = ((stp_hck) ? CPG_SD_STP_HCK : 0) | \
44 ((stp_ck) ? CPG_SD_STP_CK : 0) | \
58 const struct sd_div_table *div_table;
66 * stp_hck stp_ck (div) (div) = sd_srcfc x sd_fc
67 *-------------------------------------------------------------------
79 static const struct sd_div_table cpg_sd_div_table[] = {
80 /* CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) */
81 CPG_SD_DIV_TABLE_DATA(0, 0, 0, 1, 4),
82 CPG_SD_DIV_TABLE_DATA(0, 0, 1, 1, 8),
83 CPG_SD_DIV_TABLE_DATA(1, 0, 2, 1, 16),
84 CPG_SD_DIV_TABLE_DATA(1, 0, 3, 1, 32),
85 CPG_SD_DIV_TABLE_DATA(1, 0, 4, 1, 64),
86 CPG_SD_DIV_TABLE_DATA(0, 0, 0, 0, 2),
87 CPG_SD_DIV_TABLE_DATA(0, 0, 1, 0, 4),
88 CPG_SD_DIV_TABLE_DATA(1, 0, 2, 0, 8),
89 CPG_SD_DIV_TABLE_DATA(1, 0, 3, 0, 16),
90 CPG_SD_DIV_TABLE_DATA(1, 0, 4, 0, 32),
93 #define to_sd_clock(_hw) container_of(_hw, struct sd_clock, hw)
95 static int cpg_sd_clock_enable(struct clk_hw *hw)
97 struct sd_clock *clock = to_sd_clock(hw);
101 val = clk_readl(clock->reg);
103 sd_fc = val & CPG_SD_FC_MASK;
104 for (i = 0; i < clock->div_num; i++)
105 if (sd_fc == (clock->div_table[i].val & CPG_SD_FC_MASK))
108 if (i >= clock->div_num)
111 val &= ~(CPG_SD_STP_MASK);
112 val |= clock->div_table[i].val & CPG_SD_STP_MASK;
114 clk_writel(val, clock->reg);
119 static void cpg_sd_clock_disable(struct clk_hw *hw)
121 struct sd_clock *clock = to_sd_clock(hw);
123 clk_writel(clk_readl(clock->reg) | CPG_SD_STP_MASK, clock->reg);
126 static int cpg_sd_clock_is_enabled(struct clk_hw *hw)
128 struct sd_clock *clock = to_sd_clock(hw);
130 return !(clk_readl(clock->reg) & CPG_SD_STP_MASK);
133 static unsigned long cpg_sd_clock_recalc_rate(struct clk_hw *hw,
134 unsigned long parent_rate)
136 struct sd_clock *clock = to_sd_clock(hw);
137 unsigned long rate = parent_rate;
141 val = clk_readl(clock->reg);
143 sd_fc = val & CPG_SD_FC_MASK;
144 for (i = 0; i < clock->div_num; i++)
145 if (sd_fc == (clock->div_table[i].val & CPG_SD_FC_MASK))
148 if (i >= clock->div_num)
151 return DIV_ROUND_CLOSEST(rate, clock->div_table[i].div);
154 static unsigned int cpg_sd_clock_calc_div(struct sd_clock *clock,
156 unsigned long parent_rate)
163 div = DIV_ROUND_CLOSEST(parent_rate, rate);
165 return clamp_t(unsigned int, div, clock->div_min, clock->div_max);
168 static long cpg_sd_clock_round_rate(struct clk_hw *hw, unsigned long rate,
169 unsigned long *parent_rate)
171 struct sd_clock *clock = to_sd_clock(hw);
172 unsigned int div = cpg_sd_clock_calc_div(clock, rate, *parent_rate);
174 return DIV_ROUND_CLOSEST(*parent_rate, div);
177 static int cpg_sd_clock_set_rate(struct clk_hw *hw, unsigned long rate,
178 unsigned long parent_rate)
180 struct sd_clock *clock = to_sd_clock(hw);
181 unsigned int div = cpg_sd_clock_calc_div(clock, rate, parent_rate);
185 for (i = 0; i < clock->div_num; i++)
186 if (div == clock->div_table[i].div)
189 if (i >= clock->div_num)
192 val = clk_readl(clock->reg);
193 val &= ~(CPG_SD_STP_MASK | CPG_SD_FC_MASK);
194 val |= clock->div_table[i].val & (CPG_SD_STP_MASK | CPG_SD_FC_MASK);
195 clk_writel(val, clock->reg);
200 static const struct clk_ops cpg_sd_clock_ops = {
201 .enable = cpg_sd_clock_enable,
202 .disable = cpg_sd_clock_disable,
203 .is_enabled = cpg_sd_clock_is_enabled,
204 .recalc_rate = cpg_sd_clock_recalc_rate,
205 .round_rate = cpg_sd_clock_round_rate,
206 .set_rate = cpg_sd_clock_set_rate,
209 static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core,
211 const char *parent_name)
213 struct clk_init_data init;
214 struct sd_clock *clock;
218 clock = kzalloc(sizeof(*clock), GFP_KERNEL);
220 return ERR_PTR(-ENOMEM);
222 init.name = core->name;
223 init.ops = &cpg_sd_clock_ops;
224 init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT;
225 init.parent_names = &parent_name;
226 init.num_parents = 1;
228 clock->reg = base + core->offset;
229 clock->hw.init = &init;
230 clock->div_table = cpg_sd_div_table;
231 clock->div_num = ARRAY_SIZE(cpg_sd_div_table);
233 clock->div_max = clock->div_table[0].div;
234 clock->div_min = clock->div_max;
235 for (i = 1; i < clock->div_num; i++) {
236 clock->div_max = max(clock->div_max, clock->div_table[i].div);
237 clock->div_min = min(clock->div_min, clock->div_table[i].div);
240 clk = clk_register(NULL, &clock->hw);
248 static const struct rcar_gen3_cpg_pll_config *cpg_pll_config __initdata;
249 static unsigned int cpg_clk_extalr __initdata;
251 struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
252 const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
253 struct clk **clks, void __iomem *base)
255 const struct clk *parent;
256 unsigned int mult = 1;
257 unsigned int div = 1;
260 parent = clks[core->parent];
262 return ERR_CAST(parent);
264 switch (core->type) {
265 case CLK_TYPE_GEN3_MAIN:
266 div = cpg_pll_config->extal_div;
269 case CLK_TYPE_GEN3_PLL0:
271 * PLL0 is a configurable multiplier clock. Register it as a
272 * fixed factor clock for now as there's no generic multiplier
273 * clock implementation and we currently have no need to change
274 * the multiplier value.
276 value = readl(base + CPG_PLL0CR);
277 mult = (((value >> 24) & 0x7f) + 1) * 2;
280 case CLK_TYPE_GEN3_PLL1:
281 mult = cpg_pll_config->pll1_mult;
284 case CLK_TYPE_GEN3_PLL2:
286 * PLL2 is a configurable multiplier clock. Register it as a
287 * fixed factor clock for now as there's no generic multiplier
288 * clock implementation and we currently have no need to change
289 * the multiplier value.
291 value = readl(base + CPG_PLL2CR);
292 mult = (((value >> 24) & 0x7f) + 1) * 2;
295 case CLK_TYPE_GEN3_PLL3:
296 mult = cpg_pll_config->pll3_mult;
299 case CLK_TYPE_GEN3_PLL4:
301 * PLL4 is a configurable multiplier clock. Register it as a
302 * fixed factor clock for now as there's no generic multiplier
303 * clock implementation and we currently have no need to change
304 * the multiplier value.
306 value = readl(base + CPG_PLL4CR);
307 mult = (((value >> 24) & 0x7f) + 1) * 2;
310 case CLK_TYPE_GEN3_SD:
311 return cpg_sd_clk_register(core, base, __clk_get_name(parent));
313 case CLK_TYPE_GEN3_R:
316 * Only if EXTALR is populated, we switch to it.
318 value = readl(base + CPG_RCKCR) & 0x3f;
320 if (clk_get_rate(clks[cpg_clk_extalr])) {
321 parent = clks[cpg_clk_extalr];
325 writel(value, base + CPG_RCKCR);
329 return ERR_PTR(-EINVAL);
332 return clk_register_fixed_factor(NULL, core->name,
333 __clk_get_name(parent), 0, mult, div);
337 * Reset register definitions.
339 #define MODEMR 0xe6160060
341 u32 __init rcar_gen3_read_mode_pins(void)
343 void __iomem *modemr = ioremap_nocache(MODEMR, 4);
347 mode = ioread32(modemr);
353 int __init rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config,
354 unsigned int clk_extalr)
356 cpg_pll_config = config;
357 cpg_clk_extalr = clk_extalr;