1 /* SPDX-License-Identifier: GPL-2.0 */
3 * R-Car Gen2 Clock Pulse Generator
5 * Copyright (C) 2016 Cogent Embedded Inc.
8 #ifndef __CLK_RENESAS_RCAR_GEN2_CPG_H__
9 #define __CLK_RENESAS_RCAR_GEN2_CPG_H__
11 enum rcar_gen2_clk_types {
12 CLK_TYPE_GEN2_MAIN = CLK_TYPE_CUSTOM,
26 struct rcar_gen2_cpg_pll_config {
30 u8 pll0_mult; /* leave as zero if PLL0CR exists */
33 struct clk *rcar_gen2_cpg_clk_register(struct device *dev,
34 const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
35 struct clk **clks, void __iomem *base,
36 struct raw_notifier_head *notifiers);
37 int rcar_gen2_cpg_init(const struct rcar_gen2_cpg_pll_config *config,
38 unsigned int pll0_div, u32 mode);