drivers/clk/renesas/r8a7795-cpg-mssr.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * r8a7795 Clock Pulse Generator / Module Standby and Software Reset
   4  *
   5  * Copyright (C) 2015 Glider bvba
   6  * Copyright (C) 2018-2019 Renesas Electronics Corp.
   7  *
   8  * Based on clk-rcar-gen3.c
   9  *
  10  * Copyright (C) 2015 Renesas Electronics Corp.
  11  */
  12
  13 #include <linux/device.h>
  14 #include <linux/init.h>
  15 #include <linux/kernel.h>
  16 #include <linux/soc/renesas/rcar-rst.h>
  17 #include <linux/sys_soc.h>
  18
  19 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
  20
  21 #include "renesas-cpg-mssr.h"
  22 #include "rcar-gen3-cpg.h"
  23
  24 enum clk_ids {
  25         /* Core Clock Outputs exported to DT */
  26         LAST_DT_CORE_CLK = R8A7795_CLK_S0D12,
  27
  28         /* External Input Clocks */
  29         CLK_EXTAL,
  30         CLK_EXTALR,
  31
  32         /* Internal Core Clocks */
  33         CLK_MAIN,
  34         CLK_PLL0,
  35         CLK_PLL1,
  36         CLK_PLL2,
  37         CLK_PLL3,
  38         CLK_PLL4,
  39         CLK_PLL1_DIV2,
  40         CLK_PLL1_DIV4,
  41         CLK_S0,
  42         CLK_S1,
  43         CLK_S2,
  44         CLK_S3,
  45         CLK_SDSRC,
  46         CLK_SSPSRC,
  47         CLK_RPCSRC,
  48         CLK_RINT,
  49
  50         /* Module Clocks */
  51         MOD_CLK_BASE
  52 };
  53
  54 static const struct cpg_core_clk r8a7795_core_clks[] __initconst = {
  55         /* External Clock Inputs */
  56         DEF_INPUT("extal",      CLK_EXTAL),
  57         DEF_INPUT("extalr",     CLK_EXTALR),
  58
  59         /* Internal Core Clocks */
  60         DEF_BASE(".main",       CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
  61         DEF_BASE(".pll0",       CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
  62         DEF_BASE(".pll1",       CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
  63         DEF_BASE(".pll2",       CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
  64         DEF_BASE(".pll3",       CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
  65         DEF_BASE(".pll4",       CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
  66
  67         DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2,     CLK_PLL1,       2, 1),
  68         DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4,     CLK_PLL1_DIV2,  2, 1),
  69         DEF_FIXED(".s0",        CLK_S0,            CLK_PLL1_DIV2,  2, 1),
  70         DEF_FIXED(".s1",        CLK_S1,            CLK_PLL1_DIV2,  3, 1),
  71         DEF_FIXED(".s2",        CLK_S2,            CLK_PLL1_DIV2,  4, 1),
  72         DEF_FIXED(".s3",        CLK_S3,            CLK_PLL1_DIV2,  6, 1),
  73         DEF_FIXED(".sdsrc",     CLK_SDSRC,         CLK_PLL1_DIV2,  2, 1),
  74
  75         DEF_BASE(".rpcsrc",     CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
  76
  77         DEF_GEN3_OSC(".r",      CLK_RINT,          CLK_EXTAL,      32),
  78
  79         /* Core Clock Outputs */
  80         DEF_GEN3_Z("z",         R8A7795_CLK_Z,     CLK_TYPE_GEN3_Z,  CLK_PLL0, 2, 8),
  81         DEF_GEN3_Z("z2",        R8A7795_CLK_Z2,    CLK_TYPE_GEN3_Z,  CLK_PLL2, 2, 0),
  82         DEF_GEN3_Z("zg",        R8A7795_CLK_ZG,    CLK_TYPE_GEN3_ZG, CLK_PLL4, 4, 24),
  83         DEF_FIXED("ztr",        R8A7795_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),
  84         DEF_FIXED("ztrd2",      R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
  85         DEF_FIXED("zt",         R8A7795_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),
  86         DEF_FIXED("zx",         R8A7795_CLK_ZX,    CLK_PLL1_DIV2,  2, 1),
  87         DEF_FIXED("s0d1",       R8A7795_CLK_S0D1,  CLK_S0,         1, 1),
  88         DEF_FIXED("s0d2",       R8A7795_CLK_S0D2,  CLK_S0,         2, 1),
  89         DEF_FIXED("s0d3",       R8A7795_CLK_S0D3,  CLK_S0,         3, 1),
  90         DEF_FIXED("s0d4",       R8A7795_CLK_S0D4,  CLK_S0,         4, 1),
  91         DEF_FIXED("s0d6",       R8A7795_CLK_S0D6,  CLK_S0,         6, 1),
  92         DEF_FIXED("s0d8",       R8A7795_CLK_S0D8,  CLK_S0,         8, 1),
  93         DEF_FIXED("s0d12",      R8A7795_CLK_S0D12, CLK_S0,        12, 1),
  94         DEF_FIXED("s1d1",       R8A7795_CLK_S1D1,  CLK_S1,         1, 1),
  95         DEF_FIXED("s1d2",       R8A7795_CLK_S1D2,  CLK_S1,         2, 1),
  96         DEF_FIXED("s1d4",       R8A7795_CLK_S1D4,  CLK_S1,         4, 1),
  97         DEF_FIXED("s2d1",       R8A7795_CLK_S2D1,  CLK_S2,         1, 1),
  98         DEF_FIXED("s2d2",       R8A7795_CLK_S2D2,  CLK_S2,         2, 1),
  99         DEF_FIXED("s2d4",       R8A7795_CLK_S2D4,  CLK_S2,         4, 1),
 100         DEF_FIXED("s3d1",       R8A7795_CLK_S3D1,  CLK_S3,         1, 1),
 101         DEF_FIXED("s3d2",       R8A7795_CLK_S3D2,  CLK_S3,         2, 1),
 102         DEF_FIXED("s3d4",       R8A7795_CLK_S3D4,  CLK_S3,         4, 1),
 103
 104         DEF_GEN3_SDH("sd0h",    R8A7795_CLK_SD0H,  CLK_SDSRC,        0x074),
 105         DEF_GEN3_SDH("sd1h",    R8A7795_CLK_SD1H,  CLK_SDSRC,        0x078),
 106         DEF_GEN3_SDH("sd2h",    R8A7795_CLK_SD2H,  CLK_SDSRC,        0x268),
 107         DEF_GEN3_SDH("sd3h",    R8A7795_CLK_SD3H,  CLK_SDSRC,        0x26c),
 108         DEF_GEN3_SD("sd0",      R8A7795_CLK_SD0,   R8A7795_CLK_SD0H, 0x074),
 109         DEF_GEN3_SD("sd1",      R8A7795_CLK_SD1,   R8A7795_CLK_SD1H, 0x078),
 110         DEF_GEN3_SD("sd2",      R8A7795_CLK_SD2,   R8A7795_CLK_SD2H, 0x268),
 111         DEF_GEN3_SD("sd3",      R8A7795_CLK_SD3,   R8A7795_CLK_SD3H, 0x26c),
 112
 113         DEF_BASE("rpc",         R8A7795_CLK_RPC,   CLK_TYPE_GEN3_RPC,   CLK_RPCSRC),
 114         DEF_BASE("rpcd2",       R8A7795_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A7795_CLK_RPC),
 115
 116         DEF_FIXED("cl",         R8A7795_CLK_CL,    CLK_PLL1_DIV2, 48, 1),
 117         DEF_FIXED("cr",         R8A7795_CLK_CR,    CLK_PLL1_DIV4,  2, 1),
 118         DEF_FIXED("cp",         R8A7795_CLK_CP,    CLK_EXTAL,      2, 1),
 119         DEF_FIXED("cpex",       R8A7795_CLK_CPEX,  CLK_EXTAL,      2, 1),
 120
 121         DEF_DIV6P1("canfd",     R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
 122         DEF_DIV6P1("csi0",      R8A7795_CLK_CSI0,  CLK_PLL1_DIV4, 0x00c),
 123         DEF_DIV6P1("mso",       R8A7795_CLK_MSO,   CLK_PLL1_DIV4, 0x014),
 124         DEF_DIV6P1("hdmi",      R8A7795_CLK_HDMI,  CLK_PLL1_DIV4, 0x250),
 125
 126         DEF_GEN3_OSC("osc",     R8A7795_CLK_OSC,   CLK_EXTAL,     8),
 127
 128         DEF_BASE("r",           R8A7795_CLK_R,     CLK_TYPE_GEN3_R, CLK_RINT),
 129 };
 130
 131 static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {
 132         DEF_MOD("3dge",                  112,   R8A7795_CLK_ZG),
 133         DEF_MOD("fdp1-1",                118,   R8A7795_CLK_S0D1),
 134         DEF_MOD("fdp1-0",                119,   R8A7795_CLK_S0D1),
 135         DEF_MOD("tmu4",                  121,   R8A7795_CLK_S0D6),
 136         DEF_MOD("tmu3",                  122,   R8A7795_CLK_S3D2),
 137         DEF_MOD("tmu2",                  123,   R8A7795_CLK_S3D2),
 138         DEF_MOD("tmu1",                  124,   R8A7795_CLK_S3D2),
 139         DEF_MOD("tmu0",                  125,   R8A7795_CLK_CP),
 140         DEF_MOD("scif5",                 202,   R8A7795_CLK_S3D4),
 141         DEF_MOD("scif4",                 203,   R8A7795_CLK_S3D4),
 142         DEF_MOD("scif3",                 204,   R8A7795_CLK_S3D4),
 143         DEF_MOD("scif1",                 206,   R8A7795_CLK_S3D4),
 144         DEF_MOD("scif0",                 207,   R8A7795_CLK_S3D4),
 145         DEF_MOD("msiof3",                208,   R8A7795_CLK_MSO),
 146         DEF_MOD("msiof2",                209,   R8A7795_CLK_MSO),
 147         DEF_MOD("msiof1",                210,   R8A7795_CLK_MSO),
 148         DEF_MOD("msiof0",                211,   R8A7795_CLK_MSO),
 149         DEF_MOD("sys-dmac2",             217,   R8A7795_CLK_S3D1),
 150         DEF_MOD("sys-dmac1",             218,   R8A7795_CLK_S3D1),
 151         DEF_MOD("sys-dmac0",             219,   R8A7795_CLK_S0D3),
 152         DEF_MOD("sceg-pub",              229,   R8A7795_CLK_CR),
 153         DEF_MOD("cmt3",                  300,   R8A7795_CLK_R),
 154         DEF_MOD("cmt2",                  301,   R8A7795_CLK_R),
 155         DEF_MOD("cmt1",                  302,   R8A7795_CLK_R),
 156         DEF_MOD("cmt0",                  303,   R8A7795_CLK_R),
 157         DEF_MOD("tpu0",                  304,   R8A7795_CLK_S3D4),
 158         DEF_MOD("scif2",                 310,   R8A7795_CLK_S3D4),
 159         DEF_MOD("sdif3",                 311,   R8A7795_CLK_SD3),
 160         DEF_MOD("sdif2",                 312,   R8A7795_CLK_SD2),
 161         DEF_MOD("sdif1",                 313,   R8A7795_CLK_SD1),
 162         DEF_MOD("sdif0",                 314,   R8A7795_CLK_SD0),
 163         DEF_MOD("pcie1",                 318,   R8A7795_CLK_S3D1),
 164         DEF_MOD("pcie0",                 319,   R8A7795_CLK_S3D1),
 165         DEF_MOD("usb-dmac30",            326,   R8A7795_CLK_S3D1),
 166         DEF_MOD("usb3-if0",              328,   R8A7795_CLK_S3D1),
 167         DEF_MOD("usb-dmac31",            329,   R8A7795_CLK_S3D1),
 168         DEF_MOD("usb-dmac0",             330,   R8A7795_CLK_S3D1),
 169         DEF_MOD("usb-dmac1",             331,   R8A7795_CLK_S3D1),
 170         DEF_MOD("rwdt",                  402,   R8A7795_CLK_R),
 171         DEF_MOD("intc-ex",               407,   R8A7795_CLK_CP),
 172         DEF_MOD("intc-ap",               408,   R8A7795_CLK_S0D3),
 173         DEF_MOD("audmac1",               501,   R8A7795_CLK_S1D2),
 174         DEF_MOD("audmac0",               502,   R8A7795_CLK_S1D2),
 175         DEF_MOD("drif31",                508,   R8A7795_CLK_S3D2),
 176         DEF_MOD("drif30",                509,   R8A7795_CLK_S3D2),
 177         DEF_MOD("drif21",                510,   R8A7795_CLK_S3D2),
 178         DEF_MOD("drif20",                511,   R8A7795_CLK_S3D2),
 179         DEF_MOD("drif11",                512,   R8A7795_CLK_S3D2),
 180         DEF_MOD("drif10",                513,   R8A7795_CLK_S3D2),
 181         DEF_MOD("drif01",                514,   R8A7795_CLK_S3D2),
 182         DEF_MOD("drif00",                515,   R8A7795_CLK_S3D2),
 183         DEF_MOD("hscif4",                516,   R8A7795_CLK_S3D1),
 184         DEF_MOD("hscif3",                517,   R8A7795_CLK_S3D1),
 185         DEF_MOD("hscif2",                518,   R8A7795_CLK_S3D1),
 186         DEF_MOD("hscif1",                519,   R8A7795_CLK_S3D1),
 187         DEF_MOD("hscif0",                520,   R8A7795_CLK_S3D1),
 188         DEF_MOD("thermal",               522,   R8A7795_CLK_CP),
 189         DEF_MOD("pwm",                   523,   R8A7795_CLK_S0D12),
 190         DEF_MOD("fcpvd2",                601,   R8A7795_CLK_S0D2),
 191         DEF_MOD("fcpvd1",                602,   R8A7795_CLK_S0D2),
 192         DEF_MOD("fcpvd0",                603,   R8A7795_CLK_S0D2),
 193         DEF_MOD("fcpvb1",                606,   R8A7795_CLK_S0D1),
 194         DEF_MOD("fcpvb0",                607,   R8A7795_CLK_S0D1),
 195         DEF_MOD("fcpvi1",                610,   R8A7795_CLK_S0D1),
 196         DEF_MOD("fcpvi0",                611,   R8A7795_CLK_S0D1),
 197         DEF_MOD("fcpf1",                 614,   R8A7795_CLK_S0D1),
 198         DEF_MOD("fcpf0",                 615,   R8A7795_CLK_S0D1),
 199         DEF_MOD("fcpcs",                 619,   R8A7795_CLK_S0D1),
 200         DEF_MOD("vspd2",                 621,   R8A7795_CLK_S0D2),
 201         DEF_MOD("vspd1",                 622,   R8A7795_CLK_S0D2),
 202         DEF_MOD("vspd0",                 623,   R8A7795_CLK_S0D2),
 203         DEF_MOD("vspbc",                 624,   R8A7795_CLK_S0D1),
 204         DEF_MOD("vspbd",                 626,   R8A7795_CLK_S0D1),
 205         DEF_MOD("vspi1",                 630,   R8A7795_CLK_S0D1),
 206         DEF_MOD("vspi0",                 631,   R8A7795_CLK_S0D1),
 207         DEF_MOD("ehci3",                 700,   R8A7795_CLK_S3D2),
 208         DEF_MOD("ehci2",                 701,   R8A7795_CLK_S3D2),
 209         DEF_MOD("ehci1",                 702,   R8A7795_CLK_S3D2),
 210         DEF_MOD("ehci0",                 703,   R8A7795_CLK_S3D2),
 211         DEF_MOD("hsusb",                 704,   R8A7795_CLK_S3D2),
 212         DEF_MOD("hsusb3",                705,   R8A7795_CLK_S3D2),
 213         DEF_MOD("cmm3",                  708,   R8A7795_CLK_S2D1),
 214         DEF_MOD("cmm2",                  709,   R8A7795_CLK_S2D1),
 215         DEF_MOD("cmm1",                  710,   R8A7795_CLK_S2D1),
 216         DEF_MOD("cmm0",                  711,   R8A7795_CLK_S2D1),
 217         DEF_MOD("csi20",                 714,   R8A7795_CLK_CSI0),
 218         DEF_MOD("csi41",                 715,   R8A7795_CLK_CSI0),
 219         DEF_MOD("csi40",                 716,   R8A7795_CLK_CSI0),
 220         DEF_MOD("du3",                   721,   R8A7795_CLK_S2D1),
 221         DEF_MOD("du2",                   722,   R8A7795_CLK_S2D1),
 222         DEF_MOD("du1",                   723,   R8A7795_CLK_S2D1),
 223         DEF_MOD("du0",                   724,   R8A7795_CLK_S2D1),
 224         DEF_MOD("lvds",                  727,   R8A7795_CLK_S0D4),
 225         DEF_MOD("hdmi1",                 728,   R8A7795_CLK_HDMI),
 226         DEF_MOD("hdmi0",                 729,   R8A7795_CLK_HDMI),
 227         DEF_MOD("mlp",                   802,   R8A7795_CLK_S2D1),
 228         DEF_MOD("vin7",                  804,   R8A7795_CLK_S0D2),
 229         DEF_MOD("vin6",                  805,   R8A7795_CLK_S0D2),
 230         DEF_MOD("vin5",                  806,   R8A7795_CLK_S0D2),
 231         DEF_MOD("vin4",                  807,   R8A7795_CLK_S0D2),
 232         DEF_MOD("vin3",                  808,   R8A7795_CLK_S0D2),
 233         DEF_MOD("vin2",                  809,   R8A7795_CLK_S0D2),
 234         DEF_MOD("vin1",                  810,   R8A7795_CLK_S0D2),
 235         DEF_MOD("vin0",                  811,   R8A7795_CLK_S0D2),
 236         DEF_MOD("etheravb",              812,   R8A7795_CLK_S0D6),
 237         DEF_MOD("sata0",                 815,   R8A7795_CLK_S3D2),
 238         DEF_MOD("imr3",                  820,   R8A7795_CLK_S0D2),
 239         DEF_MOD("imr2",                  821,   R8A7795_CLK_S0D2),
 240         DEF_MOD("imr1",                  822,   R8A7795_CLK_S0D2),
 241         DEF_MOD("imr0",                  823,   R8A7795_CLK_S0D2),
 242         DEF_MOD("gpio7",                 905,   R8A7795_CLK_S3D4),
 243         DEF_MOD("gpio6",                 906,   R8A7795_CLK_S3D4),
 244         DEF_MOD("gpio5",                 907,   R8A7795_CLK_S3D4),
 245         DEF_MOD("gpio4",                 908,   R8A7795_CLK_S3D4),
 246         DEF_MOD("gpio3",                 909,   R8A7795_CLK_S3D4),
 247         DEF_MOD("gpio2",                 910,   R8A7795_CLK_S3D4),
 248         DEF_MOD("gpio1",                 911,   R8A7795_CLK_S3D4),
 249         DEF_MOD("gpio0",                 912,   R8A7795_CLK_S3D4),
 250         DEF_MOD("can-fd",                914,   R8A7795_CLK_S3D2),
 251         DEF_MOD("can-if1",               915,   R8A7795_CLK_S3D4),
 252         DEF_MOD("can-if0",               916,   R8A7795_CLK_S3D4),
 253         DEF_MOD("rpc-if",                917,   R8A7795_CLK_RPCD2),
 254         DEF_MOD("i2c6",                  918,   R8A7795_CLK_S0D6),
 255         DEF_MOD("i2c5",                  919,   R8A7795_CLK_S0D6),
 256         DEF_MOD("adg",                   922,   R8A7795_CLK_S0D4),
 257         DEF_MOD("i2c-dvfs",              926,   R8A7795_CLK_CP),
 258         DEF_MOD("i2c4",                  927,   R8A7795_CLK_S0D6),
 259         DEF_MOD("i2c3",                  928,   R8A7795_CLK_S0D6),
 260         DEF_MOD("i2c2",                  929,   R8A7795_CLK_S3D2),
 261         DEF_MOD("i2c1",                  930,   R8A7795_CLK_S3D2),
 262         DEF_MOD("i2c0",                  931,   R8A7795_CLK_S3D2),
 263         DEF_MOD("ssi-all",              1005,   R8A7795_CLK_S3D4),
 264         DEF_MOD("ssi9",                 1006,   MOD_CLK_ID(1005)),
 265         DEF_MOD("ssi8",                 1007,   MOD_CLK_ID(1005)),
 266         DEF_MOD("ssi7",                 1008,   MOD_CLK_ID(1005)),
 267         DEF_MOD("ssi6",                 1009,   MOD_CLK_ID(1005)),
 268         DEF_MOD("ssi5",                 1010,   MOD_CLK_ID(1005)),
 269         DEF_MOD("ssi4",                 1011,   MOD_CLK_ID(1005)),
 270         DEF_MOD("ssi3",                 1012,   MOD_CLK_ID(1005)),
 271         DEF_MOD("ssi2",                 1013,   MOD_CLK_ID(1005)),
 272         DEF_MOD("ssi1",                 1014,   MOD_CLK_ID(1005)),
 273         DEF_MOD("ssi0",                 1015,   MOD_CLK_ID(1005)),
 274         DEF_MOD("scu-all",              1017,   R8A7795_CLK_S3D4),
 275         DEF_MOD("scu-dvc1",             1018,   MOD_CLK_ID(1017)),
 276         DEF_MOD("scu-dvc0",             1019,   MOD_CLK_ID(1017)),
 277         DEF_MOD("scu-ctu1-mix1",        1020,   MOD_CLK_ID(1017)),
 278         DEF_MOD("scu-ctu0-mix0",        1021,   MOD_CLK_ID(1017)),
 279         DEF_MOD("scu-src9",             1022,   MOD_CLK_ID(1017)),
 280         DEF_MOD("scu-src8",             1023,   MOD_CLK_ID(1017)),
 281         DEF_MOD("scu-src7",             1024,   MOD_CLK_ID(1017)),
 282         DEF_MOD("scu-src6",             1025,   MOD_CLK_ID(1017)),
 283         DEF_MOD("scu-src5",             1026,   MOD_CLK_ID(1017)),
 284         DEF_MOD("scu-src4",             1027,   MOD_CLK_ID(1017)),
 285         DEF_MOD("scu-src3",             1028,   MOD_CLK_ID(1017)),
 286         DEF_MOD("scu-src2",             1029,   MOD_CLK_ID(1017)),
 287         DEF_MOD("scu-src1",             1030,   MOD_CLK_ID(1017)),
 288         DEF_MOD("scu-src0",             1031,   MOD_CLK_ID(1017)),
 289 };
 290
 291 static const unsigned int r8a7795_crit_mod_clks[] __initconst = {
 292         MOD_CLK_ID(402),        /* RWDT */
 293         MOD_CLK_ID(408),        /* INTC-AP (GIC) */
 294 };
 295
 296 /*
 297  * CPG Clock Data
 298  */
 299
 300 /*
 301  *   MD         EXTAL           PLL0    PLL1    PLL2    PLL3    PLL4    OSC
 302  * 14 13 19 17  (MHz)
 303  *-------------------------------------------------------------------------
 304  * 0  0  0  0   16.66 x 1       x180    x192    x144    x192    x144    /16
 305  * 0  0  0  1   16.66 x 1       x180    x192    x144    x128    x144    /16
 306  * 0  0  1  0   Prohibited setting
 307  * 0  0  1  1   16.66 x 1       x180    x192    x144    x192    x144    /16
 308  * 0  1  0  0   20    x 1       x150    x160    x120    x160    x120    /19
 309  * 0  1  0  1   20    x 1       x150    x160    x120    x106    x120    /19
 310  * 0  1  1  0   Prohibited setting
 311  * 0  1  1  1   20    x 1       x150    x160    x120    x160    x120    /19
 312  * 1  0  0  0   25    x 1       x120    x128    x96     x128    x96     /24
 313  * 1  0  0  1   25    x 1       x120    x128    x96     x84     x96     /24
 314  * 1  0  1  0   Prohibited setting
 315  * 1  0  1  1   25    x 1       x120    x128    x96     x128    x96     /24
 316  * 1  1  0  0   33.33 / 2       x180    x192    x144    x192    x144    /32
 317  * 1  1  0  1   33.33 / 2       x180    x192    x144    x128    x144    /32
 318  * 1  1  1  0   Prohibited setting
 319  * 1  1  1  1   33.33 / 2       x180    x192    x144    x192    x144    /32
 320  */
 321 #define CPG_PLL_CONFIG_INDEX(md)        ((((md) & BIT(14)) >> 11) | \
 322                                          (((md) & BIT(13)) >> 11) | \
 323                                          (((md) & BIT(19)) >> 18) | \
 324                                          (((md) & BIT(17)) >> 17))
 325
 326 static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
 327         /* EXTAL div    PLL1 mult/div   PLL3 mult/div   OSC prediv */
 328         { 1,            192,    1,      192,    1,      16,     },
 329         { 1,            192,    1,      128,    1,      16,     },
 330         { 0, /* Prohibited setting */                           },
 331         { 1,            192,    1,      192,    1,      16,     },
 332         { 1,            160,    1,      160,    1,      19,     },
 333         { 1,            160,    1,      106,    1,      19,     },
 334         { 0, /* Prohibited setting */                           },
 335         { 1,            160,    1,      160,    1,      19,     },
 336         { 1,            128,    1,      128,    1,      24,     },
 337         { 1,            128,    1,      84,     1,      24,     },
 338         { 0, /* Prohibited setting */                           },
 339         { 1,            128,    1,      128,    1,      24,     },
 340         { 2,            192,    1,      192,    1,      32,     },
 341         { 2,            192,    1,      128,    1,      32,     },
 342         { 0, /* Prohibited setting */                           },
 343         { 2,            192,    1,      192,    1,      32,     },
 344 };
 345
 346 static const struct soc_device_attribute r8a7795_denylist[] __initconst = {
 347         { .soc_id = "r8a7795", .revision = "ES1.*" },
 348         { /* sentinel */ }
 349 };
 350
 351 static int __init r8a7795_cpg_mssr_init(struct device *dev)
 352 {
 353         const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
 354         u32 cpg_mode;
 355         int error;
 356
 357         /*
 358          * We panic here to ensure removed SoCs and clk updates are always in
 359          * sync to avoid overclocking damages. The panic can only be seen with
 360          * commandline args 'earlycon keep_bootcon'. But these SoCs were for
 361          * developers only anyhow.
 362          */
 363         if (soc_device_match(r8a7795_denylist))
 364                 panic("SoC not supported anymore!\n");
 365
 366         error = rcar_rst_read_mode_pins(&cpg_mode);
 367         if (error)
 368                 return error;
 369
 370         cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
 371         if (!cpg_pll_config->extal_div) {
 372                 dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode);
 373                 return -EINVAL;
 374         }
 375
 376         return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
 377 }
 378
 379 const struct cpg_mssr_info r8a7795_cpg_mssr_info __initconst = {
 380         /* Core Clocks */
 381         .core_clks = r8a7795_core_clks,
 382         .num_core_clks = ARRAY_SIZE(r8a7795_core_clks),
 383         .last_dt_core_clk = LAST_DT_CORE_CLK,
 384         .num_total_core_clks = MOD_CLK_BASE,
 385
 386         /* Module Clocks */
 387         .mod_clks = r8a7795_mod_clks,
 388         .num_mod_clks = ARRAY_SIZE(r8a7795_mod_clks),
 389         .num_hw_mod_clks = 12 * 32,
 390
 391         /* Critical Module Clocks */
 392         .crit_mod_clks = r8a7795_crit_mod_clks,
 393         .num_crit_mod_clks = ARRAY_SIZE(r8a7795_crit_mod_clks),
 394
 395         /* Callbacks */
 396         .init = r8a7795_cpg_mssr_init,
 397         .cpg_clk_register = rcar_gen3_cpg_clk_register,
 398 };