2 * rcar_gen2 Core CPG Clocks
4 * Copyright (C) 2013 Ideas On Board SPRL
6 * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
13 #include <linux/clk-provider.h>
14 #include <linux/clk/renesas.h>
15 #include <linux/init.h>
16 #include <linux/kernel.h>
17 #include <linux/math64.h>
19 #include <linux/of_address.h>
20 #include <linux/slab.h>
21 #include <linux/spinlock.h>
23 struct rcar_gen2_cpg {
24 struct clk_onecell_data data;
29 #define CPG_FRQCRB 0x00000004
30 #define CPG_FRQCRB_KICK BIT(31)
31 #define CPG_SDCKCR 0x00000074
32 #define CPG_PLL0CR 0x000000d8
33 #define CPG_FRQCRC 0x000000e0
34 #define CPG_FRQCRC_ZFC_MASK (0x1f << 8)
35 #define CPG_FRQCRC_ZFC_SHIFT 8
36 #define CPG_ADSPCKCR 0x0000025c
37 #define CPG_RCANCKCR 0x00000270
39 /* -----------------------------------------------------------------------------
42 * Traits of this clock:
43 * prepare - clk_prepare only ensures that parents are prepared
44 * enable - clk_enable only ensures that parents are enabled
45 * rate - rate is adjustable. clk->rate = parent->rate * mult / 32
46 * parent - fixed parent. No clk_set_parent support
52 void __iomem *kick_reg;
55 #define to_z_clk(_hw) container_of(_hw, struct cpg_z_clk, hw)
57 static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
58 unsigned long parent_rate)
60 struct cpg_z_clk *zclk = to_z_clk(hw);
64 val = (clk_readl(zclk->reg) & CPG_FRQCRC_ZFC_MASK)
65 >> CPG_FRQCRC_ZFC_SHIFT;
68 return div_u64((u64)parent_rate * mult, 32);
71 static long cpg_z_clk_round_rate(struct clk_hw *hw, unsigned long rate,
72 unsigned long *parent_rate)
74 unsigned long prate = *parent_rate;
80 mult = div_u64((u64)rate * 32, prate);
81 mult = clamp(mult, 1U, 32U);
83 return *parent_rate / 32 * mult;
86 static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
87 unsigned long parent_rate)
89 struct cpg_z_clk *zclk = to_z_clk(hw);
94 mult = div_u64((u64)rate * 32, parent_rate);
95 mult = clamp(mult, 1U, 32U);
97 if (clk_readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
100 val = clk_readl(zclk->reg);
101 val &= ~CPG_FRQCRC_ZFC_MASK;
102 val |= (32 - mult) << CPG_FRQCRC_ZFC_SHIFT;
103 clk_writel(val, zclk->reg);
106 * Set KICK bit in FRQCRB to update hardware setting and wait for
107 * clock change completion.
109 kick = clk_readl(zclk->kick_reg);
110 kick |= CPG_FRQCRB_KICK;
111 clk_writel(kick, zclk->kick_reg);
114 * Note: There is no HW information about the worst case latency.
116 * Using experimental measurements, it seems that no more than
117 * ~10 iterations are needed, independently of the CPU rate.
118 * Since this value might be dependent on external xtal rate, pll1
119 * rate or even the other emulation clocks rate, use 1000 as a
120 * "super" safe value.
122 for (i = 1000; i; i--) {
123 if (!(clk_readl(zclk->kick_reg) & CPG_FRQCRB_KICK))
132 static const struct clk_ops cpg_z_clk_ops = {
133 .recalc_rate = cpg_z_clk_recalc_rate,
134 .round_rate = cpg_z_clk_round_rate,
135 .set_rate = cpg_z_clk_set_rate,
138 static struct clk * __init cpg_z_clk_register(struct rcar_gen2_cpg *cpg)
140 static const char *parent_name = "pll0";
141 struct clk_init_data init;
142 struct cpg_z_clk *zclk;
145 zclk = kzalloc(sizeof(*zclk), GFP_KERNEL);
147 return ERR_PTR(-ENOMEM);
150 init.ops = &cpg_z_clk_ops;
152 init.parent_names = &parent_name;
153 init.num_parents = 1;
155 zclk->reg = cpg->reg + CPG_FRQCRC;
156 zclk->kick_reg = cpg->reg + CPG_FRQCRB;
157 zclk->hw.init = &init;
159 clk = clk_register(NULL, &zclk->hw);
166 static struct clk * __init cpg_rcan_clk_register(struct rcar_gen2_cpg *cpg,
167 struct device_node *np)
169 const char *parent_name = of_clk_get_parent_name(np, 1);
170 struct clk_fixed_factor *fixed;
171 struct clk_gate *gate;
174 fixed = kzalloc(sizeof(*fixed), GFP_KERNEL);
176 return ERR_PTR(-ENOMEM);
181 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
184 return ERR_PTR(-ENOMEM);
187 gate->reg = cpg->reg + CPG_RCANCKCR;
189 gate->flags = CLK_GATE_SET_TO_DISABLE;
190 gate->lock = &cpg->lock;
192 clk = clk_register_composite(NULL, "rcan", &parent_name, 1, NULL, NULL,
193 &fixed->hw, &clk_fixed_factor_ops,
194 &gate->hw, &clk_gate_ops, 0);
204 static const struct clk_div_table cpg_adsp_div_table[] = {
205 { 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 },
206 { 5, 12 }, { 6, 16 }, { 7, 18 }, { 8, 24 },
207 { 10, 36 }, { 11, 48 }, { 0, 0 },
210 static struct clk * __init cpg_adsp_clk_register(struct rcar_gen2_cpg *cpg)
212 const char *parent_name = "pll1";
213 struct clk_divider *div;
214 struct clk_gate *gate;
217 div = kzalloc(sizeof(*div), GFP_KERNEL);
219 return ERR_PTR(-ENOMEM);
221 div->reg = cpg->reg + CPG_ADSPCKCR;
223 div->table = cpg_adsp_div_table;
224 div->lock = &cpg->lock;
226 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
229 return ERR_PTR(-ENOMEM);
232 gate->reg = cpg->reg + CPG_ADSPCKCR;
234 gate->flags = CLK_GATE_SET_TO_DISABLE;
235 gate->lock = &cpg->lock;
237 clk = clk_register_composite(NULL, "adsp", &parent_name, 1, NULL, NULL,
238 &div->hw, &clk_divider_ops,
239 &gate->hw, &clk_gate_ops, 0);
248 /* -----------------------------------------------------------------------------
253 * MD EXTAL PLL0 PLL1 PLL3
254 * 14 13 19 (MHz) *1 *1
255 *---------------------------------------------------
256 * 0 0 0 15 x 1 x172/2 x208/2 x106
257 * 0 0 1 15 x 1 x172/2 x208/2 x88
258 * 0 1 0 20 x 1 x130/2 x156/2 x80
259 * 0 1 1 20 x 1 x130/2 x156/2 x66
260 * 1 0 0 26 / 2 x200/2 x240/2 x122
261 * 1 0 1 26 / 2 x200/2 x240/2 x102
262 * 1 1 0 30 / 2 x172/2 x208/2 x106
263 * 1 1 1 30 / 2 x172/2 x208/2 x88
265 * *1 : Table 7.6 indicates VCO output (PLLx = VCO/2)
267 #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
268 (((md) & BIT(13)) >> 12) | \
269 (((md) & BIT(19)) >> 19))
270 struct cpg_pll_config {
271 unsigned int extal_div;
272 unsigned int pll1_mult;
273 unsigned int pll3_mult;
274 unsigned int pll0_mult; /* For R-Car V2H and E2 only */
277 static const struct cpg_pll_config cpg_pll_configs[8] __initconst = {
278 { 1, 208, 106, 200 }, { 1, 208, 88, 200 },
279 { 1, 156, 80, 150 }, { 1, 156, 66, 150 },
280 { 2, 240, 122, 230 }, { 2, 240, 102, 230 },
281 { 2, 208, 106, 200 }, { 2, 208, 88, 200 },
285 static const struct clk_div_table cpg_sdh_div_table[] = {
286 { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 },
287 { 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
288 { 8, 24 }, { 10, 36 }, { 11, 48 }, { 0, 0 },
291 static const struct clk_div_table cpg_sd01_div_table[] = {
293 { 5, 12 }, { 6, 16 }, { 7, 18 }, { 8, 24 },
294 { 10, 36 }, { 11, 48 }, { 12, 10 }, { 0, 0 },
297 /* -----------------------------------------------------------------------------
301 static u32 cpg_mode __initdata;
303 static const char * const pll0_mult_match[] = {
304 "renesas,r8a7792-cpg-clocks",
305 "renesas,r8a7794-cpg-clocks",
309 static struct clk * __init
310 rcar_gen2_cpg_register_clock(struct device_node *np, struct rcar_gen2_cpg *cpg,
311 const struct cpg_pll_config *config,
314 const struct clk_div_table *table = NULL;
315 const char *parent_name;
317 unsigned int mult = 1;
318 unsigned int div = 1;
320 if (!strcmp(name, "main")) {
321 parent_name = of_clk_get_parent_name(np, 0);
322 div = config->extal_div;
323 } else if (!strcmp(name, "pll0")) {
324 /* PLL0 is a configurable multiplier clock. Register it as a
325 * fixed factor clock for now as there's no generic multiplier
326 * clock implementation and we currently have no need to change
327 * the multiplier value.
329 if (of_device_compatible_match(np, pll0_mult_match)) {
330 /* R-Car V2H and E2 do not have PLL0CR */
331 mult = config->pll0_mult;
334 u32 value = clk_readl(cpg->reg + CPG_PLL0CR);
335 mult = ((value >> 24) & ((1 << 7) - 1)) + 1;
337 parent_name = "main";
338 } else if (!strcmp(name, "pll1")) {
339 parent_name = "main";
340 mult = config->pll1_mult / 2;
341 } else if (!strcmp(name, "pll3")) {
342 parent_name = "main";
343 mult = config->pll3_mult;
344 } else if (!strcmp(name, "lb")) {
345 parent_name = "pll1";
346 div = cpg_mode & BIT(18) ? 36 : 24;
347 } else if (!strcmp(name, "qspi")) {
348 parent_name = "pll1_div2";
349 div = (cpg_mode & (BIT(3) | BIT(2) | BIT(1))) == BIT(2)
351 } else if (!strcmp(name, "sdh")) {
352 parent_name = "pll1";
353 table = cpg_sdh_div_table;
355 } else if (!strcmp(name, "sd0")) {
356 parent_name = "pll1";
357 table = cpg_sd01_div_table;
359 } else if (!strcmp(name, "sd1")) {
360 parent_name = "pll1";
361 table = cpg_sd01_div_table;
363 } else if (!strcmp(name, "z")) {
364 return cpg_z_clk_register(cpg);
365 } else if (!strcmp(name, "rcan")) {
366 return cpg_rcan_clk_register(cpg, np);
367 } else if (!strcmp(name, "adsp")) {
368 return cpg_adsp_clk_register(cpg);
370 return ERR_PTR(-EINVAL);
374 return clk_register_fixed_factor(NULL, name, parent_name, 0,
377 return clk_register_divider_table(NULL, name, parent_name, 0,
378 cpg->reg + CPG_SDCKCR, shift,
379 4, 0, table, &cpg->lock);
382 static void __init rcar_gen2_cpg_clocks_init(struct device_node *np)
384 const struct cpg_pll_config *config;
385 struct rcar_gen2_cpg *cpg;
390 num_clks = of_property_count_strings(np, "clock-output-names");
392 pr_err("%s: failed to count clocks\n", __func__);
396 cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
397 clks = kzalloc(num_clks * sizeof(*clks), GFP_KERNEL);
398 if (cpg == NULL || clks == NULL) {
399 /* We're leaking memory on purpose, there's no point in cleaning
400 * up as the system won't boot anyway.
402 pr_err("%s: failed to allocate cpg\n", __func__);
406 spin_lock_init(&cpg->lock);
408 cpg->data.clks = clks;
409 cpg->data.clk_num = num_clks;
411 cpg->reg = of_iomap(np, 0);
412 if (WARN_ON(cpg->reg == NULL))
415 config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
417 for (i = 0; i < num_clks; ++i) {
421 of_property_read_string_index(np, "clock-output-names", i,
424 clk = rcar_gen2_cpg_register_clock(np, cpg, config, name);
426 pr_err("%s: failed to register %s %s clock (%ld)\n",
427 __func__, np->name, name, PTR_ERR(clk));
429 cpg->data.clks[i] = clk;
432 of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
434 cpg_mstp_add_clk_domain(np);
436 CLK_OF_DECLARE(rcar_gen2_cpg_clks, "renesas,rcar-gen2-cpg-clocks",
437 rcar_gen2_cpg_clocks_init);
439 void __init rcar_gen2_clocks_init(u32 mode)