1 // SPDX-License-Identifier: GPL-2.0
3 * r8a7778 Core CPG Clocks
5 * Copyright (C) 2014 Ulrich Hecht
8 #include <linux/clk-provider.h>
9 #include <linux/clk/renesas.h>
10 #include <linux/of_address.h>
11 #include <linux/slab.h>
12 #include <linux/soc/renesas/rcar-rst.h>
14 /* PLL multipliers per bits 11, 12, and 18 of MODEMR */
16 unsigned long plla_mult;
17 unsigned long pllb_mult;
18 } r8a7778_rates[] __initconst = {
28 /* Clock dividers per bits 1 and 2 of MODEMR */
32 } r8a7778_divs[6] __initconst = {
33 { "b", { 12, 12, 16, 18 } },
34 { "out", { 12, 12, 16, 18 } },
35 { "p", { 16, 12, 16, 12 } },
36 { "s", { 4, 3, 4, 3 } },
37 { "s1", { 8, 6, 8, 6 } },
40 static u32 cpg_mode_rates __initdata;
41 static u32 cpg_mode_divs __initdata;
43 static struct clk * __init
44 r8a7778_cpg_register_clock(struct device_node *np, const char *name)
46 if (!strcmp(name, "plla")) {
47 return clk_register_fixed_factor(NULL, "plla",
48 of_clk_get_parent_name(np, 0), 0,
49 r8a7778_rates[cpg_mode_rates].plla_mult, 1);
50 } else if (!strcmp(name, "pllb")) {
51 return clk_register_fixed_factor(NULL, "pllb",
52 of_clk_get_parent_name(np, 0), 0,
53 r8a7778_rates[cpg_mode_rates].pllb_mult, 1);
57 for (i = 0; i < ARRAY_SIZE(r8a7778_divs); i++) {
58 if (!strcmp(name, r8a7778_divs[i].name)) {
59 return clk_register_fixed_factor(NULL,
62 r8a7778_divs[i].div[cpg_mode_divs]);
67 return ERR_PTR(-EINVAL);
71 static void __init r8a7778_cpg_clocks_init(struct device_node *np)
73 struct clk_onecell_data *data;
79 if (rcar_rst_read_mode_pins(&mode))
82 BUG_ON(!(mode & BIT(19)));
84 cpg_mode_rates = (!!(mode & BIT(18)) << 2) |
85 (!!(mode & BIT(12)) << 1) |
87 cpg_mode_divs = (!!(mode & BIT(2)) << 1) |
90 num_clks = of_property_count_strings(np, "clock-output-names");
92 pr_err("%s: failed to count clocks\n", __func__);
96 data = kzalloc(sizeof(*data), GFP_KERNEL);
97 clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);
98 if (data == NULL || clks == NULL) {
99 /* We're leaking memory on purpose, there's no point in cleaning
100 * up as the system won't boot anyway.
106 data->clk_num = num_clks;
108 for (i = 0; i < num_clks; ++i) {
112 of_property_read_string_index(np, "clock-output-names", i,
115 clk = r8a7778_cpg_register_clock(np, name);
117 pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
118 __func__, np, name, PTR_ERR(clk));
123 of_clk_add_provider(np, of_clk_src_onecell_get, data);
125 cpg_mstp_add_clk_domain(np);
128 CLK_OF_DECLARE(r8a7778_cpg_clks, "renesas,r8a7778-cpg-clocks",
129 r8a7778_cpg_clocks_init);