1 // SPDX-License-Identifier: GPL-2.0
3 * r8a73a4 Core CPG Clocks
5 * Copyright (C) 2014 Ulrich Hecht
8 #include <linux/clk-provider.h>
9 #include <linux/clk/renesas.h>
10 #include <linux/init.h>
12 #include <linux/kernel.h>
13 #include <linux/slab.h>
15 #include <linux/of_address.h>
16 #include <linux/spinlock.h>
19 struct clk_onecell_data data;
24 #define CPG_CKSCR 0xc0
25 #define CPG_FRQCRA 0x00
26 #define CPG_FRQCRB 0x04
27 #define CPG_FRQCRC 0xe0
28 #define CPG_PLL0CR 0xd8
29 #define CPG_PLL1CR 0x28
30 #define CPG_PLL2CR 0x2c
31 #define CPG_PLL2HCR 0xe4
32 #define CPG_PLL2SCR 0xf4
34 #define CLK_ENABLE_ON_INIT BIT(0)
42 static struct div4_clk div4_clks[] = {
43 { "i", CPG_FRQCRA, 20 },
44 { "m3", CPG_FRQCRA, 12 },
45 { "b", CPG_FRQCRA, 8 },
46 { "m1", CPG_FRQCRA, 4 },
47 { "m2", CPG_FRQCRA, 0 },
48 { "zx", CPG_FRQCRB, 12 },
49 { "zs", CPG_FRQCRB, 8 },
50 { "hp", CPG_FRQCRB, 4 },
54 static const struct clk_div_table div4_div_table[] = {
55 { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 }, { 5, 12 },
56 { 6, 16 }, { 7, 18 }, { 8, 24 }, { 10, 36 }, { 11, 48 },
60 static struct clk * __init
61 r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg,
64 const struct clk_div_table *table = NULL;
65 const char *parent_name;
66 unsigned int shift, reg;
67 unsigned int mult = 1;
71 if (!strcmp(name, "main")) {
72 u32 ckscr = readl(cpg->reg + CPG_CKSCR);
74 switch ((ckscr >> 28) & 3) {
76 parent_name = of_clk_get_parent_name(np, 0);
78 case 1: /* extal1 / 2 */
79 parent_name = of_clk_get_parent_name(np, 0);
83 parent_name = of_clk_get_parent_name(np, 1);
85 case 3: /* extal2 / 2 */
86 parent_name = of_clk_get_parent_name(np, 1);
90 } else if (!strcmp(name, "pll0")) {
91 /* PLL0/1 are configurable multiplier clocks. Register them as
92 * fixed factor clocks for now as there's no generic multiplier
93 * clock implementation and we currently have no need to change
94 * the multiplier value.
96 u32 value = readl(cpg->reg + CPG_PLL0CR);
99 mult = ((value >> 24) & 0x7f) + 1;
102 } else if (!strcmp(name, "pll1")) {
103 u32 value = readl(cpg->reg + CPG_PLL1CR);
105 parent_name = "main";
106 /* XXX: enable bit? */
107 mult = ((value >> 24) & 0x7f) + 1;
110 } else if (!strncmp(name, "pll2", 4)) {
124 return ERR_PTR(-EINVAL);
126 value = readl(cpg->reg + cr);
127 switch ((value >> 5) & 7) {
129 parent_name = "main";
133 parent_name = "extal2";
137 parent_name = "extal2";
141 parent_name = "main";
144 parent_name = "extal2";
147 pr_warn("%s: unexpected parent of %s\n", __func__,
149 return ERR_PTR(-EINVAL);
151 /* XXX: enable bit? */
152 mult = ((value >> 24) & 0x7f) + 1;
153 } else if (!strcmp(name, "z") || !strcmp(name, "z2")) {
156 parent_name = "pll0";
157 if (name[1] == '2') {
162 mult = 0x20 - ((readl(cpg->reg + CPG_FRQCRC) >> shift) & 0x1f);
166 for (c = div4_clks; c->name; c++) {
167 if (!strcmp(name, c->name))
171 return ERR_PTR(-EINVAL);
173 parent_name = "pll1";
174 table = div4_div_table;
180 return clk_register_fixed_factor(NULL, name, parent_name, 0,
183 return clk_register_divider_table(NULL, name, parent_name, 0,
184 cpg->reg + reg, shift, 4, 0,
189 static void __init r8a73a4_cpg_clocks_init(struct device_node *np)
191 struct r8a73a4_cpg *cpg;
196 num_clks = of_property_count_strings(np, "clock-output-names");
198 pr_err("%s: failed to count clocks\n", __func__);
202 cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
203 clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);
204 if (cpg == NULL || clks == NULL) {
205 /* We're leaking memory on purpose, there's no point in cleaning
206 * up as the system won't boot anyway.
211 spin_lock_init(&cpg->lock);
213 cpg->data.clks = clks;
214 cpg->data.clk_num = num_clks;
216 cpg->reg = of_iomap(np, 0);
217 if (WARN_ON(cpg->reg == NULL))
220 for (i = 0; i < num_clks; ++i) {
224 of_property_read_string_index(np, "clock-output-names", i,
227 clk = r8a73a4_cpg_register_clock(np, cpg, name);
229 pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
230 __func__, np, name, PTR_ERR(clk));
232 cpg->data.clks[i] = clk;
235 of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
237 CLK_OF_DECLARE(r8a73a4_cpg_clks, "renesas,r8a73a4-cpg-clocks",
238 r8a73a4_cpg_clocks_init);