4 * Copyright (C) 2013 Ideas On Board SPRL
5 * Copyright (C) 2015 Glider bvba
7 * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
14 #include <linux/clk.h>
15 #include <linux/clk-provider.h>
16 #include <linux/clkdev.h>
17 #include <linux/clk/renesas.h>
18 #include <linux/device.h>
21 #include <linux/of_address.h>
22 #include <linux/pm_clock.h>
23 #include <linux/pm_domain.h>
24 #include <linux/spinlock.h>
27 * MSTP clocks. We can't use standard gate clocks as we need to poll on the
28 * status register when enabling the clock.
31 #define MSTP_MAX_CLOCKS 32
34 * struct mstp_clock_group - MSTP gating clocks group
36 * @data: clocks in this group
37 * @smstpcr: module stop control register
38 * @mstpsr: module stop status register (optional)
39 * @lock: protects writes to SMSTPCR
40 * @width_8bit: registers are 8-bit, not 32-bit
42 struct mstp_clock_group {
43 struct clk_onecell_data data;
44 void __iomem *smstpcr;
51 * struct mstp_clock - MSTP gating clock
52 * @hw: handle between common and hardware-specific interfaces
53 * @bit_index: control bit index
54 * @group: MSTP clocks group
59 struct mstp_clock_group *group;
62 #define to_mstp_clock(_hw) container_of(_hw, struct mstp_clock, hw)
64 static inline u32 cpg_mstp_read(struct mstp_clock_group *group,
67 return group->width_8bit ? readb(reg) : clk_readl(reg);
70 static inline void cpg_mstp_write(struct mstp_clock_group *group, u32 val,
73 group->width_8bit ? writeb(val, reg) : clk_writel(val, reg);
76 static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
78 struct mstp_clock *clock = to_mstp_clock(hw);
79 struct mstp_clock_group *group = clock->group;
80 u32 bitmask = BIT(clock->bit_index);
85 spin_lock_irqsave(&group->lock, flags);
87 value = cpg_mstp_read(group, group->smstpcr);
92 cpg_mstp_write(group, value, group->smstpcr);
94 spin_unlock_irqrestore(&group->lock, flags);
96 if (!enable || !group->mstpsr)
99 for (i = 1000; i > 0; --i) {
100 if (!(cpg_mstp_read(group, group->mstpsr) & bitmask))
106 pr_err("%s: failed to enable %p[%d]\n", __func__,
107 group->smstpcr, clock->bit_index);
114 static int cpg_mstp_clock_enable(struct clk_hw *hw)
116 return cpg_mstp_clock_endisable(hw, true);
119 static void cpg_mstp_clock_disable(struct clk_hw *hw)
121 cpg_mstp_clock_endisable(hw, false);
124 static int cpg_mstp_clock_is_enabled(struct clk_hw *hw)
126 struct mstp_clock *clock = to_mstp_clock(hw);
127 struct mstp_clock_group *group = clock->group;
131 value = cpg_mstp_read(group, group->mstpsr);
133 value = cpg_mstp_read(group, group->smstpcr);
135 return !(value & BIT(clock->bit_index));
138 static const struct clk_ops cpg_mstp_clock_ops = {
139 .enable = cpg_mstp_clock_enable,
140 .disable = cpg_mstp_clock_disable,
141 .is_enabled = cpg_mstp_clock_is_enabled,
144 static struct clk * __init
145 cpg_mstp_clock_register(const char *name, const char *parent_name,
146 unsigned int index, struct mstp_clock_group *group)
148 struct clk_init_data init;
149 struct mstp_clock *clock;
152 clock = kzalloc(sizeof(*clock), GFP_KERNEL);
154 pr_err("%s: failed to allocate MSTP clock.\n", __func__);
155 return ERR_PTR(-ENOMEM);
159 init.ops = &cpg_mstp_clock_ops;
160 init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT;
161 init.parent_names = &parent_name;
162 init.num_parents = 1;
164 clock->bit_index = index;
165 clock->group = group;
166 clock->hw.init = &init;
168 clk = clk_register(NULL, &clock->hw);
176 static void __init cpg_mstp_clocks_init(struct device_node *np)
178 struct mstp_clock_group *group;
183 group = kzalloc(sizeof(*group), GFP_KERNEL);
184 clks = kmalloc_array(MSTP_MAX_CLOCKS, sizeof(*clks), GFP_KERNEL);
185 if (group == NULL || clks == NULL) {
188 pr_err("%s: failed to allocate group\n", __func__);
192 spin_lock_init(&group->lock);
193 group->data.clks = clks;
195 group->smstpcr = of_iomap(np, 0);
196 group->mstpsr = of_iomap(np, 1);
198 if (group->smstpcr == NULL) {
199 pr_err("%s: failed to remap SMSTPCR\n", __func__);
205 if (of_device_is_compatible(np, "renesas,r7s72100-mstp-clocks"))
206 group->width_8bit = true;
208 for (i = 0; i < MSTP_MAX_CLOCKS; ++i)
209 clks[i] = ERR_PTR(-ENOENT);
211 if (of_find_property(np, "clock-indices", &i))
212 idxname = "clock-indices";
214 idxname = "renesas,clock-indices";
216 for (i = 0; i < MSTP_MAX_CLOCKS; ++i) {
217 const char *parent_name;
222 /* Skip clocks with no name. */
223 ret = of_property_read_string_index(np, "clock-output-names",
225 if (ret < 0 || strlen(name) == 0)
228 parent_name = of_clk_get_parent_name(np, i);
229 ret = of_property_read_u32_index(np, idxname, i, &clkidx);
230 if (parent_name == NULL || ret < 0)
233 if (clkidx >= MSTP_MAX_CLOCKS) {
234 pr_err("%s: invalid clock %s %s index %u\n",
235 __func__, np->name, name, clkidx);
239 clks[clkidx] = cpg_mstp_clock_register(name, parent_name,
241 if (!IS_ERR(clks[clkidx])) {
242 group->data.clk_num = max(group->data.clk_num,
245 * Register a clkdev to let board code retrieve the
246 * clock by name and register aliases for non-DT
249 * FIXME: Remove this when all devices that require a
250 * clock will be instantiated from DT.
252 clk_register_clkdev(clks[clkidx], name, NULL);
254 pr_err("%s: failed to register %s %s clock (%ld)\n",
255 __func__, np->name, name, PTR_ERR(clks[clkidx]));
259 of_clk_add_provider(np, of_clk_src_onecell_get, &group->data);
261 CLK_OF_DECLARE(cpg_mstp_clks, "renesas,cpg-mstp-clocks", cpg_mstp_clocks_init);
263 int cpg_mstp_attach_dev(struct generic_pm_domain *unused, struct device *dev)
265 struct device_node *np = dev->of_node;
266 struct of_phandle_args clkspec;
271 while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
273 if (of_device_is_compatible(clkspec.np,
274 "renesas,cpg-mstp-clocks"))
277 /* BSC on r8a73a4/sh73a0 uses zb_clk instead of an mstp clock */
278 if (!strcmp(clkspec.np->name, "zb_clk"))
281 of_node_put(clkspec.np);
288 clk = of_clk_get_from_provider(&clkspec);
289 of_node_put(clkspec.np);
294 error = pm_clk_create(dev);
296 dev_err(dev, "pm_clk_create failed %d\n", error);
300 error = pm_clk_add_clk(dev, clk);
302 dev_err(dev, "pm_clk_add_clk %pC failed %d\n", clk, error);
315 void cpg_mstp_detach_dev(struct generic_pm_domain *unused, struct device *dev)
317 if (!list_empty(&dev->power.subsys_data->clock_list))
321 void __init cpg_mstp_add_clk_domain(struct device_node *np)
323 struct generic_pm_domain *pd;
326 if (of_property_read_u32(np, "#power-domain-cells", &ncells)) {
327 pr_warn("%s lacks #power-domain-cells\n", np->full_name);
331 pd = kzalloc(sizeof(*pd), GFP_KERNEL);
336 pd->flags = GENPD_FLAG_PM_CLK;
337 pd->attach_dev = cpg_mstp_attach_dev;
338 pd->detach_dev = cpg_mstp_detach_dev;
339 pm_genpd_init(pd, &pm_domain_always_on_gov, false);
341 of_genpd_add_provider_simple(np, pd);