1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013 Ideas On Board SPRL
6 * Copyright (C) 2015 Glider bvba
8 * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
13 #include <linux/clkdev.h>
14 #include <linux/clk/renesas.h>
15 #include <linux/device.h>
17 #include <linux/iopoll.h>
19 #include <linux/of_address.h>
20 #include <linux/pm_clock.h>
21 #include <linux/pm_domain.h>
22 #include <linux/spinlock.h>
25 * MSTP clocks. We can't use standard gate clocks as we need to poll on the
26 * status register when enabling the clock.
29 #define MSTP_MAX_CLOCKS 32
32 * struct mstp_clock_group - MSTP gating clocks group
34 * @data: clock specifier translation for clocks in this group
35 * @smstpcr: module stop control register
36 * @mstpsr: module stop status register (optional)
37 * @lock: protects writes to SMSTPCR
38 * @width_8bit: registers are 8-bit, not 32-bit
39 * @clks: clocks in this group
41 struct mstp_clock_group {
42 struct clk_onecell_data data;
43 void __iomem *smstpcr;
51 * struct mstp_clock - MSTP gating clock
52 * @hw: handle between common and hardware-specific interfaces
53 * @bit_index: control bit index
54 * @group: MSTP clocks group
59 struct mstp_clock_group *group;
62 #define to_mstp_clock(_hw) container_of(_hw, struct mstp_clock, hw)
64 static inline u32 cpg_mstp_read(struct mstp_clock_group *group,
67 return group->width_8bit ? readb(reg) : readl(reg);
70 static inline void cpg_mstp_write(struct mstp_clock_group *group, u32 val,
73 group->width_8bit ? writeb(val, reg) : writel(val, reg);
76 static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
78 struct mstp_clock *clock = to_mstp_clock(hw);
79 struct mstp_clock_group *group = clock->group;
80 u32 bitmask = BIT(clock->bit_index);
85 spin_lock_irqsave(&group->lock, flags);
87 value = cpg_mstp_read(group, group->smstpcr);
92 cpg_mstp_write(group, value, group->smstpcr);
95 /* dummy read to ensure write has completed */
96 cpg_mstp_read(group, group->smstpcr);
97 barrier_data(group->smstpcr);
100 spin_unlock_irqrestore(&group->lock, flags);
102 if (!enable || !group->mstpsr)
105 /* group->width_8bit is always false if group->mstpsr is present */
106 ret = readl_poll_timeout_atomic(group->mstpsr, value,
107 !(value & bitmask), 0, 10);
109 pr_err("%s: failed to enable %p[%d]\n", __func__,
110 group->smstpcr, clock->bit_index);
115 static int cpg_mstp_clock_enable(struct clk_hw *hw)
117 return cpg_mstp_clock_endisable(hw, true);
120 static void cpg_mstp_clock_disable(struct clk_hw *hw)
122 cpg_mstp_clock_endisable(hw, false);
125 static int cpg_mstp_clock_is_enabled(struct clk_hw *hw)
127 struct mstp_clock *clock = to_mstp_clock(hw);
128 struct mstp_clock_group *group = clock->group;
132 value = cpg_mstp_read(group, group->mstpsr);
134 value = cpg_mstp_read(group, group->smstpcr);
136 return !(value & BIT(clock->bit_index));
139 static const struct clk_ops cpg_mstp_clock_ops = {
140 .enable = cpg_mstp_clock_enable,
141 .disable = cpg_mstp_clock_disable,
142 .is_enabled = cpg_mstp_clock_is_enabled,
145 static struct clk * __init cpg_mstp_clock_register(const char *name,
146 const char *parent_name, unsigned int index,
147 struct mstp_clock_group *group)
149 struct clk_init_data init = {};
150 struct mstp_clock *clock;
153 clock = kzalloc(sizeof(*clock), GFP_KERNEL);
155 return ERR_PTR(-ENOMEM);
158 init.ops = &cpg_mstp_clock_ops;
159 init.flags = CLK_SET_RATE_PARENT;
160 /* INTC-SYS is the module clock of the GIC, and must not be disabled */
161 if (!strcmp(name, "intc-sys")) {
162 pr_debug("MSTP %s setting CLK_IS_CRITICAL\n", name);
163 init.flags |= CLK_IS_CRITICAL;
165 init.parent_names = &parent_name;
166 init.num_parents = 1;
168 clock->bit_index = index;
169 clock->group = group;
170 clock->hw.init = &init;
172 clk = clk_register(NULL, &clock->hw);
180 static void __init cpg_mstp_clocks_init(struct device_node *np)
182 struct mstp_clock_group *group;
187 group = kzalloc(struct_size(group, clks, MSTP_MAX_CLOCKS), GFP_KERNEL);
192 spin_lock_init(&group->lock);
193 group->data.clks = clks;
195 group->smstpcr = of_iomap(np, 0);
196 group->mstpsr = of_iomap(np, 1);
198 if (group->smstpcr == NULL) {
199 pr_err("%s: failed to remap SMSTPCR\n", __func__);
204 if (of_device_is_compatible(np, "renesas,r7s72100-mstp-clocks"))
205 group->width_8bit = true;
207 for (i = 0; i < MSTP_MAX_CLOCKS; ++i)
208 clks[i] = ERR_PTR(-ENOENT);
210 if (of_find_property(np, "clock-indices", &i))
211 idxname = "clock-indices";
213 idxname = "renesas,clock-indices";
215 for (i = 0; i < MSTP_MAX_CLOCKS; ++i) {
216 const char *parent_name;
221 /* Skip clocks with no name. */
222 ret = of_property_read_string_index(np, "clock-output-names",
224 if (ret < 0 || strlen(name) == 0)
227 parent_name = of_clk_get_parent_name(np, i);
228 ret = of_property_read_u32_index(np, idxname, i, &clkidx);
229 if (parent_name == NULL || ret < 0)
232 if (clkidx >= MSTP_MAX_CLOCKS) {
233 pr_err("%s: invalid clock %pOFn %s index %u\n",
234 __func__, np, name, clkidx);
238 clks[clkidx] = cpg_mstp_clock_register(name, parent_name,
240 if (!IS_ERR(clks[clkidx])) {
241 group->data.clk_num = max(group->data.clk_num,
244 * Register a clkdev to let board code retrieve the
245 * clock by name and register aliases for non-DT
248 * FIXME: Remove this when all devices that require a
249 * clock will be instantiated from DT.
251 clk_register_clkdev(clks[clkidx], name, NULL);
253 pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
254 __func__, np, name, PTR_ERR(clks[clkidx]));
258 of_clk_add_provider(np, of_clk_src_onecell_get, &group->data);
260 CLK_OF_DECLARE(cpg_mstp_clks, "renesas,cpg-mstp-clocks", cpg_mstp_clocks_init);
262 int cpg_mstp_attach_dev(struct generic_pm_domain *unused, struct device *dev)
264 struct device_node *np = dev->of_node;
265 struct of_phandle_args clkspec;
270 while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
272 if (of_device_is_compatible(clkspec.np,
273 "renesas,cpg-mstp-clocks"))
276 /* BSC on r8a73a4/sh73a0 uses zb_clk instead of an mstp clock */
277 if (of_node_name_eq(clkspec.np, "zb_clk"))
280 of_node_put(clkspec.np);
287 clk = of_clk_get_from_provider(&clkspec);
288 of_node_put(clkspec.np);
293 error = pm_clk_create(dev);
297 error = pm_clk_add_clk(dev, clk);
310 void cpg_mstp_detach_dev(struct generic_pm_domain *unused, struct device *dev)
312 if (!pm_clk_no_clocks(dev))
316 void __init cpg_mstp_add_clk_domain(struct device_node *np)
318 struct generic_pm_domain *pd;
321 if (of_property_read_u32(np, "#power-domain-cells", &ncells)) {
322 pr_warn("%pOF lacks #power-domain-cells\n", np);
326 pd = kzalloc(sizeof(*pd), GFP_KERNEL);
331 pd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |
332 GENPD_FLAG_ACTIVE_WAKEUP;
333 pd->attach_dev = cpg_mstp_attach_dev;
334 pd->detach_dev = cpg_mstp_detach_dev;
335 pm_genpd_init(pd, &pm_domain_always_on_gov, false);
337 of_genpd_add_provider_simple(np, pd);