1 // SPDX-License-Identifier: GPL-2.0
3 * r8a7790 Common Clock Framework support
5 * Copyright (C) 2013 Renesas Solutions Corp.
7 * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10 #include <linux/clk-provider.h>
11 #include <linux/init.h>
13 #include <linux/kernel.h>
14 #include <linux/notifier.h>
16 #include <linux/of_address.h>
18 #include <linux/slab.h>
22 #define CPG_DIV6_CKSTP BIT(8)
23 #define CPG_DIV6_DIV(d) ((d) & 0x3f)
24 #define CPG_DIV6_DIV_MASK 0x3f
27 * struct div6_clock - CPG 6 bit divider clock
28 * @hw: handle between common and hardware-specific interfaces
29 * @reg: IO-remapped register
30 * @div: divisor value (1-64)
31 * @src_shift: Shift to access the register bits to select the parent clock
32 * @src_width: Number of register bits to select the parent clock (may be 0)
33 * @nb: Notifier block to save/restore clock state for system resume
34 * @parents: Array to map from valid parent clocks indices to hardware indices
42 struct notifier_block nb;
46 #define to_div6_clock(_hw) container_of(_hw, struct div6_clock, hw)
48 static int cpg_div6_clock_enable(struct clk_hw *hw)
50 struct div6_clock *clock = to_div6_clock(hw);
53 val = (readl(clock->reg) & ~(CPG_DIV6_DIV_MASK | CPG_DIV6_CKSTP))
54 | CPG_DIV6_DIV(clock->div - 1);
55 writel(val, clock->reg);
60 static void cpg_div6_clock_disable(struct clk_hw *hw)
62 struct div6_clock *clock = to_div6_clock(hw);
65 val = readl(clock->reg);
66 val |= CPG_DIV6_CKSTP;
68 * DIV6 clocks require the divisor field to be non-zero when stopping
69 * the clock. However, some clocks (e.g. ZB on sh73a0) fail to be
70 * re-enabled later if the divisor field is changed when stopping the
73 if (!(val & CPG_DIV6_DIV_MASK))
74 val |= CPG_DIV6_DIV_MASK;
75 writel(val, clock->reg);
78 static int cpg_div6_clock_is_enabled(struct clk_hw *hw)
80 struct div6_clock *clock = to_div6_clock(hw);
82 return !(readl(clock->reg) & CPG_DIV6_CKSTP);
85 static unsigned long cpg_div6_clock_recalc_rate(struct clk_hw *hw,
86 unsigned long parent_rate)
88 struct div6_clock *clock = to_div6_clock(hw);
90 return parent_rate / clock->div;
93 static unsigned int cpg_div6_clock_calc_div(unsigned long rate,
94 unsigned long parent_rate)
101 div = DIV_ROUND_CLOSEST(parent_rate, rate);
102 return clamp_t(unsigned int, div, 1, 64);
105 static long cpg_div6_clock_round_rate(struct clk_hw *hw, unsigned long rate,
106 unsigned long *parent_rate)
108 unsigned int div = cpg_div6_clock_calc_div(rate, *parent_rate);
110 return *parent_rate / div;
113 static int cpg_div6_clock_set_rate(struct clk_hw *hw, unsigned long rate,
114 unsigned long parent_rate)
116 struct div6_clock *clock = to_div6_clock(hw);
117 unsigned int div = cpg_div6_clock_calc_div(rate, parent_rate);
122 val = readl(clock->reg) & ~CPG_DIV6_DIV_MASK;
123 /* Only program the new divisor if the clock isn't stopped. */
124 if (!(val & CPG_DIV6_CKSTP))
125 writel(val | CPG_DIV6_DIV(clock->div - 1), clock->reg);
130 static u8 cpg_div6_clock_get_parent(struct clk_hw *hw)
132 struct div6_clock *clock = to_div6_clock(hw);
136 if (clock->src_width == 0)
139 hw_index = (readl(clock->reg) >> clock->src_shift) &
140 (BIT(clock->src_width) - 1);
141 for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
142 if (clock->parents[i] == hw_index)
146 pr_err("%s: %s DIV6 clock set to invalid parent %u\n",
147 __func__, clk_hw_get_name(hw), hw_index);
151 static int cpg_div6_clock_set_parent(struct clk_hw *hw, u8 index)
153 struct div6_clock *clock = to_div6_clock(hw);
157 if (index >= clk_hw_get_num_parents(hw))
160 mask = ~((BIT(clock->src_width) - 1) << clock->src_shift);
161 hw_index = clock->parents[index];
163 writel((readl(clock->reg) & mask) | (hw_index << clock->src_shift),
169 static const struct clk_ops cpg_div6_clock_ops = {
170 .enable = cpg_div6_clock_enable,
171 .disable = cpg_div6_clock_disable,
172 .is_enabled = cpg_div6_clock_is_enabled,
173 .get_parent = cpg_div6_clock_get_parent,
174 .set_parent = cpg_div6_clock_set_parent,
175 .recalc_rate = cpg_div6_clock_recalc_rate,
176 .round_rate = cpg_div6_clock_round_rate,
177 .set_rate = cpg_div6_clock_set_rate,
180 static int cpg_div6_clock_notifier_call(struct notifier_block *nb,
181 unsigned long action, void *data)
183 struct div6_clock *clock = container_of(nb, struct div6_clock, nb);
186 case PM_EVENT_RESUME:
188 * TODO: This does not yet support DIV6 clocks with multiple
189 * parents, as the parent selection bits are not restored.
190 * Fortunately so far such DIV6 clocks are found only on
191 * R/SH-Mobile SoCs, while the resume functionality is only
192 * needed on R-Car Gen3.
194 if (__clk_get_enable_count(clock->hw.clk))
195 cpg_div6_clock_enable(&clock->hw);
197 cpg_div6_clock_disable(&clock->hw);
205 * cpg_div6_register - Register a DIV6 clock
206 * @name: Name of the DIV6 clock
207 * @num_parents: Number of parent clocks of the DIV6 clock (1, 4, or 8)
208 * @parent_names: Array containing the names of the parent clocks
209 * @reg: Mapped register used to control the DIV6 clock
210 * @notifiers: Optional notifier chain to save/restore state for system resume
212 struct clk * __init cpg_div6_register(const char *name,
213 unsigned int num_parents,
214 const char **parent_names,
216 struct raw_notifier_head *notifiers)
218 unsigned int valid_parents;
219 struct clk_init_data init;
220 struct div6_clock *clock;
224 clock = kzalloc(struct_size(clock, parents, num_parents), GFP_KERNEL);
226 return ERR_PTR(-ENOMEM);
231 * Read the divisor. Disabling the clock overwrites the divisor, so we
232 * need to cache its value for the enable operation.
234 clock->div = (readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1;
236 switch (num_parents) {
238 /* fixed parent clock */
239 clock->src_shift = clock->src_width = 0;
242 /* clock with EXSRC bits 6-7 */
243 clock->src_shift = 6;
244 clock->src_width = 2;
247 /* VCLK with EXSRC bits 12-14 */
248 clock->src_shift = 12;
249 clock->src_width = 3;
252 pr_err("%s: invalid number of parents for DIV6 clock %s\n",
254 clk = ERR_PTR(-EINVAL);
258 /* Filter out invalid parents */
259 for (i = 0, valid_parents = 0; i < num_parents; i++) {
260 if (parent_names[i]) {
261 parent_names[valid_parents] = parent_names[i];
262 clock->parents[valid_parents] = i;
267 /* Register the clock. */
269 init.ops = &cpg_div6_clock_ops;
271 init.parent_names = parent_names;
272 init.num_parents = valid_parents;
274 clock->hw.init = &init;
276 clk = clk_register(NULL, &clock->hw);
281 clock->nb.notifier_call = cpg_div6_clock_notifier_call;
282 raw_notifier_chain_register(notifiers, &clock->nb);
292 static void __init cpg_div6_clock_init(struct device_node *np)
294 unsigned int num_parents;
295 const char **parent_names;
296 const char *clk_name = np->name;
301 num_parents = of_clk_get_parent_count(np);
302 if (num_parents < 1) {
303 pr_err("%s: no parent found for %pOFn DIV6 clock\n",
308 parent_names = kmalloc_array(num_parents, sizeof(*parent_names),
313 reg = of_iomap(np, 0);
315 pr_err("%s: failed to map %pOFn DIV6 clock register\n",
320 /* Parse the DT properties. */
321 of_property_read_string(np, "clock-output-names", &clk_name);
323 for (i = 0; i < num_parents; i++)
324 parent_names[i] = of_clk_get_parent_name(np, i);
326 clk = cpg_div6_register(clk_name, num_parents, parent_names, reg, NULL);
328 pr_err("%s: failed to register %pOFn DIV6 clock (%ld)\n",
329 __func__, np, PTR_ERR(clk));
333 of_clk_add_provider(np, of_clk_src_simple_get, clk);
343 CLK_OF_DECLARE(cpg_div6_clk, "renesas,cpg-div6-clock", cpg_div6_clock_init);