1 // SPDX-License-Identifier: GPL-2.0
3 * MTMIPS SoCs Clock Driver
4 * Author: Sergio Paracuellos <sergio.paracuellos@gmail.com>
7 #include <linux/bitops.h>
8 #include <linux/clk-provider.h>
9 #include <linux/mfd/syscon.h>
10 #include <linux/platform_device.h>
11 #include <linux/regmap.h>
12 #include <linux/reset-controller.h>
13 #include <linux/slab.h>
15 /* Configuration registers */
16 #define SYSC_REG_SYSTEM_CONFIG 0x10
17 #define SYSC_REG_CLKCFG0 0x2c
18 #define SYSC_REG_RESET_CTRL 0x34
19 #define SYSC_REG_CPU_SYS_CLKCFG 0x3c
20 #define SYSC_REG_CPLL_CONFIG0 0x54
21 #define SYSC_REG_CPLL_CONFIG1 0x58
24 #define RT2880_CONFIG_CPUCLK_SHIFT 20
25 #define RT2880_CONFIG_CPUCLK_MASK 0x3
26 #define RT2880_CONFIG_CPUCLK_250 0x0
27 #define RT2880_CONFIG_CPUCLK_266 0x1
28 #define RT2880_CONFIG_CPUCLK_280 0x2
29 #define RT2880_CONFIG_CPUCLK_300 0x3
32 #define RT305X_SYSCFG_CPUCLK_SHIFT 18
33 #define RT305X_SYSCFG_CPUCLK_MASK 0x1
34 #define RT305X_SYSCFG_CPUCLK_LOW 0x0
35 #define RT305X_SYSCFG_CPUCLK_HIGH 0x1
38 #define RT3352_SYSCFG0_CPUCLK_SHIFT 8
39 #define RT3352_SYSCFG0_CPUCLK_MASK 0x1
40 #define RT3352_SYSCFG0_CPUCLK_LOW 0x0
41 #define RT3352_SYSCFG0_CPUCLK_HIGH 0x1
44 #define RT3883_SYSCFG0_DRAM_TYPE_DDR2 BIT(17)
45 #define RT3883_SYSCFG0_CPUCLK_SHIFT 8
46 #define RT3883_SYSCFG0_CPUCLK_MASK 0x3
47 #define RT3883_SYSCFG0_CPUCLK_250 0x0
48 #define RT3883_SYSCFG0_CPUCLK_384 0x1
49 #define RT3883_SYSCFG0_CPUCLK_480 0x2
50 #define RT3883_SYSCFG0_CPUCLK_500 0x3
53 #define RT5350_CLKCFG0_XTAL_SEL BIT(20)
54 #define RT5350_SYSCFG0_CPUCLK_SHIFT 8
55 #define RT5350_SYSCFG0_CPUCLK_MASK 0x3
56 #define RT5350_SYSCFG0_CPUCLK_360 0x0
57 #define RT5350_SYSCFG0_CPUCLK_320 0x2
58 #define RT5350_SYSCFG0_CPUCLK_300 0x3
60 /* MT7620 and MT76x8 SoCs */
61 #define MT7620_XTAL_FREQ_SEL BIT(6)
62 #define CPLL_CFG0_SW_CFG BIT(31)
63 #define CPLL_CFG0_PLL_MULT_RATIO_SHIFT 16
64 #define CPLL_CFG0_PLL_MULT_RATIO_MASK 0x7
65 #define CPLL_CFG0_LC_CURFCK BIT(15)
66 #define CPLL_CFG0_BYPASS_REF_CLK BIT(14)
67 #define CPLL_CFG0_PLL_DIV_RATIO_SHIFT 10
68 #define CPLL_CFG0_PLL_DIV_RATIO_MASK 0x3
69 #define CPLL_CFG1_CPU_AUX1 BIT(25)
70 #define CPLL_CFG1_CPU_AUX0 BIT(24)
71 #define CLKCFG0_PERI_CLK_SEL BIT(4)
72 #define CPU_SYS_CLKCFG_OCP_RATIO_SHIFT 16
73 #define CPU_SYS_CLKCFG_OCP_RATIO_MASK 0xf
74 #define CPU_SYS_CLKCFG_OCP_RATIO_1 0 /* 1:1 (Reserved) */
75 #define CPU_SYS_CLKCFG_OCP_RATIO_1_5 1 /* 1:1.5 (Reserved) */
76 #define CPU_SYS_CLKCFG_OCP_RATIO_2 2 /* 1:2 */
77 #define CPU_SYS_CLKCFG_OCP_RATIO_2_5 3 /* 1:2.5 (Reserved) */
78 #define CPU_SYS_CLKCFG_OCP_RATIO_3 4 /* 1:3 */
79 #define CPU_SYS_CLKCFG_OCP_RATIO_3_5 5 /* 1:3.5 (Reserved) */
80 #define CPU_SYS_CLKCFG_OCP_RATIO_4 6 /* 1:4 */
81 #define CPU_SYS_CLKCFG_OCP_RATIO_5 7 /* 1:5 */
82 #define CPU_SYS_CLKCFG_OCP_RATIO_10 8 /* 1:10 */
83 #define CPU_SYS_CLKCFG_CPU_FDIV_SHIFT 8
84 #define CPU_SYS_CLKCFG_CPU_FDIV_MASK 0x1f
85 #define CPU_SYS_CLKCFG_CPU_FFRAC_SHIFT 0
86 #define CPU_SYS_CLKCFG_CPU_FFRAC_MASK 0x1f
89 #define CLKCFG_FDIV_MASK 0x1f00
90 #define CLKCFG_FDIV_USB_VAL 0x0300
91 #define CLKCFG_FFRAC_MASK 0x001f
92 #define CLKCFG_FFRAC_USB_VAL 0x0003
95 struct mtmips_clk_fixed;
96 struct mtmips_clk_factor;
98 struct mtmips_clk_data {
99 struct mtmips_clk *clk_base;
101 struct mtmips_clk_fixed *clk_fixed;
102 size_t num_clk_fixed;
103 struct mtmips_clk_factor *clk_factor;
104 size_t num_clk_factor;
105 struct mtmips_clk *clk_periph;
106 size_t num_clk_periph;
109 struct mtmips_clk_priv {
111 const struct mtmips_clk_data *data;
116 struct mtmips_clk_priv *priv;
119 struct mtmips_clk_fixed {
126 struct mtmips_clk_factor {
135 static unsigned long mtmips_pherip_clk_rate(struct clk_hw *hw,
136 unsigned long parent_rate)
141 static const struct clk_ops mtmips_periph_clk_ops = {
142 .recalc_rate = mtmips_pherip_clk_rate,
145 #define CLK_PERIPH(_name, _parent) { \
146 .init = &(const struct clk_init_data) { \
148 .ops = &mtmips_periph_clk_ops, \
149 .parent_data = &(const struct clk_parent_data) {\
155 * There are drivers for these SoCs that are \
156 * older than clock driver and are not prepared \
157 * for the clock. We don't want the kernel to \
158 * disable anything so we add CLK_IS_CRITICAL \
161 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL \
165 static struct mtmips_clk rt2880_pherip_clks[] = {
166 { CLK_PERIPH("300100.timer", "bus") },
167 { CLK_PERIPH("300120.watchdog", "bus") },
168 { CLK_PERIPH("300500.uart", "bus") },
169 { CLK_PERIPH("300900.i2c", "bus") },
170 { CLK_PERIPH("300c00.uartlite", "bus") },
171 { CLK_PERIPH("400000.ethernet", "bus") },
172 { CLK_PERIPH("480000.wmac", "xtal") }
175 static struct mtmips_clk rt305x_pherip_clks[] = {
176 { CLK_PERIPH("10000100.timer", "bus") },
177 { CLK_PERIPH("10000120.watchdog", "bus") },
178 { CLK_PERIPH("10000500.uart", "bus") },
179 { CLK_PERIPH("10000900.i2c", "bus") },
180 { CLK_PERIPH("10000a00.i2s", "bus") },
181 { CLK_PERIPH("10000b00.spi", "bus") },
182 { CLK_PERIPH("10000b40.spi", "bus") },
183 { CLK_PERIPH("10000c00.uartlite", "bus") },
184 { CLK_PERIPH("10100000.ethernet", "bus") },
185 { CLK_PERIPH("10180000.wmac", "xtal") }
188 static struct mtmips_clk rt5350_pherip_clks[] = {
189 { CLK_PERIPH("10000100.timer", "bus") },
190 { CLK_PERIPH("10000120.watchdog", "bus") },
191 { CLK_PERIPH("10000500.uart", "periph") },
192 { CLK_PERIPH("10000900.i2c", "periph") },
193 { CLK_PERIPH("10000a00.i2s", "periph") },
194 { CLK_PERIPH("10000b00.spi", "bus") },
195 { CLK_PERIPH("10000b40.spi", "bus") },
196 { CLK_PERIPH("10000c00.uartlite", "periph") },
197 { CLK_PERIPH("10100000.ethernet", "bus") },
198 { CLK_PERIPH("10180000.wmac", "xtal") }
201 static struct mtmips_clk mt7620_pherip_clks[] = {
202 { CLK_PERIPH("10000100.timer", "periph") },
203 { CLK_PERIPH("10000120.watchdog", "periph") },
204 { CLK_PERIPH("10000500.uart", "periph") },
205 { CLK_PERIPH("10000900.i2c", "periph") },
206 { CLK_PERIPH("10000a00.i2s", "periph") },
207 { CLK_PERIPH("10000b00.spi", "bus") },
208 { CLK_PERIPH("10000b40.spi", "bus") },
209 { CLK_PERIPH("10000c00.uartlite", "periph") },
210 { CLK_PERIPH("10180000.wmac", "xtal") }
213 static struct mtmips_clk mt76x8_pherip_clks[] = {
214 { CLK_PERIPH("10000100.timer", "periph") },
215 { CLK_PERIPH("10000120.watchdog", "periph") },
216 { CLK_PERIPH("10000900.i2c", "periph") },
217 { CLK_PERIPH("10000a00.i2s", "pcmi2s") },
218 { CLK_PERIPH("10000b00.spi", "bus") },
219 { CLK_PERIPH("10000b40.spi", "bus") },
220 { CLK_PERIPH("10000c00.uart0", "periph") },
221 { CLK_PERIPH("10000d00.uart1", "periph") },
222 { CLK_PERIPH("10000e00.uart2", "periph") },
223 { CLK_PERIPH("10300000.wmac", "xtal") }
226 static int mtmips_register_pherip_clocks(struct device_node *np,
227 struct clk_hw_onecell_data *clk_data,
228 struct mtmips_clk_priv *priv)
230 struct clk_hw **hws = clk_data->hws;
231 struct mtmips_clk *sclk;
232 size_t idx_start = priv->data->num_clk_base + priv->data->num_clk_fixed +
233 priv->data->num_clk_factor;
236 for (i = 0; i < priv->data->num_clk_periph; i++) {
237 int idx = idx_start + i;
239 sclk = &priv->data->clk_periph[i];
240 ret = of_clk_hw_register(np, &sclk->hw);
242 pr_err("Couldn't register peripheral clock %d\n", idx);
246 hws[idx] = &sclk->hw;
253 sclk = &priv->data->clk_periph[i];
254 clk_hw_unregister(&sclk->hw);
259 #define CLK_FIXED(_name, _parent, _rate) \
266 static struct mtmips_clk_fixed rt305x_fixed_clocks[] = {
267 CLK_FIXED("xtal", NULL, 40000000)
270 static struct mtmips_clk_fixed rt3352_fixed_clocks[] = {
271 CLK_FIXED("periph", "xtal", 40000000)
274 static struct mtmips_clk_fixed mt76x8_fixed_clocks[] = {
275 CLK_FIXED("pcmi2s", "xtal", 480000000),
276 CLK_FIXED("periph", "xtal", 40000000)
279 static int mtmips_register_fixed_clocks(struct clk_hw_onecell_data *clk_data,
280 struct mtmips_clk_priv *priv)
282 struct clk_hw **hws = clk_data->hws;
283 struct mtmips_clk_fixed *sclk;
284 size_t idx_start = priv->data->num_clk_base;
287 for (i = 0; i < priv->data->num_clk_fixed; i++) {
288 int idx = idx_start + i;
290 sclk = &priv->data->clk_fixed[i];
291 sclk->hw = clk_hw_register_fixed_rate(NULL, sclk->name,
294 if (IS_ERR(sclk->hw)) {
295 ret = PTR_ERR(sclk->hw);
296 pr_err("Couldn't register fixed clock %d\n", idx);
307 sclk = &priv->data->clk_fixed[i];
308 clk_hw_unregister_fixed_rate(sclk->hw);
313 #define CLK_FACTOR(_name, _parent, _mult, _div) \
319 .flags = CLK_SET_RATE_PARENT \
322 static struct mtmips_clk_factor rt2880_factor_clocks[] = {
323 CLK_FACTOR("bus", "cpu", 1, 2)
326 static struct mtmips_clk_factor rt305x_factor_clocks[] = {
327 CLK_FACTOR("bus", "cpu", 1, 3)
330 static int mtmips_register_factor_clocks(struct clk_hw_onecell_data *clk_data,
331 struct mtmips_clk_priv *priv)
333 struct clk_hw **hws = clk_data->hws;
334 struct mtmips_clk_factor *sclk;
335 size_t idx_start = priv->data->num_clk_base + priv->data->num_clk_fixed;
338 for (i = 0; i < priv->data->num_clk_factor; i++) {
339 int idx = idx_start + i;
341 sclk = &priv->data->clk_factor[i];
342 sclk->hw = clk_hw_register_fixed_factor(NULL, sclk->name,
343 sclk->parent, sclk->flags,
344 sclk->mult, sclk->div);
345 if (IS_ERR(sclk->hw)) {
346 ret = PTR_ERR(sclk->hw);
347 pr_err("Couldn't register factor clock %d\n", idx);
358 sclk = &priv->data->clk_factor[i];
359 clk_hw_unregister_fixed_factor(sclk->hw);
364 static inline struct mtmips_clk *to_mtmips_clk(struct clk_hw *hw)
366 return container_of(hw, struct mtmips_clk, hw);
369 static unsigned long rt5350_xtal_recalc_rate(struct clk_hw *hw,
370 unsigned long parent_rate)
372 struct mtmips_clk *clk = to_mtmips_clk(hw);
373 struct regmap *sysc = clk->priv->sysc;
376 regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &val);
377 if (!(val & RT5350_CLKCFG0_XTAL_SEL))
383 static unsigned long rt5350_cpu_recalc_rate(struct clk_hw *hw,
384 unsigned long xtal_clk)
386 struct mtmips_clk *clk = to_mtmips_clk(hw);
387 struct regmap *sysc = clk->priv->sysc;
390 regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t);
391 t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) & RT5350_SYSCFG0_CPUCLK_MASK;
394 case RT5350_SYSCFG0_CPUCLK_360:
396 case RT5350_SYSCFG0_CPUCLK_320:
398 case RT5350_SYSCFG0_CPUCLK_300:
405 static unsigned long rt5350_bus_recalc_rate(struct clk_hw *hw,
406 unsigned long parent_rate)
408 if (parent_rate == 320000000)
409 return parent_rate / 4;
411 return parent_rate / 3;
414 static unsigned long rt3352_cpu_recalc_rate(struct clk_hw *hw,
415 unsigned long xtal_clk)
417 struct mtmips_clk *clk = to_mtmips_clk(hw);
418 struct regmap *sysc = clk->priv->sysc;
421 regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t);
422 t = (t >> RT3352_SYSCFG0_CPUCLK_SHIFT) & RT3352_SYSCFG0_CPUCLK_MASK;
425 case RT3352_SYSCFG0_CPUCLK_LOW:
427 case RT3352_SYSCFG0_CPUCLK_HIGH:
434 static unsigned long rt305x_cpu_recalc_rate(struct clk_hw *hw,
435 unsigned long xtal_clk)
437 struct mtmips_clk *clk = to_mtmips_clk(hw);
438 struct regmap *sysc = clk->priv->sysc;
441 regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t);
442 t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) & RT305X_SYSCFG_CPUCLK_MASK;
445 case RT305X_SYSCFG_CPUCLK_LOW:
447 case RT305X_SYSCFG_CPUCLK_HIGH:
454 static unsigned long rt3883_cpu_recalc_rate(struct clk_hw *hw,
455 unsigned long xtal_clk)
457 struct mtmips_clk *clk = to_mtmips_clk(hw);
458 struct regmap *sysc = clk->priv->sysc;
461 regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t);
462 t = (t >> RT3883_SYSCFG0_CPUCLK_SHIFT) & RT3883_SYSCFG0_CPUCLK_MASK;
465 case RT3883_SYSCFG0_CPUCLK_250:
467 case RT3883_SYSCFG0_CPUCLK_384:
469 case RT3883_SYSCFG0_CPUCLK_480:
471 case RT3883_SYSCFG0_CPUCLK_500:
478 static unsigned long rt3883_bus_recalc_rate(struct clk_hw *hw,
479 unsigned long parent_rate)
481 struct mtmips_clk *clk = to_mtmips_clk(hw);
482 struct regmap *sysc = clk->priv->sysc;
486 regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t);
487 ddr2 = t & RT3883_SYSCFG0_DRAM_TYPE_DDR2;
489 switch (parent_rate) {
491 return (ddr2) ? 125000000 : 83000000;
493 return (ddr2) ? 128000000 : 96000000;
495 return (ddr2) ? 160000000 : 120000000;
497 return (ddr2) ? 166000000 : 125000000;
499 WARN_ON_ONCE(parent_rate == 0);
500 return parent_rate / 4;
504 static unsigned long rt2880_cpu_recalc_rate(struct clk_hw *hw,
505 unsigned long xtal_clk)
507 struct mtmips_clk *clk = to_mtmips_clk(hw);
508 struct regmap *sysc = clk->priv->sysc;
511 regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t);
512 t = (t >> RT2880_CONFIG_CPUCLK_SHIFT) & RT2880_CONFIG_CPUCLK_MASK;
515 case RT2880_CONFIG_CPUCLK_250:
517 case RT2880_CONFIG_CPUCLK_266:
519 case RT2880_CONFIG_CPUCLK_280:
521 case RT2880_CONFIG_CPUCLK_300:
528 static u32 mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div)
539 static unsigned long mt7620_pll_recalc_rate(struct clk_hw *hw,
540 unsigned long parent_rate)
542 static const u32 clk_divider[] = { 2, 3, 4, 8 };
543 struct mtmips_clk *clk = to_mtmips_clk(hw);
544 struct regmap *sysc = clk->priv->sysc;
545 unsigned long cpu_pll;
550 regmap_read(sysc, SYSC_REG_CPLL_CONFIG0, &t);
551 if (t & CPLL_CFG0_BYPASS_REF_CLK) {
552 cpu_pll = parent_rate;
553 } else if ((t & CPLL_CFG0_SW_CFG) == 0) {
556 mul = (t >> CPLL_CFG0_PLL_MULT_RATIO_SHIFT) &
557 CPLL_CFG0_PLL_MULT_RATIO_MASK;
559 if (t & CPLL_CFG0_LC_CURFCK)
562 div = (t >> CPLL_CFG0_PLL_DIV_RATIO_SHIFT) &
563 CPLL_CFG0_PLL_DIV_RATIO_MASK;
565 WARN_ON_ONCE(div >= ARRAY_SIZE(clk_divider));
567 cpu_pll = mt7620_calc_rate(parent_rate, mul, clk_divider[div]);
570 regmap_read(sysc, SYSC_REG_CPLL_CONFIG1, &t);
571 if (t & CPLL_CFG1_CPU_AUX1)
574 if (t & CPLL_CFG1_CPU_AUX0)
580 static unsigned long mt7620_cpu_recalc_rate(struct clk_hw *hw,
581 unsigned long parent_rate)
583 struct mtmips_clk *clk = to_mtmips_clk(hw);
584 struct regmap *sysc = clk->priv->sysc;
589 regmap_read(sysc, SYSC_REG_CPU_SYS_CLKCFG, &t);
590 mul = t & CPU_SYS_CLKCFG_CPU_FFRAC_MASK;
591 div = (t >> CPU_SYS_CLKCFG_CPU_FDIV_SHIFT) &
592 CPU_SYS_CLKCFG_CPU_FDIV_MASK;
594 return mt7620_calc_rate(parent_rate, mul, div);
597 static unsigned long mt7620_bus_recalc_rate(struct clk_hw *hw,
598 unsigned long parent_rate)
600 static const u32 ocp_dividers[16] = {
601 [CPU_SYS_CLKCFG_OCP_RATIO_2] = 2,
602 [CPU_SYS_CLKCFG_OCP_RATIO_3] = 3,
603 [CPU_SYS_CLKCFG_OCP_RATIO_4] = 4,
604 [CPU_SYS_CLKCFG_OCP_RATIO_5] = 5,
605 [CPU_SYS_CLKCFG_OCP_RATIO_10] = 10,
607 struct mtmips_clk *clk = to_mtmips_clk(hw);
608 struct regmap *sysc = clk->priv->sysc;
613 regmap_read(sysc, SYSC_REG_CPU_SYS_CLKCFG, &t);
614 ocp_ratio = (t >> CPU_SYS_CLKCFG_OCP_RATIO_SHIFT) &
615 CPU_SYS_CLKCFG_OCP_RATIO_MASK;
617 if (WARN_ON_ONCE(ocp_ratio >= ARRAY_SIZE(ocp_dividers)))
620 div = ocp_dividers[ocp_ratio];
622 if (WARN(!div, "invalid divider for OCP ratio %u", ocp_ratio))
625 return parent_rate / div;
628 static unsigned long mt7620_periph_recalc_rate(struct clk_hw *hw,
629 unsigned long parent_rate)
631 struct mtmips_clk *clk = to_mtmips_clk(hw);
632 struct regmap *sysc = clk->priv->sysc;
635 regmap_read(sysc, SYSC_REG_CLKCFG0, &t);
636 if (t & CLKCFG0_PERI_CLK_SEL)
642 static unsigned long mt76x8_xtal_recalc_rate(struct clk_hw *hw,
643 unsigned long parent_rate)
645 struct mtmips_clk *clk = to_mtmips_clk(hw);
646 struct regmap *sysc = clk->priv->sysc;
649 regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t);
650 if (t & MT7620_XTAL_FREQ_SEL)
656 static unsigned long mt76x8_cpu_recalc_rate(struct clk_hw *hw,
657 unsigned long xtal_clk)
659 if (xtal_clk == 40000000)
665 #define CLK_BASE(_name, _parent, _recalc) { \
666 .init = &(const struct clk_init_data) { \
668 .ops = &(const struct clk_ops) { \
669 .recalc_rate = _recalc, \
671 .parent_data = &(const struct clk_parent_data) { \
675 .num_parents = _parent ? 1 : 0 \
679 static struct mtmips_clk rt2880_clks_base[] = {
680 { CLK_BASE("cpu", "xtal", rt2880_cpu_recalc_rate) }
683 static struct mtmips_clk rt305x_clks_base[] = {
684 { CLK_BASE("cpu", "xtal", rt305x_cpu_recalc_rate) }
687 static struct mtmips_clk rt3352_clks_base[] = {
688 { CLK_BASE("xtal", NULL, rt5350_xtal_recalc_rate) },
689 { CLK_BASE("cpu", "xtal", rt3352_cpu_recalc_rate) }
692 static struct mtmips_clk rt3883_clks_base[] = {
693 { CLK_BASE("cpu", "xtal", rt3883_cpu_recalc_rate) },
694 { CLK_BASE("bus", "cpu", rt3883_bus_recalc_rate) }
697 static struct mtmips_clk rt5350_clks_base[] = {
698 { CLK_BASE("xtal", NULL, rt5350_xtal_recalc_rate) },
699 { CLK_BASE("cpu", "xtal", rt5350_cpu_recalc_rate) },
700 { CLK_BASE("bus", "cpu", rt5350_bus_recalc_rate) }
703 static struct mtmips_clk mt7620_clks_base[] = {
704 { CLK_BASE("xtal", NULL, mt76x8_xtal_recalc_rate) },
705 { CLK_BASE("pll", "xtal", mt7620_pll_recalc_rate) },
706 { CLK_BASE("cpu", "pll", mt7620_cpu_recalc_rate) },
707 { CLK_BASE("periph", "xtal", mt7620_periph_recalc_rate) },
708 { CLK_BASE("bus", "cpu", mt7620_bus_recalc_rate) }
711 static struct mtmips_clk mt76x8_clks_base[] = {
712 { CLK_BASE("xtal", NULL, mt76x8_xtal_recalc_rate) },
713 { CLK_BASE("cpu", "xtal", mt76x8_cpu_recalc_rate) }
716 static int mtmips_register_clocks(struct device_node *np,
717 struct clk_hw_onecell_data *clk_data,
718 struct mtmips_clk_priv *priv)
720 struct clk_hw **hws = clk_data->hws;
721 struct mtmips_clk *sclk;
724 for (i = 0; i < priv->data->num_clk_base; i++) {
725 sclk = &priv->data->clk_base[i];
727 ret = of_clk_hw_register(np, &sclk->hw);
729 pr_err("Couldn't register top clock %i\n", i);
740 sclk = &priv->data->clk_base[i];
741 clk_hw_unregister(&sclk->hw);
746 static const struct mtmips_clk_data rt2880_clk_data = {
747 .clk_base = rt2880_clks_base,
748 .num_clk_base = ARRAY_SIZE(rt2880_clks_base),
749 .clk_fixed = rt305x_fixed_clocks,
750 .num_clk_fixed = ARRAY_SIZE(rt305x_fixed_clocks),
751 .clk_factor = rt2880_factor_clocks,
752 .num_clk_factor = ARRAY_SIZE(rt2880_factor_clocks),
753 .clk_periph = rt2880_pherip_clks,
754 .num_clk_periph = ARRAY_SIZE(rt2880_pherip_clks),
757 static const struct mtmips_clk_data rt305x_clk_data = {
758 .clk_base = rt305x_clks_base,
759 .num_clk_base = ARRAY_SIZE(rt305x_clks_base),
760 .clk_fixed = rt305x_fixed_clocks,
761 .num_clk_fixed = ARRAY_SIZE(rt305x_fixed_clocks),
762 .clk_factor = rt305x_factor_clocks,
763 .num_clk_factor = ARRAY_SIZE(rt305x_factor_clocks),
764 .clk_periph = rt305x_pherip_clks,
765 .num_clk_periph = ARRAY_SIZE(rt305x_pherip_clks),
768 static const struct mtmips_clk_data rt3352_clk_data = {
769 .clk_base = rt3352_clks_base,
770 .num_clk_base = ARRAY_SIZE(rt3352_clks_base),
771 .clk_fixed = rt3352_fixed_clocks,
772 .num_clk_fixed = ARRAY_SIZE(rt3352_fixed_clocks),
773 .clk_factor = rt305x_factor_clocks,
774 .num_clk_factor = ARRAY_SIZE(rt305x_factor_clocks),
775 .clk_periph = rt5350_pherip_clks,
776 .num_clk_periph = ARRAY_SIZE(rt5350_pherip_clks),
779 static const struct mtmips_clk_data rt3883_clk_data = {
780 .clk_base = rt3883_clks_base,
781 .num_clk_base = ARRAY_SIZE(rt3883_clks_base),
782 .clk_fixed = rt305x_fixed_clocks,
783 .num_clk_fixed = ARRAY_SIZE(rt305x_fixed_clocks),
786 .clk_periph = rt5350_pherip_clks,
787 .num_clk_periph = ARRAY_SIZE(rt5350_pherip_clks),
790 static const struct mtmips_clk_data rt5350_clk_data = {
791 .clk_base = rt5350_clks_base,
792 .num_clk_base = ARRAY_SIZE(rt5350_clks_base),
793 .clk_fixed = rt3352_fixed_clocks,
794 .num_clk_fixed = ARRAY_SIZE(rt3352_fixed_clocks),
797 .clk_periph = rt5350_pherip_clks,
798 .num_clk_periph = ARRAY_SIZE(rt5350_pherip_clks),
801 static const struct mtmips_clk_data mt7620_clk_data = {
802 .clk_base = mt7620_clks_base,
803 .num_clk_base = ARRAY_SIZE(mt7620_clks_base),
808 .clk_periph = mt7620_pherip_clks,
809 .num_clk_periph = ARRAY_SIZE(mt7620_pherip_clks),
812 static const struct mtmips_clk_data mt76x8_clk_data = {
813 .clk_base = mt76x8_clks_base,
814 .num_clk_base = ARRAY_SIZE(mt76x8_clks_base),
815 .clk_fixed = mt76x8_fixed_clocks,
816 .num_clk_fixed = ARRAY_SIZE(mt76x8_fixed_clocks),
817 .clk_factor = rt305x_factor_clocks,
818 .num_clk_factor = ARRAY_SIZE(rt305x_factor_clocks),
819 .clk_periph = mt76x8_pherip_clks,
820 .num_clk_periph = ARRAY_SIZE(mt76x8_pherip_clks),
823 static const struct of_device_id mtmips_of_match[] = {
825 .compatible = "ralink,rt2880-reset",
829 .compatible = "ralink,rt2880-sysc",
830 .data = &rt2880_clk_data,
833 .compatible = "ralink,rt3050-sysc",
834 .data = &rt305x_clk_data,
837 .compatible = "ralink,rt3052-sysc",
838 .data = &rt305x_clk_data,
841 .compatible = "ralink,rt3352-sysc",
842 .data = &rt3352_clk_data,
845 .compatible = "ralink,rt3883-sysc",
846 .data = &rt3883_clk_data,
849 .compatible = "ralink,rt5350-sysc",
850 .data = &rt5350_clk_data,
853 .compatible = "ralink,mt7620-sysc",
854 .data = &mt7620_clk_data,
857 .compatible = "ralink,mt7628-sysc",
858 .data = &mt76x8_clk_data,
861 .compatible = "ralink,mt7688-sysc",
862 .data = &mt76x8_clk_data,
867 static void __init mtmips_clk_regs_init(struct device_node *node,
868 struct mtmips_clk_priv *priv)
872 if (!of_device_is_compatible(node, "ralink,mt7620-sysc"))
876 * When the CPU goes into sleep mode, the BUS
877 * clock will be too low for USB to function properly.
878 * Adjust the busses fractional divider to fix this
880 regmap_read(priv->sysc, SYSC_REG_CPU_SYS_CLKCFG, &t);
881 t &= ~(CLKCFG_FDIV_MASK | CLKCFG_FFRAC_MASK);
882 t |= CLKCFG_FDIV_USB_VAL | CLKCFG_FFRAC_USB_VAL;
883 regmap_write(priv->sysc, SYSC_REG_CPU_SYS_CLKCFG, t);
886 static void __init mtmips_clk_init(struct device_node *node)
888 const struct of_device_id *match;
889 const struct mtmips_clk_data *data;
890 struct mtmips_clk_priv *priv;
891 struct clk_hw_onecell_data *clk_data;
894 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
898 priv->sysc = syscon_node_to_regmap(node);
899 if (IS_ERR(priv->sysc)) {
900 pr_err("Could not get sysc syscon regmap\n");
904 mtmips_clk_regs_init(node, priv);
906 match = of_match_node(mtmips_of_match, node);
912 count = priv->data->num_clk_base + priv->data->num_clk_fixed +
913 priv->data->num_clk_factor + priv->data->num_clk_periph;
914 clk_data = kzalloc(struct_size(clk_data, hws, count), GFP_KERNEL);
918 ret = mtmips_register_clocks(node, clk_data, priv);
920 pr_err("Couldn't register top clocks\n");
924 ret = mtmips_register_fixed_clocks(clk_data, priv);
926 pr_err("Couldn't register fixed clocks\n");
930 ret = mtmips_register_factor_clocks(clk_data, priv);
932 pr_err("Couldn't register factor clocks\n");
933 goto unreg_clk_fixed;
936 ret = mtmips_register_pherip_clocks(node, clk_data, priv);
938 pr_err("Couldn't register peripheral clocks\n");
939 goto unreg_clk_factor;
942 clk_data->num = count;
944 ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
946 pr_err("Couldn't add clk hw provider\n");
947 goto unreg_clk_periph;
953 for (i = 0; i < priv->data->num_clk_periph; i++) {
954 struct mtmips_clk *sclk = &priv->data->clk_periph[i];
956 clk_hw_unregister(&sclk->hw);
960 for (i = 0; i < priv->data->num_clk_factor; i++) {
961 struct mtmips_clk_factor *sclk = &priv->data->clk_factor[i];
963 clk_hw_unregister_fixed_factor(sclk->hw);
967 for (i = 0; i < priv->data->num_clk_fixed; i++) {
968 struct mtmips_clk_fixed *sclk = &priv->data->clk_fixed[i];
970 clk_hw_unregister_fixed_rate(sclk->hw);
974 for (i = 0; i < priv->data->num_clk_base; i++) {
975 struct mtmips_clk *sclk = &priv->data->clk_base[i];
977 clk_hw_unregister(&sclk->hw);
986 CLK_OF_DECLARE_DRIVER(rt2880_clk, "ralink,rt2880-sysc", mtmips_clk_init);
987 CLK_OF_DECLARE_DRIVER(rt3050_clk, "ralink,rt3050-sysc", mtmips_clk_init);
988 CLK_OF_DECLARE_DRIVER(rt3052_clk, "ralink,rt3052-sysc", mtmips_clk_init);
989 CLK_OF_DECLARE_DRIVER(rt3352_clk, "ralink,rt3352-sysc", mtmips_clk_init);
990 CLK_OF_DECLARE_DRIVER(rt3883_clk, "ralink,rt3883-sysc", mtmips_clk_init);
991 CLK_OF_DECLARE_DRIVER(rt5350_clk, "ralink,rt5350-sysc", mtmips_clk_init);
992 CLK_OF_DECLARE_DRIVER(mt7620_clk, "ralink,mt7620-sysc", mtmips_clk_init);
993 CLK_OF_DECLARE_DRIVER(mt7628_clk, "ralink,mt7628-sysc", mtmips_clk_init);
994 CLK_OF_DECLARE_DRIVER(mt7688_clk, "ralink,mt7688-sysc", mtmips_clk_init);
997 struct reset_controller_dev rcdev;
1001 static struct mtmips_rst *to_mtmips_rst(struct reset_controller_dev *dev)
1003 return container_of(dev, struct mtmips_rst, rcdev);
1006 static int mtmips_assert_device(struct reset_controller_dev *rcdev,
1009 struct mtmips_rst *data = to_mtmips_rst(rcdev);
1010 struct regmap *sysc = data->sysc;
1012 return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), BIT(id));
1015 static int mtmips_deassert_device(struct reset_controller_dev *rcdev,
1018 struct mtmips_rst *data = to_mtmips_rst(rcdev);
1019 struct regmap *sysc = data->sysc;
1021 return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), 0);
1024 static int mtmips_reset_device(struct reset_controller_dev *rcdev,
1029 ret = mtmips_assert_device(rcdev, id);
1033 return mtmips_deassert_device(rcdev, id);
1036 static int mtmips_rst_xlate(struct reset_controller_dev *rcdev,
1037 const struct of_phandle_args *reset_spec)
1039 unsigned long id = reset_spec->args[0];
1041 if (id == 0 || id >= rcdev->nr_resets)
1047 static const struct reset_control_ops reset_ops = {
1048 .reset = mtmips_reset_device,
1049 .assert = mtmips_assert_device,
1050 .deassert = mtmips_deassert_device
1053 static int mtmips_reset_init(struct device *dev, struct regmap *sysc)
1055 struct mtmips_rst *rst_data;
1057 rst_data = devm_kzalloc(dev, sizeof(*rst_data), GFP_KERNEL);
1061 rst_data->sysc = sysc;
1062 rst_data->rcdev.ops = &reset_ops;
1063 rst_data->rcdev.owner = THIS_MODULE;
1064 rst_data->rcdev.nr_resets = 32;
1065 rst_data->rcdev.of_reset_n_cells = 1;
1066 rst_data->rcdev.of_xlate = mtmips_rst_xlate;
1067 rst_data->rcdev.of_node = dev_of_node(dev);
1069 return devm_reset_controller_register(dev, &rst_data->rcdev);
1072 static int mtmips_clk_probe(struct platform_device *pdev)
1074 struct device_node *np = pdev->dev.of_node;
1075 struct device *dev = &pdev->dev;
1076 struct mtmips_clk_priv *priv;
1079 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1083 priv->sysc = syscon_node_to_regmap(np);
1084 if (IS_ERR(priv->sysc))
1085 return dev_err_probe(dev, PTR_ERR(priv->sysc),
1086 "Could not get sysc syscon regmap\n");
1088 ret = mtmips_reset_init(dev, priv->sysc);
1090 return dev_err_probe(dev, ret, "Could not init reset controller\n");
1095 static struct platform_driver mtmips_clk_driver = {
1096 .probe = mtmips_clk_probe,
1098 .name = "mtmips-clk",
1099 .of_match_table = mtmips_of_match,
1103 static int __init mtmips_clk_reset_init(void)
1105 return platform_driver_register(&mtmips_clk_driver);
1107 arch_initcall(mtmips_clk_reset_init);