drivers/clk/qcom/videocc-sm8250.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/clk-provider.h>
   7 #include <linux/module.h>
   8 #include <linux/platform_device.h>
   9 #include <linux/regmap.h>
  10
  11 #include <dt-bindings/clock/qcom,videocc-sm8250.h>
  12
  13 #include "clk-alpha-pll.h"
  14 #include "clk-branch.h"
  15 #include "clk-rcg.h"
  16 #include "clk-regmap.h"
  17 #include "clk-regmap-divider.h"
  18 #include "common.h"
  19 #include "reset.h"
  20 #include "gdsc.h"
  21
  22 enum {
  23         P_BI_TCXO,
  24         P_VIDEO_PLL0_OUT_MAIN,
  25         P_VIDEO_PLL1_OUT_MAIN,
  26 };
  27
  28 static struct pll_vco lucid_vco[] = {
  29         { 249600000, 2000000000, 0 },
  30 };
  31
  32 static const struct alpha_pll_config video_pll0_config = {
  33         .l = 0x25,
  34         .alpha = 0x8000,
  35         .config_ctl_val = 0x20485699,
  36         .config_ctl_hi_val = 0x00002261,
  37         .config_ctl_hi1_val = 0x329A699C,
  38         .user_ctl_val = 0x00000000,
  39         .user_ctl_hi_val = 0x00000805,
  40         .user_ctl_hi1_val = 0x00000000,
  41 };
  42
  43 static struct clk_alpha_pll video_pll0 = {
  44         .offset = 0x42c,
  45         .vco_table = lucid_vco,
  46         .num_vco = ARRAY_SIZE(lucid_vco),
  47         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
  48         .clkr = {
  49                 .hw.init = &(struct clk_init_data){
  50                         .name = "video_pll0",
  51                         .parent_data = &(const struct clk_parent_data){
  52                                 .fw_name = "bi_tcxo",
  53                         },
  54                         .num_parents = 1,
  55                         .ops = &clk_alpha_pll_lucid_ops,
  56                 },
  57         },
  58 };
  59
  60 static const struct alpha_pll_config video_pll1_config = {
  61         .l = 0x2B,
  62         .alpha = 0xC000,
  63         .config_ctl_val = 0x20485699,
  64         .config_ctl_hi_val = 0x00002261,
  65         .config_ctl_hi1_val = 0x329A699C,
  66         .user_ctl_val = 0x00000000,
  67         .user_ctl_hi_val = 0x00000805,
  68         .user_ctl_hi1_val = 0x00000000,
  69 };
  70
  71 static struct clk_alpha_pll video_pll1 = {
  72         .offset = 0x7d0,
  73         .vco_table = lucid_vco,
  74         .num_vco = ARRAY_SIZE(lucid_vco),
  75         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
  76         .clkr = {
  77                 .hw.init = &(struct clk_init_data){
  78                         .name = "video_pll1",
  79                         .parent_data = &(const struct clk_parent_data){
  80                                 .fw_name = "bi_tcxo",
  81                         },
  82                         .num_parents = 1,
  83                         .ops = &clk_alpha_pll_lucid_ops,
  84                 },
  85         },
  86 };
  87
  88 static const struct parent_map video_cc_parent_map_1[] = {
  89         { P_BI_TCXO, 0 },
  90         { P_VIDEO_PLL0_OUT_MAIN, 1 },
  91 };
  92
  93 static const struct clk_parent_data video_cc_parent_data_1[] = {
  94         { .fw_name = "bi_tcxo" },
  95         { .hw = &video_pll0.clkr.hw },
  96 };
  97
  98 static const struct parent_map video_cc_parent_map_2[] = {
  99         { P_BI_TCXO, 0 },
 100         { P_VIDEO_PLL1_OUT_MAIN, 1 },
 101 };
 102
 103 static const struct clk_parent_data video_cc_parent_data_2[] = {
 104         { .fw_name = "bi_tcxo" },
 105         { .hw = &video_pll1.clkr.hw },
 106 };
 107
 108 static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = {
 109         F(19200000, P_BI_TCXO, 1, 0, 0),
 110         F(720000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
 111         F(1014000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
 112         F(1098000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
 113         F(1332000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
 114         { }
 115 };
 116
 117 static struct clk_rcg2 video_cc_mvs0_clk_src = {
 118         .cmd_rcgr = 0xb94,
 119         .mnd_width = 0,
 120         .hid_width = 5,
 121         .parent_map = video_cc_parent_map_1,
 122         .freq_tbl = ftbl_video_cc_mvs0_clk_src,
 123         .clkr.hw.init = &(struct clk_init_data){
 124                 .name = "video_cc_mvs0_clk_src",
 125                 .parent_data = video_cc_parent_data_1,
 126                 .num_parents = ARRAY_SIZE(video_cc_parent_data_1),
 127                 .flags = CLK_SET_RATE_PARENT,
 128                 .ops = &clk_rcg2_shared_ops,
 129         },
 130 };
 131
 132 static const struct freq_tbl ftbl_video_cc_mvs1_clk_src[] = {
 133         F(19200000, P_BI_TCXO, 1, 0, 0),
 134         F(840000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0),
 135         F(1098000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0),
 136         F(1332000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0),
 137         { }
 138 };
 139
 140 static struct clk_rcg2 video_cc_mvs1_clk_src = {
 141         .cmd_rcgr = 0xbb4,
 142         .mnd_width = 0,
 143         .hid_width = 5,
 144         .parent_map = video_cc_parent_map_2,
 145         .freq_tbl = ftbl_video_cc_mvs1_clk_src,
 146         .clkr.hw.init = &(struct clk_init_data){
 147                 .name = "video_cc_mvs1_clk_src",
 148                 .parent_data = video_cc_parent_data_2,
 149                 .num_parents = ARRAY_SIZE(video_cc_parent_data_2),
 150                 .flags = CLK_SET_RATE_PARENT,
 151                 .ops = &clk_rcg2_shared_ops,
 152         },
 153 };
 154
 155 static struct clk_regmap_div video_cc_mvs0c_div2_div_clk_src = {
 156         .reg = 0xc54,
 157         .shift = 0,
 158         .width = 2,
 159         .clkr.hw.init = &(struct clk_init_data) {
 160                 .name = "video_cc_mvs0c_div2_div_clk_src",
 161                 .parent_hws = (const struct clk_hw*[]){
 162                         &video_cc_mvs0_clk_src.clkr.hw,
 163                 },
 164                 .num_parents = 1,
 165                 .flags = CLK_SET_RATE_PARENT,
 166                 .ops = &clk_regmap_div_ro_ops,
 167         },
 168 };
 169
 170 static struct clk_regmap_div video_cc_mvs0_div_clk_src = {
 171         .reg = 0xd54,
 172         .shift = 0,
 173         .width = 2,
 174         .clkr.hw.init = &(struct clk_init_data) {
 175                 .name = "video_cc_mvs0_div_clk_src",
 176                 .parent_hws = (const struct clk_hw*[]){
 177                         &video_cc_mvs0_clk_src.clkr.hw,
 178                 },
 179                 .num_parents = 1,
 180                 .flags = CLK_SET_RATE_PARENT,
 181                 .ops = &clk_regmap_div_ro_ops,
 182         },
 183 };
 184
 185 static struct clk_regmap_div video_cc_mvs1c_div2_div_clk_src = {
 186         .reg = 0xcf4,
 187         .shift = 0,
 188         .width = 2,
 189         .clkr.hw.init = &(struct clk_init_data) {
 190                 .name = "video_cc_mvs1c_div2_div_clk_src",
 191                 .parent_hws = (const struct clk_hw*[]){
 192                         &video_cc_mvs1_clk_src.clkr.hw,
 193                 },
 194                 .num_parents = 1,
 195                 .flags = CLK_SET_RATE_PARENT,
 196                 .ops = &clk_regmap_div_ro_ops,
 197         },
 198 };
 199
 200 static struct clk_branch video_cc_mvs0c_clk = {
 201         .halt_reg = 0xc34,
 202         .halt_check = BRANCH_HALT,
 203         .clkr = {
 204                 .enable_reg = 0xc34,
 205                 .enable_mask = BIT(0),
 206                 .hw.init = &(struct clk_init_data){
 207                         .name = "video_cc_mvs0c_clk",
 208                         .parent_hws = (const struct clk_hw*[]){
 209                                 &video_cc_mvs0c_div2_div_clk_src.clkr.hw,
 210                         },
 211                         .num_parents = 1,
 212                         .flags = CLK_SET_RATE_PARENT,
 213                         .ops = &clk_branch2_ops,
 214                 },
 215         },
 216 };
 217
 218 static struct clk_branch video_cc_mvs0_clk = {
 219         .halt_reg = 0xd34,
 220         .halt_check = BRANCH_HALT_VOTED,
 221         .clkr = {
 222                 .enable_reg = 0xd34,
 223                 .enable_mask = BIT(0),
 224                 .hw.init = &(struct clk_init_data){
 225                         .name = "video_cc_mvs0_clk",
 226                         .parent_hws = (const struct clk_hw*[]){
 227                                 &video_cc_mvs0_div_clk_src.clkr.hw,
 228                         },
 229                         .num_parents = 1,
 230                         .flags = CLK_SET_RATE_PARENT,
 231                         .ops = &clk_branch2_ops,
 232                 },
 233         },
 234 };
 235
 236 static struct clk_branch video_cc_mvs1_div2_clk = {
 237         .halt_reg = 0xdf4,
 238         .halt_check = BRANCH_HALT_VOTED,
 239         .clkr = {
 240                 .enable_reg = 0xdf4,
 241                 .enable_mask = BIT(0),
 242                 .hw.init = &(struct clk_init_data){
 243                         .name = "video_cc_mvs1_div2_clk",
 244                         .parent_hws = (const struct clk_hw*[]){
 245                                 &video_cc_mvs1c_div2_div_clk_src.clkr.hw,
 246                         },
 247                         .num_parents = 1,
 248                         .flags = CLK_SET_RATE_PARENT,
 249                         .ops = &clk_branch2_ops,
 250                 },
 251         },
 252 };
 253
 254 static struct clk_branch video_cc_mvs1c_clk = {
 255         .halt_reg = 0xcd4,
 256         .halt_check = BRANCH_HALT_VOTED,
 257         .clkr = {
 258                 .enable_reg = 0xcd4,
 259                 .enable_mask = BIT(0),
 260                 .hw.init = &(struct clk_init_data){
 261                         .name = "video_cc_mvs1c_clk",
 262                         .parent_hws = (const struct clk_hw*[]){
 263                                 &video_cc_mvs1c_div2_div_clk_src.clkr.hw,
 264                         },
 265                         .num_parents = 1,
 266                         .flags = CLK_SET_RATE_PARENT,
 267                         .ops = &clk_branch2_ops,
 268                 },
 269         },
 270 };
 271
 272 static struct gdsc mvs0c_gdsc = {
 273         .gdscr = 0xbf8,
 274         .pd = {
 275                 .name = "mvs0c_gdsc",
 276         },
 277         .flags = 0,
 278         .pwrsts = PWRSTS_OFF_ON,
 279         .supply = "mmcx",
 280 };
 281
 282 static struct gdsc mvs1c_gdsc = {
 283         .gdscr = 0xc98,
 284         .pd = {
 285                 .name = "mvs1c_gdsc",
 286         },
 287         .flags = 0,
 288         .pwrsts = PWRSTS_OFF_ON,
 289         .supply = "mmcx",
 290 };
 291
 292 static struct gdsc mvs0_gdsc = {
 293         .gdscr = 0xd18,
 294         .pd = {
 295                 .name = "mvs0_gdsc",
 296         },
 297         .flags = HW_CTRL,
 298         .pwrsts = PWRSTS_OFF_ON,
 299         .supply = "mmcx",
 300 };
 301
 302 static struct gdsc mvs1_gdsc = {
 303         .gdscr = 0xd98,
 304         .pd = {
 305                 .name = "mvs1_gdsc",
 306         },
 307         .flags = HW_CTRL,
 308         .pwrsts = PWRSTS_OFF_ON,
 309         .supply = "mmcx",
 310 };
 311
 312 static struct clk_regmap *video_cc_sm8250_clocks[] = {
 313         [VIDEO_CC_MVS0_CLK] = &video_cc_mvs0_clk.clkr,
 314         [VIDEO_CC_MVS0_CLK_SRC] = &video_cc_mvs0_clk_src.clkr,
 315         [VIDEO_CC_MVS0_DIV_CLK_SRC] = &video_cc_mvs0_div_clk_src.clkr,
 316         [VIDEO_CC_MVS0C_CLK] = &video_cc_mvs0c_clk.clkr,
 317         [VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC] = &video_cc_mvs0c_div2_div_clk_src.clkr,
 318         [VIDEO_CC_MVS1_CLK_SRC] = &video_cc_mvs1_clk_src.clkr,
 319         [VIDEO_CC_MVS1_DIV2_CLK] = &video_cc_mvs1_div2_clk.clkr,
 320         [VIDEO_CC_MVS1C_CLK] = &video_cc_mvs1c_clk.clkr,
 321         [VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC] = &video_cc_mvs1c_div2_div_clk_src.clkr,
 322         [VIDEO_CC_PLL0] = &video_pll0.clkr,
 323         [VIDEO_CC_PLL1] = &video_pll1.clkr,
 324 };
 325
 326 static const struct qcom_reset_map video_cc_sm8250_resets[] = {
 327         [VIDEO_CC_CVP_INTERFACE_BCR] = { 0xe54 },
 328         [VIDEO_CC_CVP_MVS0_BCR] = { 0xd14 },
 329         [VIDEO_CC_MVS0C_CLK_ARES] = { 0xc34, 2 },
 330         [VIDEO_CC_CVP_MVS0C_BCR] = { 0xbf4 },
 331         [VIDEO_CC_CVP_MVS1_BCR] = { 0xd94 },
 332         [VIDEO_CC_MVS1C_CLK_ARES] = { 0xcd4, 2 },
 333         [VIDEO_CC_CVP_MVS1C_BCR] = { 0xc94 },
 334 };
 335
 336 static struct gdsc *video_cc_sm8250_gdscs[] = {
 337         [MVS0C_GDSC] = &mvs0c_gdsc,
 338         [MVS1C_GDSC] = &mvs1c_gdsc,
 339         [MVS0_GDSC] = &mvs0_gdsc,
 340         [MVS1_GDSC] = &mvs1_gdsc,
 341 };
 342
 343 static const struct regmap_config video_cc_sm8250_regmap_config = {
 344         .reg_bits = 32,
 345         .reg_stride = 4,
 346         .val_bits = 32,
 347         .max_register = 0xf4c,
 348         .fast_io = true,
 349 };
 350
 351 static const struct qcom_cc_desc video_cc_sm8250_desc = {
 352         .config = &video_cc_sm8250_regmap_config,
 353         .clks = video_cc_sm8250_clocks,
 354         .num_clks = ARRAY_SIZE(video_cc_sm8250_clocks),
 355         .resets = video_cc_sm8250_resets,
 356         .num_resets = ARRAY_SIZE(video_cc_sm8250_resets),
 357         .gdscs = video_cc_sm8250_gdscs,
 358         .num_gdscs = ARRAY_SIZE(video_cc_sm8250_gdscs),
 359 };
 360
 361 static const struct of_device_id video_cc_sm8250_match_table[] = {
 362         { .compatible = "qcom,sm8250-videocc" },
 363         { }
 364 };
 365 MODULE_DEVICE_TABLE(of, video_cc_sm8250_match_table);
 366
 367 static int video_cc_sm8250_probe(struct platform_device *pdev)
 368 {
 369         struct regmap *regmap;
 370
 371         regmap = qcom_cc_map(pdev, &video_cc_sm8250_desc);
 372         if (IS_ERR(regmap))
 373                 return PTR_ERR(regmap);
 374
 375         clk_lucid_pll_configure(&video_pll0, regmap, &video_pll0_config);
 376         clk_lucid_pll_configure(&video_pll1, regmap, &video_pll1_config);
 377
 378         /* Keep VIDEO_CC_AHB_CLK and VIDEO_CC_XO_CLK ALWAYS-ON */
 379         regmap_update_bits(regmap, 0xe58, BIT(0), BIT(0));
 380         regmap_update_bits(regmap, 0xeec, BIT(0), BIT(0));
 381
 382         return qcom_cc_really_probe(pdev, &video_cc_sm8250_desc, regmap);
 383 }
 384
 385 static struct platform_driver video_cc_sm8250_driver = {
 386         .probe  = video_cc_sm8250_probe,
 387         .driver = {
 388                 .name = "sm8250-videocc",
 389                 .of_match_table = video_cc_sm8250_match_table,
 390         },
 391 };
 392
 393 static int __init video_cc_sm8250_init(void)
 394 {
 395         return platform_driver_register(&video_cc_sm8250_driver);
 396 }
 397 subsys_initcall(video_cc_sm8250_init);
 398
 399 static void __exit video_cc_sm8250_exit(void)
 400 {
 401         platform_driver_unregister(&video_cc_sm8250_driver);
 402 }
 403 module_exit(video_cc_sm8250_exit);
 404
 405 MODULE_LICENSE("GPL v2");
 406 MODULE_DESCRIPTION("QTI VIDEOCC SM8250 Driver");