1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2021, The Linux Foundation. All rights reserved.
6 #include <linux/clk-provider.h>
7 #include <linux/module.h>
8 #include <linux/platform_device.h>
9 #include <linux/regmap.h>
11 #include <dt-bindings/clock/qcom,videocc-sc7280.h>
13 #include "clk-alpha-pll.h"
14 #include "clk-branch.h"
23 P_VIDEO_PLL0_OUT_EVEN,
26 static const struct pll_vco lucid_vco[] = {
27 { 249600000, 2000000000, 0 },
30 /* 400MHz Configuration */
31 static const struct alpha_pll_config video_pll0_config = {
34 .config_ctl_val = 0x20485699,
35 .config_ctl_hi_val = 0x00002261,
36 .config_ctl_hi1_val = 0x329A299C,
37 .user_ctl_val = 0x00000001,
38 .user_ctl_hi_val = 0x00000805,
39 .user_ctl_hi1_val = 0x00000000,
42 static struct clk_alpha_pll video_pll0 = {
44 .vco_table = lucid_vco,
45 .num_vco = ARRAY_SIZE(lucid_vco),
46 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
48 .hw.init = &(struct clk_init_data){
50 .parent_data = &(const struct clk_parent_data){
54 .ops = &clk_alpha_pll_lucid_ops,
59 static const struct parent_map video_cc_parent_map_0[] = {
61 { P_VIDEO_PLL0_OUT_EVEN, 3 },
64 static const struct clk_parent_data video_cc_parent_data_0[] = {
65 { .fw_name = "bi_tcxo" },
66 { .hw = &video_pll0.clkr.hw },
69 static const struct parent_map video_cc_parent_map_1[] = {
73 static const struct clk_parent_data video_cc_parent_data_1[] = {
74 { .fw_name = "sleep_clk" },
77 static const struct freq_tbl ftbl_video_cc_iris_clk_src[] = {
78 F(133333333, P_VIDEO_PLL0_OUT_EVEN, 3, 0, 0),
79 F(240000000, P_VIDEO_PLL0_OUT_EVEN, 2, 0, 0),
80 F(335000000, P_VIDEO_PLL0_OUT_EVEN, 2, 0, 0),
81 F(424000000, P_VIDEO_PLL0_OUT_EVEN, 2, 0, 0),
82 F(460000000, P_VIDEO_PLL0_OUT_EVEN, 2, 0, 0),
86 static struct clk_rcg2 video_cc_iris_clk_src = {
90 .parent_map = video_cc_parent_map_0,
91 .freq_tbl = ftbl_video_cc_iris_clk_src,
92 .clkr.hw.init = &(struct clk_init_data){
93 .name = "video_cc_iris_clk_src",
94 .parent_data = video_cc_parent_data_0,
95 .num_parents = ARRAY_SIZE(video_cc_parent_data_0),
96 .flags = CLK_SET_RATE_PARENT,
97 .ops = &clk_rcg2_shared_ops,
101 static const struct freq_tbl ftbl_video_cc_sleep_clk_src[] = {
102 F(32000, P_SLEEP_CLK, 1, 0, 0),
106 static struct clk_rcg2 video_cc_sleep_clk_src = {
110 .parent_map = video_cc_parent_map_1,
111 .freq_tbl = ftbl_video_cc_sleep_clk_src,
112 .clkr.hw.init = &(struct clk_init_data){
113 .name = "video_cc_sleep_clk_src",
114 .parent_data = video_cc_parent_data_1,
115 .num_parents = ARRAY_SIZE(video_cc_parent_data_1),
116 .ops = &clk_rcg2_ops,
120 static struct clk_branch video_cc_iris_ahb_clk = {
122 .halt_check = BRANCH_HALT_VOTED,
124 .enable_reg = 0x5004,
125 .enable_mask = BIT(0),
126 .hw.init = &(struct clk_init_data){
127 .name = "video_cc_iris_ahb_clk",
128 .parent_hws = (const struct clk_hw*[]){
129 &video_cc_iris_clk_src.clkr.hw,
132 .flags = CLK_SET_RATE_PARENT,
133 .ops = &clk_branch2_ops,
138 static struct clk_branch video_cc_mvs0_axi_clk = {
140 .halt_check = BRANCH_HALT,
142 .enable_reg = 0x800c,
143 .enable_mask = BIT(0),
144 .hw.init = &(struct clk_init_data){
145 .name = "video_cc_mvs0_axi_clk",
146 .ops = &clk_branch2_ops,
151 static struct clk_branch video_cc_mvs0_core_clk = {
153 .halt_check = BRANCH_HALT_VOTED,
157 .enable_reg = 0x3010,
158 .enable_mask = BIT(0),
159 .hw.init = &(struct clk_init_data){
160 .name = "video_cc_mvs0_core_clk",
161 .parent_hws = (const struct clk_hw*[]){
162 &video_cc_iris_clk_src.clkr.hw,
165 .flags = CLK_SET_RATE_PARENT,
166 .ops = &clk_branch2_ops,
171 static struct clk_branch video_cc_mvsc_core_clk = {
173 .halt_check = BRANCH_HALT,
175 .enable_reg = 0x2014,
176 .enable_mask = BIT(0),
177 .hw.init = &(struct clk_init_data){
178 .name = "video_cc_mvsc_core_clk",
179 .parent_hws = (const struct clk_hw*[]){
180 &video_cc_iris_clk_src.clkr.hw,
183 .flags = CLK_SET_RATE_PARENT,
184 .ops = &clk_branch2_ops,
189 static struct clk_branch video_cc_mvsc_ctl_axi_clk = {
191 .halt_check = BRANCH_HALT,
193 .enable_reg = 0x8004,
194 .enable_mask = BIT(0),
195 .hw.init = &(struct clk_init_data){
196 .name = "video_cc_mvsc_ctl_axi_clk",
197 .ops = &clk_branch2_ops,
202 static struct clk_branch video_cc_sleep_clk = {
204 .halt_check = BRANCH_HALT,
206 .enable_reg = 0x7034,
207 .enable_mask = BIT(0),
208 .hw.init = &(struct clk_init_data){
209 .name = "video_cc_sleep_clk",
210 .parent_hws = (const struct clk_hw*[]){
211 &video_cc_sleep_clk_src.clkr.hw,
214 .flags = CLK_SET_RATE_PARENT,
215 .ops = &clk_branch2_ops,
220 static struct clk_branch video_cc_venus_ahb_clk = {
222 .halt_check = BRANCH_HALT,
224 .enable_reg = 0x801c,
225 .enable_mask = BIT(0),
226 .hw.init = &(struct clk_init_data){
227 .name = "video_cc_venus_ahb_clk",
228 .ops = &clk_branch2_ops,
233 static struct gdsc mvs0_gdsc = {
238 .pwrsts = PWRSTS_OFF_ON,
239 .flags = HW_CTRL | RETAIN_FF_ENABLE,
242 static struct gdsc mvsc_gdsc = {
247 .flags = RETAIN_FF_ENABLE,
248 .pwrsts = PWRSTS_OFF_ON,
251 static struct clk_regmap *video_cc_sc7280_clocks[] = {
252 [VIDEO_CC_IRIS_AHB_CLK] = &video_cc_iris_ahb_clk.clkr,
253 [VIDEO_CC_IRIS_CLK_SRC] = &video_cc_iris_clk_src.clkr,
254 [VIDEO_CC_MVS0_AXI_CLK] = &video_cc_mvs0_axi_clk.clkr,
255 [VIDEO_CC_MVS0_CORE_CLK] = &video_cc_mvs0_core_clk.clkr,
256 [VIDEO_CC_MVSC_CORE_CLK] = &video_cc_mvsc_core_clk.clkr,
257 [VIDEO_CC_MVSC_CTL_AXI_CLK] = &video_cc_mvsc_ctl_axi_clk.clkr,
258 [VIDEO_CC_SLEEP_CLK] = &video_cc_sleep_clk.clkr,
259 [VIDEO_CC_SLEEP_CLK_SRC] = &video_cc_sleep_clk_src.clkr,
260 [VIDEO_CC_VENUS_AHB_CLK] = &video_cc_venus_ahb_clk.clkr,
261 [VIDEO_PLL0] = &video_pll0.clkr,
264 static struct gdsc *video_cc_sc7280_gdscs[] = {
265 [MVS0_GDSC] = &mvs0_gdsc,
266 [MVSC_GDSC] = &mvsc_gdsc,
269 static const struct regmap_config video_cc_sc7280_regmap_config = {
273 .max_register = 0xb000,
277 static const struct qcom_cc_desc video_cc_sc7280_desc = {
278 .config = &video_cc_sc7280_regmap_config,
279 .clks = video_cc_sc7280_clocks,
280 .num_clks = ARRAY_SIZE(video_cc_sc7280_clocks),
281 .gdscs = video_cc_sc7280_gdscs,
282 .num_gdscs = ARRAY_SIZE(video_cc_sc7280_gdscs),
285 static const struct of_device_id video_cc_sc7280_match_table[] = {
286 { .compatible = "qcom,sc7280-videocc" },
289 MODULE_DEVICE_TABLE(of, video_cc_sc7280_match_table);
291 static int video_cc_sc7280_probe(struct platform_device *pdev)
293 struct regmap *regmap;
295 regmap = qcom_cc_map(pdev, &video_cc_sc7280_desc);
297 return PTR_ERR(regmap);
299 clk_lucid_pll_configure(&video_pll0, regmap, &video_pll0_config);
301 return qcom_cc_really_probe(pdev, &video_cc_sc7280_desc, regmap);
304 static struct platform_driver video_cc_sc7280_driver = {
305 .probe = video_cc_sc7280_probe,
307 .name = "video_cc-sc7280",
308 .of_match_table = video_cc_sc7280_match_table,
312 static int __init video_cc_sc7280_init(void)
314 return platform_driver_register(&video_cc_sc7280_driver);
316 subsys_initcall(video_cc_sc7280_init);
318 static void __exit video_cc_sc7280_exit(void)
320 platform_driver_unregister(&video_cc_sc7280_driver);
322 module_exit(video_cc_sc7280_exit);
324 MODULE_DESCRIPTION("QTI VIDEO_CC sc7280 Driver");
325 MODULE_LICENSE("GPL v2");